Upload
vein
View
19.291
Download
2
Tags:
Embed Size (px)
Citation preview
112/04/12 1
VLSI Design and Layout PracticeVLSI Design and Layout PracticeLect5 – Stick Diagram & Scalable Lect5 – Stick Diagram & Scalable
Design RulesDesign Rules
Danny Wen-Yaw ChungDanny Wen-Yaw ChungInstitute of Electronic EngineeringInstitute of Electronic EngineeringChung-Yuan Christian UniversityChung-Yuan Christian University
Sept. 2008Sept. 2008
112/04/12 2 Wen-Yaw Chung/Chung-Yuan University VLSI Design
IC Layout Concept and Examples
I. Stick Diagram II. Design Rules III. Layout Verification
Ref: http://140.135.9.56/XMS/
112/04/12 3 Wen-Yaw Chung/Chung-Yuan University VLSI Design
112/04/12 4 Wen-Yaw Chung/Chung-Yuan University VLSI Design
112/04/12 5 Wen-Yaw Chung/Chung-Yuan University VLSI Design
A. Basic Concept 1. Based on the view point of IC layout, the
stick diagram can help us understand the circuit function and its geometrical location relative to other circuit blocks.
Legend:
contactmetal 2
metal 1
poly
ndiff
pdiff
VDD
in
VSS
out
■
112/04/12 6 Wen-Yaw Chung/Chung-Yuan University VLSI Design
A. Basic Concept 2. Although the stick diagram is an abstract
presentation of real layout, it can use graphical symbols or legend to allocate the circuit to 2-diomensional plane and reach the aim same as the physical layout does.
3. The stick diagram is similar to a backbone of the real layout but without the real size and aspect ratio of the devices, it still can reflect the real condition to layout of the silicon chip.
112/04/12 7 Wen-Yaw Chung/Chung-Yuan University VLSI Design
B. Notations of the stick diagram
112/04/12 8 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram Intermediate representation
between the transistor level and the mask (layout) level.
Gives topological information (identifies different layers and their
relationship) Assumes that wires have no width. It is possible
to translate stick diagram automatically to layout with correct design rules.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 9 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
1. When the same material (on the same layer) touch or cross, they are connected and belong to the same electrical node.
2. When polysilicon crosses N or P diffusion, an N or P transistor is formed. Polysilicon is drawn on top of diffusion. Diffusion must be drawn connecting the source and the drain. Gate is automatically self-aligned during fabrication.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 10 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
3. When a metal line needs to be connected to one of the other three conductors, a contact cut (via) is required.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 11 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram 4. Manhattan geometrical rule: When we use only vertical an
d horizontal lines In orthogonal to describe circuitry. Boston geometrical rule: The stick diagram also allows curve
s to describe circuitry. 5. In order to describe N/PMOS more completely, to add
n-well 、 P+ select 、 well contact and substrate contact are optional for 4-terminal notation.
112/04/12 12 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Conclusion
1. Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and layout.
2. Stick diagram uses different lines, colors and geometrical shapes to present circuit nodes, devices, and their relative location.
3. Stick diagram doesn’t include information about the accurate coordinates and sizes of device, the length and width of conductors and the real size of well region.
112/04/12 13 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Inverter Stick Diagrams
Basic layout
․ More area efficient layout
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 14 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS inverter described in other way.
VDD
in
VSS
out
CMOS Inverter Stick Diagrams
112/04/12 15 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Transmission Gate
The transmission gate Circuit schematic Stick diagram
112/04/12 16 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Stick DiagramsNAND/NOR
112/04/12 17 Wen-Yaw Chung/Chung-Yuan University VLSI Design
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
CMOS Stick DiagramsNAND
112/04/12 18 Wen-Yaw Chung/Chung-Yuan University VLSI Design
< Exercise 1 >
To draw the following circuitry by using a stick diagram
112/04/12 19 Wen-Yaw Chung/Chung-Yuan University VLSI Design
< Exercise 2 > To draw the stick diagram and the schematic for the following layout
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1
112/04/12 20 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Stick Diagrams[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫 EDA 聯盟 – 推廣課程 Chap.1
NOR
112/04/12 21 Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Inverter Mask Layout
Min. spacing andline width consideration
112/04/12 22 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Lambda-based Design Rules
Lambda design rules are based on a reference metric λthat has units of um.
All widths, spacing and distances are written in the form Value = m λ
Where m is scaling multiplier.<e.g.> λ= 1um w = 2 λ=2um s = 3λ=3um
112/04/12 23 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Lambda based design: half of technology since 1985. As technologychanges with smaller dimensions, a simple change in the value of canbe used to produce a new mask set.
All device mask dimensions are based on multiples of , e.g., polysilicon minimum width = 2. Minimum metal to metal spacing = 3
6
2
6
3
3
Lambda-based Design Rules
112/04/12 24 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Active Contact and Surround Rule
112/04/12 25 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Potential Problem - Misalignment
112/04/12 26 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Potential Problem – Short between Source and Drain
112/04/12 27 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Degree of anisotropy A = 1 – rlat/rvert
Where r respective etch rates
Physical Limitations
112/04/12 28 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rule (0)
Due to the photo resolution, concentration, temperature and reaction time of the chemical reagents, the layout should tolerate some errors caused by process environment.
In order to avoid the influence from process variation, the layout of the circuit schematics should follow the design Rule 。
112/04/12 29 Wen-Yaw Chung/Chung-Yuan University VLSI Design
The purpose of design rules
Ref. Jan M. Rabaey, et. al, © Digital Integrated Circuits 2nd Edition
Interface between designer and process engineer
Guidelines for constructing process masks Unit dimension: Minimum line width
scalable design rules: lambda parameter absolute dimensions (micron rules)
112/04/12 30 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rules(1)
Layout rules are used for preparing the masks for fabrication. Fabrication processes have inherent limitations in accuracy. Design rules specify geometry of masks to optimize yield and
reliability (trade-offs: area, yield, reliability). Three major rules:
Wire width: Minimum dimension associated with a given feature.
Wire separation: Allowable separation. Contact: overlap rules.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 31 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rules(2)
Two major approaches: “Micron” rules: stated at micron resolution. rules: simplified micron rules with limited s
caling attributes. may be viewed as the size of minimum feature. Design rules represents a tolerance which insur
es very high probability of correct fabrication (not a hard boundary between correct and incorrect fabrication).
Design rules are determined by experience.
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 32 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Terminology & Definition
Min. Width : The min. width of the line (layer) <Example> Wpoly(min.) = 0.5um
Min. Space : The min. spacing between lines with same material
<Example> Spoly-poly(min.) = 0.5um
112/04/12 33 Wen-Yaw Chung/Chung-Yuan University VLSI Design
<Min. Extension : The min. extension over different layers
<Example> Poly-gate extension over diffusion area = 0.55um
Min. Overlap : The overlap between different layers
<Example> Poly1 overlap Poly2 min. = 0.7um
Terminology & Definition
112/04/12 34 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Terminology & Definition
Max. area of the specific region. <Example> Bonding Pad Area, max. =
100um x 100um
112/04/12 35 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Conventional Layer Definition
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
112/04/12 36 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
IntraIntra--Layer Design RulesLayer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
Ref. Jan M. Rabaey, et. al, © Digital Integrated Circuits 2nd Edition
112/04/12 37 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
112/04/12 38 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
1
3 3
2
2
2
WellSubstrate
Select3
5
112/04/12 39 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 40 Wen-Yaw Chung/Chung-Yuan University VLSI Design
MOSIS Layout Design Rules
MOSIS design rules (SCMOS rules) are available at http://www.mosis.org.
3 basic design rules: Wire width Wire separation Contact rule
MOSIS design rule examples
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 41 Wen-Yaw Chung/Chung-Yuan University VLSI Design
III. Layout Verification
A. Definition DRC – Design Rule Check ERC – Electrical Rule Check LVS – Layout Versus Schematic LPE – Layout Parameter
Extraction
112/04/12 42 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
B. DRC(Design Rule Check) : => To check the min. line width and spac
ing based on the design rules.
C. ERC(Electrical Rule Check) : => To check the short circuit between P
ower and Ground, or check the floating node or devices.
112/04/12 43 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
D. LVS(Layout versus Schematic) : => To verify the consistency between Schematic and L
ayout. For example : to check the amount of transistor numbers, sizes of W/L.
E. LPE or PEX(Layout Parameter Extraction) : => From the database of layout, to extract the device
s with parasitics including effective W/L, parasitic capacitances and series resistance. The extracted file is in SPICE format and can be used for Post-Layout Simulation 。
112/04/12 44 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
F. SimulationsPre-Layout Simulation - before layout workPost-Layout Simulation – after layout work, post layout simulation will reflect more realistic circuit performance.
112/04/12 45 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
The complete design environment of Fill-Custom Design Design database – Cadence Design Framework IICircuit Editor – Text editor/Schematic editor (S-edit, Composer)Circuit Simulator – SPICE,TSPICE, HSPICELayout Editor – Cadence Virtuoso, Laker, L-editLayout Verification Diva, Dracula, Calibre, Hercules
112/04/12 46 Wen-Yaw Chung/Chung-Yuan University VLSI Design
Concluding Remarks Milestones technology in silicon era
Transistor Integrated Circuits CMOS Technology Key weapons in SOC era
Design Automation Design Reuse
Breakthrough techniques in design automation Simulation (e.g., SPICE, Verilog-XL, etc.) Automatic Placement and Routing (APR) Logic Synthesis (e.g., Design Compiler) Formal Verification Test Pattern Generation
It is EDA that pushes the IC design technology forward !
[Ref]: 教育部顧問室「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
112/04/12 47 Wen-Yaw Chung/Chung-Yuan University VLSI Design
[Ref.] John P. Uyemura, “Physical Design of CMOS Integrated Circuits Using L-EDIT”, PWS Publishing Company, 1995.
SCNA Layout Rules
112/04/12 48 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules
112/04/12 49 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules
112/04/12 50 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules
112/04/12 51 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules
112/04/12 52 Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules
112/04/12 53 Wen-Yaw Chung/Chung-Yuan University VLSI Design
LAB. 3
Set#1 – Stick Diagram Practice Set#2 – Reverse Engineering