Viterbi Decoder: Presentation #2

Omar Ahmad

Prateek Goenka

Saim Qidwai

Lingyan Sun

M1

Overall Project Objective:

Design of a high speed Viterbi Decoder

Stage 2: 26 Jan. 2004

Architecture Proposal

Design Manager: Yaping Zhan

Status Design Proposal (finalized) Architecture Proposal (done)

Final Algorithm Description Mapping of Algorithm into hardware High level simulation/emulation in Matlab Behavioral Verilog simulation and test bench

To be done: Floor Plan Gate Level Design Component Layout Chip Layout Spice Simulation of Entire Chip

18-525, Integrated Circuits Design Project

Viterbi Algorithm Description

Branch Calculation Unit

Add Compare Select Unit

Maximum Likelihood Path Search

Trace FIFO Trace Back Control Unit

Overview of Algorithm

18-525, Integrated Circuits Design Project

Aim: Retrieve data from the disk Algorithm based upon maximum likelihood detection

01000111, 01001111Viterbi

Decoder01100101, 00001111

BAD GOOD

Viterbi Algorithm DescriptionPseudo-Code

Step 1: Send it to the Branch and Compare Unit (BCU)• Subtract it with 16 constants C = [0 -1 -1 -2 1 0 0 -1 1 0 0 -1 2 1 1 0]• Square each result

Step 2: Send the results to Add Compare Select Unit (ACU)• Select minimum of 2 results, add using feedback loop and send to ML• Store position of minimum selected and send to trace back

Step 3: Maximum Likelihood Path Search (ML)• Find minimum value of all inputs• Find and store position

•Step 4: Trace Back•Go back along the path to find the correct input sequence

For each digit in the input sequence do:

18-525, Integrated Circuits Design Project

D

D

…

…

D

D

D

D

D D D D

…

…

………..…

C0 C1 C2 C3 Cn-1 Cn

………..

Control Logic

Input

Output

BCU

ACS

ML Search

FIFO & trace back

Input_valid

Clock

Vdd

Gnd

Output_valid

Reset

Viterbi Algorithm DescriptionFlow-chart

Branch and Compare Unit (BCU) Add Compare Select Unit (ACS)

18-525, Integrated Circuits Design Project

C0 C1 C2 C3

BCU

C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3

Input

ACS

Maximum Likelihood Path Search (ML)

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ML Search

Trace Back Unit

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D D D D D D D D

D D D D D D D D

D D D D D D D D

………………………………………………….

18-525, Integrated Circuits Design Project

Matlab Simulation

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Matlab Simulation (Test Results)

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Verilog Simulation

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Verilog Simulation (Test Result)

Match with Matlab Result

Questions?

18-525, Integrated Circuits Design Project