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Viterbi Decoder: Presentation #4
Omar Ahmad
Prateek Goenka
Saim Qidwai
Lingyan Sun
M1
Overall Project Objective:
Design of a high speed Viterbi Decoder
Stage 4: 9th Feb. 2004
Gate Level Design
Design Manager: Yaping Zhan
Status Design Proposal (finalized) Architecture Proposal (done)
Final Algorithm Description Mapping of Algorithm into hardware High level simulation/emulation in Matlab Behavioral Verilog simulation and test bench Gate level Design Floor Plan
To be done: Component Layout (10% done) Chip Layout Spice Simulation of Entire Chip
18-525, Integrated Circuits Design Project
Architecture/Floor Plan Revisions
Small change in our architecture. Instead of using subtractors, comparators are being used.
Floor Plan also to remain unchanged (until we have a better estimate using our component layouts)
18-525, Integrated Circuits Design Project
Is an 8 bit ripple carry adder really a better choice than an 8 bit carry look ahead adder ?
Concerns from last week…
18-525, Integrated Circuits Design Project
216 transistors
18-525, Integrated Circuits Design Project
Eight bit ripple carry adder
Critical Time Analysis of Ripple Carry
propagation for 8-bit ripple carry = 1.15 ns
18-525, Integrated Circuits Design Project
4 bit schematic of carry look ahead (8-bit has 480 transistors)
18-525, Integrated Circuits Design Project
4 bit ripple carry look ahead
propagation 8-bit carry look ahead = 1.12 ns
18-525, Integrated Circuits Design Project
Critical Time Analysis of Carry Look ahead
The choice is obvious…
8 bit Ripple Carry Adder
8 bit Carry Look Ahead Adder
Speed (ns.) 1.15 1.12
Transistors 216 480
18-525, Integrated Circuits Design Project
18-525, Integrated Circuits Design Project
Original Floorplan
ML Search
ACS Unit
BCU Unit
TB Unit
650
350
All units in microns
Buffering/Routing
We thought about alternatives to improve ratio
Floor Plan (alternative ideas) L shaped
ML Search
AC
S U
nit
BCU Unit
TB Unit
Bu
ffer
ing
/Ro
uti
ng
BCU Unit
AC
S U
nit
425
310
18-525, Integrated Circuits Design Project
Floor Plan (alternative ideas)
Break up
450
ML Search
ACS Unit
BCU Unit
TB Unit
Buffering/Routing
BCU Unit
ACS Unit
325
18-525, Integrated Circuits Design Project
Schematic: top level
18-525, Integrated Circuits Design Project
18-525, Integrated Circuits Design Project
Yes, but we need to go under the
hood!!
18-525, Integrated Circuits Design Project
Schematic: Top level BCU
Schematic: BCU cell
18-525, Integrated Circuits Design Project
18-525, Integrated Circuits Design Project
Schematic: ACS unit
18-525, Integrated Circuits Design Project
Schematic: ML search
18-525, Integrated Circuits Design Project
Schematic: Trace Back Unit
18-525, Integrated Circuits Design Project
Verilog Simulation: Top Level
18-525, Integrated Circuits Design Project
Critical Path
The critical path lies within the ACS_unit.
Adder
Comparator
Mux
The delay would be dominated by the adder and the comparator, therefore in worst case the critical path would be the delay of 2 8- bit adders
Approx clock speed = ½*delay = (1/1.15*2) = approx 400 Mhz
1-bit adder Layout
18-525, Integrated Circuits Design Project
18-525, Integrated Circuits Design Project
Questions?
