Program/Erase Speed, Endurance, Retention, and Disturbance

Characteristics of Single-Poly Embedded Flash Cells

Seung-Hwan Song, Jongyeon Kim, and Chris H. Kim

University of Minnesota, Minneapolis, MN

songx278@umn.eduwww.umn.edu/~chriskim/

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Purpose• Compare the characteristic of various

single-poly embedded flash cells

• Find a well-balanced single-poly

embedded flash cell configuration in

terms of program/erase speed,

endurance, retention, and disturbance

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Outline

• Motivation to Single-Poly E-Flash

• Single-Poly E-Flash Cell Configuration

• Test Chip Measured Data

– P/E Speed, Endurance, Retention

– Disturbance and coupling

• Conclusion

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Embedded Flash in System-on-Chips

• Secure non-volatile memory capable of managing circuit variability and reliability issues

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Embedded Flash Cell Comparison

• Single-poly embedded flash features– No process overhead compared to standard CMOS– Lower writing voltage, larger cell size, lower density

[1] H. Kojima et al., IEDM 2007, [2] J. Yater et al., IMW 2009[3] S. Song et al., VLSI 2012

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Single-Poly Eflash Cell Basic

• Three back-to-back core devices (M1-M2-M3)• FG can store charges during power-off periods

J. Raszka et al., ISSCC 2004

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Various Single-Poly Eflash Cells

• Various M1-M2-M3 device combinations• Not fully compared yet

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Single-Poly Eflash High Voltage Issue

• 3~4X P/E voltage than the nominal I/O supply• Extremely large cell (cell-by-cell HVS)• Unselected cells can be disturbed

J. Raszka et al., ISSCC 2004 B. Wang et al., TED 2007

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Single-Poly 5T Eflash (N-channel)

• Compact cell size (8.62μm2)• Single WL erase/program• Program inhibition via self-boosting

– Investigation of the program disturbance (this work)

S. Song et al., VLSI 2012

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Single-Poly 5T Eflash (P-channel)

• PMOS read device (M3) and select TR’s (S1, S2)• Similar operation principles to N-ch. 5T eflash

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Single-Poly 5T Eflash Combinations

• Different prog./erase, endurance, retention char.

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Test Chip Die-Photo & Features

• Two test chips in 65nm standard logic process

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Measured Erase/Program Speed

• P-ch.-1 shows fastest erase/program speed

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P-ch.-1: Fast Erase/Program Speed

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P-ch.-2: Slow Erase Speed

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P-ch.-3: Slow Erase/Program Speed

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Measured Endurance

• Larger variation in the erased cells for P-ch.-2, 3– Due to the depletion cap. variation of erase TR (M2)– Reducing the sensing margin for higher P/E cycles

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Measured Retention

• Pre-cycle: 27°C, fixed writing voltage (-7.6V)• P-ch.-3 shows least cell VTH shift in both cases

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Physical Explanation of Retention Char.

• P-ch.-3 consists of a coupling device having p+ poly where the Fermi level is near the valence band edge (less conduction band electrons)

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Measured Program Disturbance

• Boosted channel potential is estimated as ~4V• Leakage current from the boosted channel is not

severe until ~1s

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Measured Coupling Effect

• Tight BL pitch compared to other prior single-poly• Minimal mean and sigma change of cell VTH

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Multi-Level Cell Programming Test

• MLC programming test sequence – P3 state is programmed using a single pulse– P2 and P1 states are sequentially programmed using

balanced ISPP with a 0.1V step increment• Result of negligible disturbance and FG coupling

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Conclusions

• Moderate-density single-poly eflash– Cost effective embedded NVM for SoC– No process overhead beyond standard CMOS

• Various single-poly eflash topology– Cell transistor and doping types– Program/Erase speed, endurance, retention,

and disturbance issues• Optimal balance: N-channel 5T eflash cell

having a PMOS-PMOS-NMOS topology

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References• R. Strenz, “Embedded Flash Technologies and their Applications: Status & Outlook,” IEEE Int.

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