A 32Gb/s Digital-Intensive Single -Ended PAM-4 Transceiver ...people.ece.umn.edu/groups/VLSIresearch/papers/2020/ISSCC20_PAM4_slides.pdfInternational Solid-State Circuits Conference

22.4: 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor

© 2020 IEEE International Solid-State Circuits Conference 1 of 25

A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed

Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer

and an In-Situ Channel-Loss Monitor

Po-Wei Chiu and Chris H. Kim

Dept. of ECE, University of Minnesota, Minneapolis, MN



Outline• Introduction

• Time Based PAM-4 Decision Feedback Equalizer

• In-situ Channel Loss Monitor

• 65nm Test Chip Results

• Summary



Voltage-based vs. Time-based DFE

CLKPhase Detect

or

Pros

Cons

Scalable to large number of taps, low power consumption

Moderate speedHeadroom issues, limited taps, large power consumption

Ultra high speed

Time-based DFEVoltage-based DFECurrent mode logic

DifferentialInverter delay line

Single-endedCircuit

w1 w2 wN

w1 wN-1

-wN-w2

DFE: Decision Feedback Equalization

VRX(t) Σ

w1w2wN

Z-1 ......

Z-1 Z-1

x[n]Slicer



Memory Interface Trends

T. Hollis, Solid-State Magazine, 2019

• Single-ended signaling, lower supply voltage• Data rate higher than 16 Gb/s• Multi drop memory bus with more reflection

Time-based DFE becoming an attractive alternative



Pulse Amplitude Modulation (PAM)

• PAM-4 overtaking NRZ but requires more accurate conversion from voltage signal to time delay signal

VTH,H

VTH,M

VTH,L

V11

V10

V01

V00T11 T10 T01 T00

TTH,H TTH,M TTH,L

VTH

T1 T0

TTHV1

V0

NRZ

PAM-4







• Summary



Differential Voltage to Time Converter

• Two path delays change with opposite polarity• Non-linearity cancelled out by subtracting delays

DVTC: Differential VTC

Vin

CLKΔT=

TRX-TREF

RX

REF

EN

VTC (Prior art)

CLKΔT=

TRXP-TRXN

RXP

RXN

ENb EN

DVTC (This work)Vin

D=0 RXP RXN

D=1 RXN RXP

D=0 RX REF

D=1 RXREF



• Delay range improves from 42ps to 70ps

Vin

CLKΔT=

TRX-TREF

RX

REF

EN

VTC (Prior art)

CLKΔT=

TRXP-TRXN

RXP

RXN

ENb EN

DVTC (This work)Vin

0 0.20

70

ΔT (p

s)0.4 0.6 0.8 1.0 1.2

605040302010

0 0.20

70

ΔT (p

s)

Vin (V)0.4 0.6 0.8 1.0 1.2

605040302010

65nm GP, post-layout, 25°C

Vin (V)

65nm GP, post-layout, 25°C

42ps range w/ poor linearity

70ps range w/ good linearity

Differential Voltage to Time Converter

DVTC: Differential VTC



NRZ Signal Comparison

• Threshold delay generated by VTC in reference delay line

DFE

Δt=TRX-TTH

CLK

TRX

TTH

EN

Vin

V1

V0 TTH TRXN

TTHTRXN



PAM-4 Signal Comparison

• Simple buffer can generate the different threshold delays for PAM-4. Separate DAC circuit not required.

DFETTH

Δt=TRXP-TRXN+TTH

CLK

TRXP

TRXN

ENb EN

Vin

V11

V10 TRXPTRXN

TRXPTRXN

TTH



PAM-4 Signal Comparison

• Simple buffer can generate the different threshold delays for PAM-4. Separate DAC circuit not required.

DFETTH

Δt=TRXP-TRXN+TTH

CLK

TRXP

TRXN

ENb EN

Vin

V11

V10 TRXPTRXN

TRXPTRXN

TTH



PAM-4 Time-Based Receiver

From DVTC,Even

From DVTC,Odd

TBUFPDTW1X1 FF

TREF,H T-W2X2

TBUF PDTW1X1 FF

TREF,H T-W2X2

W2

W2

W1

W1

PAM-4 Decoder

+ Eye Monitor

HM

L

HM

L

RXN,E

RXP,E

RXP,O

RXN,O

33

• Half-rate operation• 12 delay lines and 6 phase detectors (PD)




From DVTC,Even

From DVTC,Odd

TBUFPDTW1X1 FF

TREF,H T-W2X2

TBUF PDTW1X1 FF

TREF,H T-W2X2

W2

W2

W1

W1

PAM-4 Decoder

+ Eye Monitor

HM

L

HM

L

RXN,E

RXP,E

RXP,O

RXN,O

33

V11

V10

V10

V01

V01

V00

RXPRXN

RXPRXN

RXPRXN

RXNRXP

RXNRXP

RXP RXN




From DVTC,Even

From DVTC,Odd

TBUFPDTW1X1 FF

TREF,H T-W2X2

TBUF PDTW1X1 FF

TREF,H T-W2X2

W2

W2

W1

W1

PAM-4 Decoder

+ Eye Monitor

HM

L

HM

L

RXN,E

RXP,E

RXP,O

RXN,O

33

V11

V10

V10

V01

V01

V00

RXPRXN

RXPRXN

RXPRXN

RXNRXP

RXNRXP

RXP RXN

RXP RXN

RXPRXN

RXPRXN

RXNRXP

RXN RXP

RXP RXN




From DVTC,Even

From DVTC,Odd

TBUFPDTW1X1 FF

TREF,H T-W2X2

TBUF PDTW1X1 FF

TREF,H T-W2X2

W2

W2

W1

W1

PAM-4 Decoder

+ Eye Monitor

HM

L

HM

L

RXN,E

RXP,E

RXP,O

RXN,O

33

V11

V10

V10

V01

V01

V00

RXPRXN

RXPRXN

RXPRXN

RXNRXP

RXNRXP

RXP RXN

RXP RXN

RXPRXN

RXPRXN

RXNRXP

RXN RXP

RXP RXN

RXP RXN

RXPRXN

RXPRXN

RXNRXP

RXN RXP

RXP RXN

H

M

L



Test Chip Diagram of PAM-4 Transceiver

8GHz Clock Generator

PRBS Generator

LSBMSB

3-Tap FFE

(half-rate)

Transmitter

DVTC

2-TapTB-DFE

EVENODD

PAM4 Decoder/ In-situ

Eye monitor

2-TapTB-DFE2-Tap

TB-DFE

Receiver Cha

nnel

DOUT DIN1

DIN2

CLK, CLKICLM

ICLM

In-situ Channel

Loss Monitor

Differential Voltage-to-Time

Converter

MUX

FF FF FF

FF FF FF

DIN2 8Gb/s

CLK (8GHz)

DIN1 8Gb/sCLK

(8GHz)

MSB

DOUT

2X

LSB

1X0X~15X

• RX: DVTC, PAM-4 TB-DFE, and BER monitor• TX: PRBS, clock generator, FFE, and driver• In-situ channel loss monitors on both sides







• Summary



Proposed Channel Loss Monitor

• Measure the toggling frequency of comparator output while sweeping reference voltage

Channel Loss Monitor

ChannelZTX

TXZRX

RX

VREF,TX

VREF,RX

fTX

fRX

/NfOUT

+-

+- SEL



Measured Frequency vs. Voltage

• Frequency decreases at higher data rates

0 0.1 0.20

1

2

3

4

Voltage (V)

Freq

uenc

y (M

Hz)

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

7GHz

1GHz

TX

RX

TXRX VREF (V)

f OUT

TX

RX

VTX

VRX

VCOM

10log|T21|2 |T21|VTX

VRX

5%



Measured Channel Loss

• Small discrepancy can be attributed to random digital pattern generated by PRBS (vs. sinusoidal input)

0 1 2 3 4 5 6 7 8-14

-12

-10

-8

-6

-4

-2

0

Loss

(dB

)

Frequency (GHz)

EM simulationProposed monitor







• Summary



BER Bathtub and Time-Domain Eye Diagram

w/o DFE

65nm GP, 1.2V, 25ºC, 32Gb/s, 8GHz

1E-12

Bit

Erro

r Rat

e

Phase (UI)-0.2 0-0.3 -0.1 0.2 0.30.1

w/ DFE

1E-9

1E-6

1E-3

X-axis: Phase (time)Y-axis: Time offset (time)



Die Photo and Feature Summary

RX72

µm89µm

Technology 65nm CMOS

Data Rate 32 Gb/s

Channel Loss 11.6dB@8GHz

BER

Circuit AreaTX: 31x72µm2

Power Efficiency 0.97 pJ/b

VDD 1.2V

<10-12

RX: 89x73µm2

TX

31µm73

µm



Performance Comparison Table

Signaling Duobinary

Technology 65nm

TRX Area

Voltage 1.05V

Data Rate 7 Gb/s

RX Circuit Type

1-Tap DFE

TRX Power Efficiency

JSSC’14 [1]

0.56 pJ/b

RX Equalization

Channel Loss [email protected]

BER <1E-12

0.0333 mm2

ISSCC’19 [2]

PAM-3

28nm

0.6V

27 Gb/s

1-Tap DFE

1.03 pJ/b

20mm

<1E-12

0.0135 mm2

ISSCC’16 [3]

Muti-Band

28nm

1.2V

10 Gb/s

Self-Equalization

0.95 pJ/b

6dB@6GHz

<1E-12

0.01 mm2

This workPAM-4

65nm

1.2V

32 Gb/s

2-Tap DFE

0.97 pJ/b

11.6dB@8GHz

<1E-12

0.009 mm2

JSSC’18 [4]NRZ

65nm

0.8V

12.5 Gb/s

2-Tap DFE

0.49 pJ/b

[email protected]

<1E-12

0.0094 mm2

Voltage-Based Voltage-Based Voltage-Based Time-BasedTime-Based

Single/Differential Single-Ended Single-Ended Differential Single-Ended Single-Ended

[1] S. Lee, et al., JSSC, 2014. [2] H. Park, et al., JSSC, 2019. [3] W. Cho, et al., ISSCC, 2016. [4] I. Yi, et al., JSSC, 2018.



Summary

• Digital-intensive PAM-4 time-based DFE

• Differential voltage-to-time converter with enhanced linearity and dynamic range

• In-situ channel loss monitor

Documents

A 32Gb/s Digital-Intensive Single -Ended PAM-4 Transceiver ...people.ece.umn.edu/groups/VLSIresearch/papers/2020/ISSCC20_PAM4_slides.pdfInternational Solid-State Circuits Conference