A Fully Integrated 40pF Output Capacitor Beat-Frequency ...people.ece.umn.edu/groups/VLSIresearch/papers/2018/ISSCC18_LDO_slides.pdf18.5 A Fully Integrated 40pF Output Capacitor Beat-Frequency-Quantizer-Based

18.5 A Fully Integrated 40pF Output Capacitor Beat-Frequency-Quantizer-Based Digital LDO with Built-In Adaptive Sampling and Active Voltage Positioning

© 2018 IEEE International Solid-State Circuits Conference 1 of 30

A Fully Integrated 40pF Output Capacitor Beat-Frequency-Quantizer-Based Digital LDO with Built-In Adaptive Sampling and

Active Voltage Positioning

Somnath Kundu1, Muqing Liu1, Richard Wong2, Shi-Jie Wen2, Chris H. Kim1

1Dept. of ECE, University of Minnesota, Minneapolis, MN2Cisco Systems, San Jose, CA



Outline• Background: Analog vs. Digital LDO

• Time based Digital LDO

• Beat-Frequency Quantizer

• Active Voltage Positioning (AVP)

• 65nm Test Chip Results

• Conclusion



Analog vs. Digital LDO

Ref: Y. Okuma, CICC’10

• Benefits of digital implementation: Scalability with technology Low voltage operation DVFS Loop parameters controlled digitally

Analog LDO Digital LDO

VREF

VDDH

VDDL

ZL

+

-Amp

Analog voltage VREF

Digital control

CKS

Digital bits

Voltage quantizer

VDDH

VDDL

ZL



Digital LDO ArchitecturesSingle-bit Quantizer

Low complexityΧ Slow responseΧ Poor stability

Y. Okuma, CICC’10S. Nasir, ISSCC’15

Multi-bit Quantizer

Χ High complexityFast response Good stability

D. Kim, ISSCC’16L. Salem, ISSCC’17

VREF +-

ShiftReg.

CKS

1-bitVDDH

VDDL

ZL

VREFDig.

Control

CKS

n-bit

ADC

VDDH

VDDL

ZL








• Conclusion



Digital control

VREF CKREF

CKOUT

Voltage to time

CKS

Time Quantizer

NOUT

VDDH

VDDL

ZL

Time based Digital LDO

• VCO followed by a time-quantizer• Fully digital voltage quantization• 1st order quantization noise shaping



Conventional Linear Time-Quantizer

NOUT

CKOUT

CKREF CKs/N Cou

nter

RST

• NOUT = # of CKOUT periods within a sampling period• Constant sampling period

CKS

CKOUT

5MHz

250MHz 225MHz

NOUT=50 NOUT=45



Conventional Linear Time-QuantizerCount

freqvolt

fREF

VOUT VREF

fOUT

Count error

N

NOUT

Const. slope (N/fREF)

steady-stateoperating point

Trade-off between speed and power/stability

• NOUT proportional to CKOUT• |N-NOUT| provides amount of pMOS switching• Large N improves resolution but slow response

fOUT

fREF

= fOUTfREF

N

constant

NOUT

CKOUT

CKREF CKs/N Cou

nter

RST

fREF

N








• Conclusion



Proposed Beat Frequency Time-Quantizer

NOUT

Cou

nter

CKs

CKREF

CKOUTD Q RST

CKS

CKREF

CKOUT

5MHz 25MHz

250MHz

245MHz 225MHz

NOUT=50 NOUT=10

• D-flip-flop acts as a beat frequency generator• Larger frequency difference generates higher fS

B. Kim, VLSI’15 (BF-PLL)S. Kundu, CICC’15 (BF-ADC)This work (BF-LDO)



Proposed Beat Frequency Time-Quantizer

• When | VREF – VOUT | is larger:‒ pMOS switching frequency becomes faster‒ pMOS switching amount increases due to large |N - NOUT|

fOUT

fREF

fREF fOUT

=fREF

fREF fOUT

NOUT

Cou

nter

CKs

CKREF

CKOUTD Q RST

Count

freqvolt

fREF

VOUT VREF

fOUT

Count error

N

NOUT

Improved switching

gain



Beat Frequency for Adaptive Sampling

VREF

VDDL

CKS

ILOAD

Freq VREF VDDL

High fS

• Fast settling• low droop

• High resolution• Low dyn. Power• Good stability

Low fS








• Conclusion



200mV100mV

100mV

w/o AVP

VDD

ILOAD


Ref: K. Yao, APEC’2004



120mV

w/ AVP

VDD

ILOAD

100mV100mV


Ref: K. Yao, APEC’2004



VREFVDDL

2fREF/(NKvco)

ILOAD

Count

volt

N

BF Quantizer

A

AB B

VREF


• BF quantizer provides inherent AVP• Voltage position is set by N








• Conclusion



VREF

+-N

VDDH

VDDLCKREF

Gain=KVCO

Programmable ILOAD

(0 - 400mA) 40pF

CKOUT

-1

Beat-freq.Quantizer

0SEL_Q

x1024

Baseline

10bPIControl

Digital control

Switch Driver

Polarity detector

CKS

NOUT

LinearQuantizer

(for testing)

Complete Block Diagram of Digital LDO

• Both linear and BF quantizers are present for performance comparison



BF Quantizer Design

Counter

D Q

D Q

RST

CKS

NOUT

CKOUT

CKREFDOUT

• An 8-bit counter counts the number of CKREF periods in a beat period

• Counter resets at the beginning of each beat period

RST

CKS

CKREF

CKOUT

NOUT

DOUT 1 2 3 4 5 65

5 6



PMOS Switch Array and Driver

ILOAD

ILOAD

I LOA

D c

ontr

ol

Switc

h dr

iver

C9-C

0 1024 PMOS Switch Array

C8

C7

C9

C6

32X16X

8X 4X

C5

C4

2X

1X

Dummy or C3-C0

Dum

my

or

C3-C

0

• Uniformly distributed layout for matching• Equal loading for all bits (C9-C0) using dummies



VCO Schematic

400

350

300

250

200

150

Mea

s. F

req.

(MH

z)

0.6 1.20.8 1Vctr (V)

1100001000

00000

VDDH =1.2V

Vctr

Fine tuning

Coarse tuning

VDDH

1 2 5

• Coarse tuning: wide range of input/output voltage• Fine tuning: compensates any mismatch between VCO pair



65nm Chip Micrograph



Measured Transient Response: ILOAD step

• Higher sampling frequency during ILOAD transition

• 108mV droop and 148mV overshoot for 50mA ILOADstep



• 5x droop and 25x settling time for baseline

Measured Transient Response: ILOAD step



0

10

20

30

40

50

0

100

200

300

400

500

600

700

10 20 30 40 50 60 70ΔILOAD (mA)

ΔT: 0.25μsVDDH : 1V

VREF : 0.8VVolta

ge d

roop

, ΔV

(mV)

Settling time, T

s (μs)

ProposedBaseline

Proposed

Baseline

0

10

20

30

0

100

200

300

400

500

600

0 1 2 3ILOAD rise time, ΔT (μs)

ILOAD: 20mA 70mAVDDH : 1V

VREF : 0.8V

Volta

ge d

roop

, ΔV

(mV)

Settling time, T

s (μs)

Proposed

Proposed

Baseline

Baseline

Voltage Droop and Settling Time Measurements

• ∆V improvement: 5X – 10X• Ts improvement: 20X – 35X

• ∆V improvement: 1.5X – 4X• Ts improvement: 15X – 30X



LOAD

DDL

DDH

DDL

REF

REF

REF

REFREF

REF

LOAD

REF

REF

REF

DDH

Measured Line and Load Regulation

• Line regulation for VREF > 0.4V• Load regulation for 10x variation in ILOAD



Active Voltage Positioning Measurements

Weak AVP DC regulation=4%

Moderate AVP DC regulation=8%

Strong AVP DC regulation=15%



92

94

96

98

100

0 20 40 60 80 100

Curr

ent e

ffici

ency

(%)

ILOAD (mA)

VREF=0.5VVREF=0.7V

VREF=0.9V

VDDH =1V-40

-30

-20

-10

0

0.01 0.1 1 10 100

PSRR

(dB)

Frequency (MHz)

VDDH =1V-dc + 50mVpp SineVREF =0.8VILOAD=40mA

Measured Current Efficiency and PSRR

• Current efficiency >93% for 10-100mA ILOAD with max of 99.5%

• Low frequency PSRR of -38dB



# From oscilloscope waveform *Without CLOAD **FOM=CLOADΔV*IQ/(ΔILOAD)2. Smaller FOMs are better

Nasir, ISSCC’15

Lee,ISSCC’16

Salem,ISSCC’17

Kim, ISSCC’17 This Work

Process 130nm 28nm 65nm 65nm 65nm

Architecture Shift Reg Shift Reg+ADC SAR ADC Event- driven ADC VCO based ADC

Adaptive sampling/ AVP Yes / No No / No No / No Yes / No Yes / Yes

V LDO_IN (V) 0.5 – 1.2 1.1 0.5 1 0.45 1 0.6 – 1.2

V LDO_OUT (V) 0.45 – 1.14 0.9 0.3 – 0.45 0.4 – 0.95 0.4 – 1.1

Max .ILOAD (mA) 4.6 200 2 3.36 100

IQ (mA) 0.024 – 0.22 0.11 0.014 0.08 – 0.26 0.1 – 1.07

CLOAD (nF) 1 23.5 0.4 (Integrated) 0.1 (Integrated) 0.04 (Integrated)

Max current efficiency (%) 98.3 99.94 99.8 99.2 99.5

∆V, Ts @ ∆ILOAD90mV,1.1μs@

1.4mA120mV,40μs#

@180mA40mV,0.1μ[email protected]

34mV.11.2μ[email protected]

108mV,1.24μs@50mA

Area (mm2) 0.355 0.021 0.0023* 0.03* 0.0374

FOM (ps)** 10100 9.57 199 20 1.38

– –

Performance Comparison Table



Conclusion

• A fully integrated digital LDO using VCO basedtime quantization

• Adaptive sampling clock utilizing beat-frequency

• Built-in active voltage positioning

• Measured max current efficiency is 99.5% withFOM of 1.38ps in 65nm CMOS

Documents

A Fully Integrated 40pF Output Capacitor Beat-Frequency ...people.ece.umn.edu/groups/VLSIresearch/papers/2018/ISSCC18_LDO_slides.pdf18.5 A Fully Integrated 40pF Output Capacitor Beat-Frequency-Quantizer-Based