Symposia on VLSI Technology and Circuits

Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping Points

Chen Zhou1, Richard Wong2, Shi-Jie Wen2, and Chris H. Kim1

1 University of Minnesota2 Cisco Systems, Inc.

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Electromigration (EM) in Power Grid

• IR drop increases due to EM in power grid

• Redundant current paths exist in power grid

• Failure time and location hard to track

Slide 1

1.20V 1.19V

1.19V 1.18V

1.20V 1.10V

1.19V 0.90Vvoids

Before EM After EM

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Previous Work on Power Grid EM

VDDVSS

B. Li, IRPS 2018 (IBM)

• Total resistance of 3x2 test

structure monitored

• Resistance shifts indicate EM

failure events

• Limitation: Simplified

structure, failure location

can only be pinpointed using

SEM, large test area due to

pads

Slide 2

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Previous Work on Voltage Tapping

Slide 3

F. Chen, IRPS 2015 (IBM)

• Via taps enable resistance measurement for each wire segment

• Failure location can be pinpointed based on resistance shift

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Proposed Power Grid EM Test Structure

• 9x9 M4-M3 “pseudo” power grid with three voltage connection points

(A,B,C)

• Voltage tapping through top and bottom vias

M3

M4

A

B

C

Connection to IO pad

20μm

20μm

0 9 18 27 36 45 54 63 72

1 73

2 74

3 75

4 76

5 77

6 78

7 79

8 17 26 35 44 53 62 71 80

M3

M4V(M4)

V(M3)

0.1µm

0.1µm

Voltage tapping at every intersection,

above and below via

Slide 4

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Voltage Drop Across Wire and Via

• Voltage drop across each via, vertical and horizontal wire segment

measured by voltage tapping

Slide 5

M3

M4 Tap #1

Tap #2

Via

0.1um

0.1umM4

Tap #1

M4 segment

Tap #2

20μm

M3

Tap #1

M3 segment

Tap #2

20μm

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65nm EM Test Chip Overview

• IO device based transmission gates used for on-the-fly voltage tapping

• Circuits >400μm away from heaters to protect from high temp.

>400μm

260μm

26

0μ

m

180μm18

0μ

m

Heater #1 Heater #2 Heater #3

Scan

chain (1 bit)

Vsense

A

B

C

Tapping voltages

TX gates

Scan Clock

Scan Data

x162

Slide 6

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Die Photo and Test Setup

162 tapping

voltages

260μm

180μm

Heating

area

Scan, TX gates

• Temperature chamber:

– Measure heater TCR before EM test

– Ambient temperature set to 0 ºC to keep control circuits cool during test

Slide 7

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Temperature Coefficient of Resistance (TCR)

• Excellent linearity between temperature and heater resistances

• Trend lines extended to target stress temperature of 350ºC

Slide 8

260μm

26

0μ

m

Heater #1

Heater #2

Heater #3

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Heater Power Dynamic Control

• Heater temperature maintained at 350ºC during measurements

• Heater current direction switched every minute to prevent EM in heaters

Heating up to 350ºC

Start stress

Voltage sensing (13 sec)

Hold for 60 seconds

Switch current direction

Hold for 60 seconds

Voltage sensing (13 sec)

Switch current direction

Heater TCR extract

Slide 9

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Heater Temperature Log

• Temperature reaches target in seconds compared to minutes in oven

• Control loop adjusts heater current every 0.83 seconds

Slide 10

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Initial Voltage Map Measurement

• 162 node voltage samples voltage drop across entire power grid

• Largest current density near voltage connection points A, B, C

M3

M4

M3M4

M4M3

V(+)

V(+)

V(-)

A

B

C

Slide 11

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EM Failure Location Analysis

• Largest shift indicates failure location

• Resistance shift not instantaneous (i.e. gradually changes over minutes)

350ºC, 10mA, A+BC, Node #31

South

Via

North

West

East

N

S

W E

After EM

Fresh

V(-)

V(-)

Slide 12

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Total Power Grid Resistance and Voltage Drop Traces

Slide 13

• Stress mode: constant current mode constant voltage mode

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Failure and Healing Types

• Both abrupt and progressive

failures observed

• Temporary healing also observed:

– Electromigration

– Mechanical stress

• Voltage drop traces provide better

insight than resistance traces

Slide 14

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EM Healing Observations

• Voltage fluctuation implies stress and healing cycles

• Healing can happen either early or late

• Redundant current paths believed to be the reason for healing

Slide 15

Chip #8 Chip #6

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First EM Failure Location

• Three current stress modes applied on multiple chips

• First failure always near negative voltage terminal: EM tensile stress

Slide 16

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EM Failure Rates

• Constant current phase: slow fast (due to current density increase)

• Constant voltage phase: failure rate reduces due to less current

Slide 17

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Failure Order

• Failures located across entire power grid

• Failure order unpredictable except for the early failures

Slide 18

First half

failures

Second half

failures

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Failure Order Variation Between Chips

• Early failures occur near the negative voltage terminal or edges

• No strong correlation of test data between chips

Slide 19

*Only first 5 failure

locations shown

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Summary

• Voltage tapping technique used to tracking real-time EM failures in

“pseudo” power grid

• Insights:

– Early failures occurs at negative voltage terminal or edges of grid

– Failure rate increases after early failure due to higher current density

– Healing was repeatedly observed during stress due to redundant current paths

– Failure order is unpredictable except for early failures

• Suggestions for future EM test chip design:

– Include both VDD and GND grids

– More voltage connection points

– Support different stress modes such as pulsed DC stress

Slide 20