Symposia on VLSI Technology and Circuits

Statistical Characterization of Radiation-Induced Pulse Waveforms and Flip-Flop Soft Errors in 14nm Tri-Gate CMOS Using a Back-

Sampling Chain (BSC) Technique

Saurabh Kumar1, M. Cho2, L. Everson1, H. Kim1, Q. Tang1, P. Mazanec1, P. Meinerzhagen2, A. Malavasi2, D. Lake2, C. Tokunaga2, H. Quinn3,

M. Khellah2, J. Tschanz2, S. Borkar2, V. De2 and C. H. Kim1

1 University of Minnesota, Minneapolis, MN2 Intel Corporation, Hillsboro, OR

3 Los Alamos National Laboratory, Los Alamos, NM

kumar175@umn.edu

This research was, in part, funded by the U.S. government. The views and conclusions contained in this documentare those of the authors and should not be interpreted as representing the official policies, either expressed orimplied, of the U.S. government

Outline

• Motivation

• Back-sampling chain (BSC) technique

• 14nm test-chip and board design

• Neutron irradiation test results

• Strike pulse re-construction results

• Conclusion

Slide 1

Slide 2

Charge

collection

S

G

Fin

D

G

S D

Charge

collection

Technology (nm)65 45 32 28 14

FIT

/Mb

(L

og

Sc

ale

)S. Lee et. al. IRPS 2015

Planar Finfet

High energy neutron

Alpha particle

Thermal neutron

Technology (nm)65 45 32 28 14

FIT

/Mb

(L

og

Sc

ale

)S. Lee et. al. IRPS 2015

Planar Finfet

High energy neutron

Alpha particle

Thermal neutron

• Device level soft errorrate has been decreasingwith scaling

Soft Error: Planar vs. Tri-Gate

G

10nm14nm

Smaller cross-section

S D

Narrower path

Scaling Impact on SER in Tri-Gate

Slide 3

• Lower SER with tri-gate scaling

‒ Taller/narrower fins, higher resistance

‒ Smaller cross-section

Slide 4

• Lower per-transistor SER

• Higher transistor count, lower VDD ���� increasedchip-level SER

• Challenge: Collecting statistically significantamount of data in limited beam time

Tra

ns

isto

r d

en

sit

y

(MT

r / m

m2)

100

101

102

103

‘07

Year of production

‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ‘17 ‘18

45nm

32nm

22nm

14nm

10nm Su

pp

ly V

olta

ge

(a.u

.)0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Scaling Impact on SER in Tri-Gate

����

☺☺☺☺

1 1

Vn

od

e

Time

Trip point of next stage

VDD

Vn

od

e

Time

Flipping threshold

VDD

To slave

Clk

Clk’

Clk’

Clk

Clk

D01

Logic SET vs. Sequential SEU/MBU

Slide 5

Flop storage nodeCombinational logic path

Circuit Dependencies

Slide 6

• For higher SER sensitivity:

- Irestore

- Istrike

- Cnode

- Vsw

: High VT , smaller size (N1): High flux/LET (radiation parameter): Small fan-out, device size: High VT , smaller device (P2)

1 Vnode

Cnode

Istrike

Irestore

1

VswN1 N2

P1 P2

Technique #1: Current Starved Buffers

Slide 7

• Starved buffer chain: High sensitivity

Long chain of current starved buffers: detection circuit

Technique #1: Current Starved Buffers

Slide 8

• Alternate starving:

SER strike

VPO

VNO

VPE

VNE VNO VNE

VPO VPE

• Analog bias knobs:Tunable resolution and sensitivity

Lower Irestore, lower Vsw

0.2 0.4 0.6 0.8

4

8

12

20

Cri

tica

l ch

arg

e

(Qc

rit, n

orm

ali

zed

)

Voltage (V)

1x INV, TT, 27°C

0

16

Higher sensitivity

Standard chain

This work

Technique #2: Back-Sampling Chain

Slide 9

• Later stage rising edgeback-samples previousstage falling edge

SER strike

'0''0''0' '0' '0'

'0''0''0''0''0'

'1' '1' '1' '1' '1'

Time

Sta

ge

Ou

tpu

t

'0'

'0'

'0'

'0'

'0'

'1''1'

'1'

'1'

'1'

# of 0's indicate original pulse width

'0'

'0'

VPO

VNO

VPE

VNE VNO VNEN2

VPO VPE

Example: Short vs. Long Strike Pulse

Slide 10

Time

Sta

ge O

utp

ut

'1'

'1'

'1'

'1'Unsampled original bits

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0'

'0''1'

'1'

'1'

'1'

'1'

Long trail

of 0's

'1'

'1'

'1'

'1'

Time

Sta

ge O

utp

ut

'0'

'0'

'0'

'0'

'0'

'0'

'0''1'

'1'

'1'

'1'

'1'

'1'

'1'

'1'

'1'

'1'

Short trail

of 0's

Unsampled original bits

Tunable Resolution and Sensitivity

Slide 11

• Allows multiple resolution-sensitivity sweeps

• Facilitates strike pulse re-construction

10 20 30 50

0.40

Min

. d

ete

cti

on

am

plitu

de

(n

orm

ali

zed

to

VD

D)

Resolution (ps)

0.24

0.16

0.08

0.32

0.0400

Sensitivity vs resolution trade-off

VPO

VNO

VPE

VNE VNO VNEN2

VPO VPE

Back-Sampling Chain (BSC) Array

Slide 12

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

QD

Q D

Buff In

Scan Out

Buff Out

Scan In

C1

QD

Q D

Unit Cell

SER Test Board

Slide 13

• Beam diameter = 3inches

• 3x3 SER test-chips fitwithin beam area

• FPGA: JTAG supportfor automated control

• 15.3 million BSCstages per board

Fa

bri

ca

ted

Bo

ard

LANL Neutron Irradiation Test

Slide 14

• 10 stacked boards with 90 test-chips in parallelirradiated under neutron beam at Los AlamosNational Laboratory (LANL)

Neutron Beam Parameters

Slide 15

Source: Los Alamos National Laboratory

• Neutron beam specs

• Avg. energy spectrum range: 1.38 – 750MeV

• Avg. neutron flux: ~ 4.2x104 neutrons/cm2/s

Neutron Test Data: SET

Slide 16

A strike on buffer

node induces SET

FF Data = '0'

FF Data = '1'

Neutron Test Data: SEU/ MBU

Slide 17

MBU

SEUFF Data = '0'

FF Data = '1'

A strike on flop

storage node induces

SEU/ MBU

Strike Pulse Width Distribution

Slide 18

• With lower VDD, sampling cut-off drops andwider SET pulses are sampled

• Qcrit decreases with lower VDD, increasing SER

0

Pulse width (ns)

0.40V VDD, 0.30V VGS

0.50V VDD, 0.30V VGS

0.60V VDD, 0.30V VGS

1.E+02

1.E+03

1.E+04

1.E+05

1.E+01

Pu

lse

co

un

t

0.15 0.30 0.45 0.60 0.75 0.90

0.4V0.5V0.6V Sampling

cut-offsVo

ltag

e

Time

Strike Pulse Width Distribution

Slide 19

• With stronger starving (lower VGS), sensitivityincreases and sampling threshold drops,sampling wider SET pulses

Pu

lse

co

un

t

1.E+02

1.E+03

1.E+04

1.E+05

0.40V VDD, 0.20V VGS

0.40V VDD, 0.25V VGS

0.40V VDD, 0.30V VGS

1.E+010

Pulse width (ns)0.15 0.30 0.45 0.60 0.75 0.90

0.25V VGS

0.20V VGS

0.30V VGSSampling

cut-offs

Vo

ltag

e

Time

SET Pulse Re-construction

Slide 20

SET Pulse Re-construction

Slide 21

SET Pulse Re-construction

Slide 22

FWHM: Full width at half maximum

SET Pulse Re-construction

Slide 23

• Higher amplitude = shorter pulse width (lowerFWHM)

• To our knowledge, this is the first time individualstrike pulses are reconstructed

FWHM: Full width at half maximum

SET Pulse Re-construction

Slide 24

0.1

0.2

0.3

0.4

0.5

0.00.2 0.6 1.0

FWHMAVG: 218ps

AmplitudeAVG: 0.42

Vo

lta

ge

(V

)

Time (ns)

VDD=0.5V

0.2 0.6 1.0

FWHMAVG: 222 ps

AmplitudeAVG: 0.45

Time (ns)

VDD=0.4V

• Lower VDD: pulse amplitude ↑, pulse width ↑

Comparison with Prior Art

Slide 25

Pulse shrinking [2]

TDC based circuit [1]

This work

Unit cell layout Irregular, not easily scalable

Regular, scalable Regular, scalable

Sensitivity tuning

Fixed by design Variable using bias knobs

Resolution > 30ps > 1ps > 1.3ps

Qcrit sensitivity 1x 0.6x 9x

Fixed by design

To TDC

*

*

[1] T. D. Loveless et. al. TNS 2012[2] J. Furuta et.al. IRPS 2011

* Results reproduced in 14nm process

Flip-Flop SEU/MBU

Slide 26

• SER exponentially increases with lower VDD

• At lower VDDs, MBU become more dominant

Fail

ure

In

Tim

e

(no

rma

lized

)

100

102

104

106

108

0.2 0.4 0.6 0.8

VDD (V)

FIT: # of SER per flop per billion hours

Cro

ss-s

ecti

on

(no

rma

lized

)

100

0.2 0.4 0.6 0.8

VDD (V)

102

104

106

108

5-bit4-bit3-bit2-bit1-bit

Conclusion

Slide 27

• BSC chain technique proposed with 9x lowerQcrit and picosecond range resolution

• BSC circuit detects SET, SEU, and MBU

• 14nm test-chip irradiated under neutron beam

• Individual strike pulses re-constructed basedon neutron irradiation data

• Next step: SER model framework development