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This introduction talks about the basics of C to Hardware compilers, software used to generate hardware (in FPGA or CPLD devices, or potentially custom silicon chips), from the well-known and loved C programming language. Most PCB level hardware design engineers are not familiar with Hardware Description Languages (HDLs) such as VHDL or Verilog. Learning a new language, and particularly the nuances of describing asynchronous and / or parallel and concurrent hardware logic circuits can be daunting. However, most electronics designers and engineers are at least partially familiar with the C programming language, used for software development on PCs as well as embedded microcontroller systems. This presentation shows how, with Altium's C-to-Hardware compiler technology, the C programming language can be used to generate parallelized, accelerated hardware in FPGA devices.
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Altium’s C-to-Hardware Compiler Technology
Enabling systems engineers and reducing development time
What is the point? (Advantages)
Most Embedded/Software engineers are looking at FPGAs as a solution to accelerate the execution of their code
They are familiar with ANSI/ISO standard C language They don’t want to learn a new language (actually, many would want
to but simply don’t have the time to) Because C code deals with higher level “untimed” algorithms, they
often get confused when trying to learn HDLs which have a very granular focus (i.e. every clock pulse and signal level has to be considered)
Everyone knows a little bit of C – it’s easier to find engineers who can code in C than in VHDL or Verilog
FPGAs have special hardware features that allow much greater throughput than traditional MCUs or DSPs, such as dedicated multipliers, DSP blocks, and high-speed SRAM
2Copyright © 2008 Altium Limited
What’s the catch? (Disadvantages)
C-based design is not always a replacement for HDL-based design. Hardware components that are modeled in the structural and/or geometric domain are not easily described in, nor efficiently inferred from, the C language. (C-to-Hardware Compiler User Manual, p3)
C as a language is inherently sequential, so it can be difficult for the inexperienced user to understand how multiple operations (parallelism) may result.
Also, some hardware HDL generated from C will still be somewhat sequential (i.e. a state machine) to perform a simple operation. It will operate faster in hardware, but still not as optimal as if the user coded directly in VHDL to begin with.
In these cases, the Embedded developer needs to be aware of what pieces of code will lend themselves well to hardware accelleration.
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How the CHC compiler process works
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The CHC makes use of Parallelism
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So, what is Parallelism, anyway? To best answer this, let us look at a few examples:– Consider the following code segment:
– The goal is to multiply each element of an array (b[i]) by 2, storing the result in a corresponding array element (a[i]).
– In a traditional microprocessor, this loop would do 100 individual multiplies, one for each element.
– This piece of code is inherently parallel-ish. The CHC finds such situations and can use dedicated resources in parallel to achieve the task in a fraction of the time.
– Array operations like this are particularly good for acceleration using C-to-Hardware.
The CHC makes use of Parallelism…
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Parallelism can occur in places where you may not have considered, giving even more significant performance:– Consider the following code segment:
– In a traditional processor, a COMPARE would be executed FIRST, followed by either the addition or the subtraction.
– In hardware, these three operations can happen in parallel (and asynchronously), with a multiplexer used to select the correct result and pass it through to the “output” which would be (in this case) alarm_level
– The reliance of the statements on the comparison is called control dependancy
Dependencies
Control dependencies offer another significant avenue for improving speed of execution of embedded code.
Data dependencies, on the other hand, can inhibit the effectiveness of the CHC:– Read-After-Write: this occurs when one operation on some value can’t
be executed until a prior one has been.
– Write-After-Read: this occurs when a value can’t be written to until another has been read.
– Write-After-Write: you get the picture…
There are other types of dependencies, such as Aliasing or Loop dependencies. Users should refer to the CHC user guide as it provides more examples of these with an explanation of how to improve C coding style to lend itself to hardware execution.
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Scheduling and Chaining
Statements that would usually execute sequentially in a traditional processor can be chained in hardware, so that execution is made asynchronous (i.e. replacing multiple statements with combinatorial logic).
Consider the code:
Assuming all these variables are 32-bit integers, Scheduling and chaining could produce the equivalent circuit:
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CO OFL
S[31..0]
A[31..0]
B[31..0]
CI
U_ADD
ADD32B
A[31..0]B[31..0]
P[63..0]
U_MULT
MULT32B
I[31..0]
S[4..0]
O[31..0]
U_SHIFT
BRLSHFT32B
b[31..0]
a[31..0]
GND
SHIFT[31..0] <= 2
i[31..0]
j[31..0]
An Example
Let's look at a simple example to see how it works with an Embedded System...
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