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Ch 9. Memory, CPLDs, and FPGAs. 1. Read-Only Memory. Az : output polarity control Az = 0 output active low Az = 1 output active high. 9.1.1 Using ROMs for “Random” Combinational Logic Function. 9.1.1 Using ROMs for “Random” Combinational Logic Function. - PowerPoint PPT Presentation
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Ch 9. Memory, CPLDs, and FPGAs
1. Read-Only Memory
Az : output polarity controlAz = 0 output active lowAz = 1 output active high
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.1 Using ROMs for “Random” Combinational Logic Function
9.1.2 Internal ROM Structure
If diode present, 1Otherwise, Ø
Diodes are missing, thenD3 – D0 = 0111 instead of 0010
9.1.2 Internal ROM Structure
9.1.3 Two-Dimensional Decoding
To reduce decoding complexity -> 7 to 128 decoder is huge-> instead, 3 – to 8 decoder + 16 – to – 1 MUX
If tr exist, 1Otherwise, Ø
9.1.3 Two-Dimensional Decoding
9.1.3 Two-Dimensional Decoding
9.1.4 Commercial ROM Types
9.1.4 Commercial ROM Types
9.1.4 Commercial ROM Types
9.1.5 ROM Control Inputs and Timing
Three state busOE : output enableCS : chip select
OE & CS must be assecped
32k x 8bit ROM x 4 = 128kbytes(= 215 x 4 = 217) 17address bits
9.1.5 ROM Control Inputs and Timing
9.1.5 ROM Control Inputs and Timing
9.1.6 ROM Applications
In many phone connections, your voice is purposely attennated by a few decibels to make things work better (page. 729)
9.1.6 ROM Applications
9.1.6 ROM Applications
9.1.6 ROM Applications
9.1.6 ROM Applications
9.1.6 ROM Applications
3. Static RAM9.3.1 Static-RAM Inputs and Outputs
D-latch when SEL = Ø OUT <- Q when SEL = WR = Ø D <- IN
9.3.1 Static-RAM Inputs and Outputs
9.3.2 Static-RAM Internal Structure
9.3.3 Static-RAM Timing
9.3.3 Static-RAM Timing
9.3.4 Standard Static-RAMs
9.3.4 Standard Static-RAMs
9.3.5 Synchronous SRAM
9.3.5 Synchronous SRAM
9.3.5 Synchronous SRAM
9.3.5 Synchronous SRAM
9.3.5 Synchronous SRAM
4. Dynamic RAM9.4.1 Dynamic-RAM Structure
To store 1, word = bit = 1To store Ø, word 1, bit = Ø
Bit line prechanged between H&1To read, word = H If cell = 1 Bit line = 1If cell = Ø, bit line = Ø
9.4.1 Dynamic-RAM Structure
9.4.1 Dynamic-RAM Structure
9.4.1 Dynamic-RAM Structure
9.4.2 SDRAM Timing
9.4.2 SDRAM Timing
9.4.2 SDRAM Timing
9.4.2 SDRAM Timing
5. Complex Programmable Logic Devices
9.5.1 Xilinx XC9500 CPLD Family
9.5.1 Xilinx XC9500 CPLD Family
9.5.2 Function-Block Architecture
9.5.2 Function-Block Architecture
9.5.3 Input/Output-Block Architecture
9.5.4 Switch Matrix
9.6.1 Xilinx XC4000 FPGA Family
6. Field-Programmable Gate Arrays
9.6.1 Xilinx XC4000 FPGA Family
F&G perform any combinationLogic function of 4 inputs H for three inputs
9.6.1 Xilinx XC4000 FPGA Family
9.6.3 Input/Output Block
9.6.3 Input/Output Block
9.6.4 Programmable Interconnect
9.6.4 Programmable Interconnect
