Technical seminar

1

XC9500 CPLDs

“Supporting the Total Product Life Cycle”

Technical seminar

2

Designer's Needs

In-System Programming

Enhanced Testability

Design changes without PCB changes

Mixed 5V/3.3V I/Os

High endurance reprogramming

Multiple speeds/densities in identical pinouts and packages

Technical seminar

3

The Industry’s First 5V Flash CPLD 5 V In-System Programming (ISP)

High performance— 5ns pin-to-pin speed— 125 MHz count frequency

Large density range — 36 to 288 macrocells (Phase 1 family)

Flexible architecture— optimized for pin-locking— global and product term clock, set/reset, OE

Most complete IEEE 1149.1 (JTAG)

Highest reprogramming endurance — 10,000 program/erase cycles

Technical seminar

4

Smaller Cell Size with FastFLASH

Source

Data

Word Line

Control

Ground

Data

Word Line

Control

Write

Floating Gate

Typical E2 CPLD Cell FastFLASH CellControl

Write

Data

Ground

Word Line

Source

Data

Word LineControl

1/3Area

Product benefits due to smaller cell4 More routing switches in the same area supports pinl

ocking4 Lower parasitic capacitance improves performance4 Long term cost improvements due to scalability

Technical seminar

5

XC9500 Architectural Features

Predictable, all pins fast, PAL-like architecture

FastCONNECT switch matrix provides 100% routing with 100% device utilization

Flexible function block

— 36 inputs with 18 outputs

— product term expansion with up to 90 product terms per macrocell

— global and product term clocks

— global and product term 3-state enables

— global and product term set/reset signals

Technical seminar

6

XC9500 Architecture

FunctionBlock 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock n

3

I/O - Global Tri-States

2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECTSwitch Matrix

JTAG Port

3

I/O

I/O

I/O - Global Set/Reset

I/O - Global Clocks

I/OBlocks

1

Technical seminar

7

FastFLASH Function Block

ToFastCONNECT

FromFastCONNECT

23 Global3-State

GlobalClocks

I/O

I/O

36

Product-Term

Allocator

Macrocell 1

ANDArray

Macrocell 18

Technical seminar

8

XC9500 Macrocell

FromFastCONNECT

36

SUM-TermLogic

D/T Q

R S

to/from other macrocells

RegisterXOR 18

GlobalClocks

GlobalOEs

P-term ClkP-term R&SP-term OE

3 2 or 4

to/from other macrocells

GlobalR/S

P-TermAllocator

Technical seminar

9

XC9500 Advanced MacrocellFrom Upper Macrocell

To Upper Macrocell

From LowerMacrocell

To Lower Macrocell

Global S/R

Global S/R

Global CLKs

Product Term OE

Technical seminar

10

Flexible Cascading

Fast

Bi-directional cascade— collects/delivers available p-terms

Automatically controlled by software

One p-term granularity level

Forwards 3 p-terms, retains 2p-terms

Forwards 5 p-terms

Delivers 5p-terms

Delivers 5p-terms

Macrocell Logicwith 18p-terms

Technical seminar

11

Feedback Paths

FastCONNECT

Pin

Local

Macrocell

FastCONNECT

FB X

Macrocell

Macrocell

Pin feedback

FastCONNECT feedback

Local feedback

Technical seminar

12

FunctionBlock

FastCONNECT

Complete Interconnectivitywith FastCONNECT™

JTAG

GlobalS/R

GlobalClocks

FunctionBlock

FunctionBlock

FunctionBlock

FunctionBlock

FunctionBlock

FunctionBlock

FunctionBlock

Global3-State

Technical seminar

13

Restrictive Max7000/S Interconnect

Pin Inputs(~ 2 entries / LAB) Macrocells

(~2 entries / LAB)

1

2

3

4

36

Technical seminar

14

XC9500 FastCONNECT

Pin Inputs(~ 3 entries / FB) Macrocells

(36 entries / FB)

1

2

3

4

36

Technical seminar

15

What is Pin-Locking?

Ability to retain device pin assignments for small to medium design changes— introducing a new variable to existing terms— adding input signals— inverting signals— introducing 1or 2 buried flip flops— adding p-terms

Requires a symmetric, uniform architecture

Requires software focus on pin-locking

Technical seminar

16

Pin-Locking is Key for ISP

Must retain pinouts as the design evolves— best done when the design software initially assigns pin

s— different from pinout pre-assigning— strong function of utilization in typical CPLD architectur

es— result of both architecture and software strategy

Pin-locking is valuable — eliminates or reduces PC Board rework— minimizes time to market, saves money— lowers designer frustration, risk

Technical seminar

17

Leading Edge Features Support

Superior Pin Locking for ISP

FastCONNECT Function Block

36

36

I/O Block

I/O Block

Wired-ANDCapability

Function Block

3X more routing switches- superior input/feedback routability

Powerful bi-directional logic allocation- any number of p-terms (up to 90 max.)

Largest block fan-in- 36 direct inputs- wired-AND provides extra

logic/more fan-in

Technical seminar

18

XC9500 Supports Design Changeswith Fixed Pinouts

Design Change XC9500 Feature

Add another input FastCONNECT switch matrixpin or FB output with 100% connectivity

Add more logic in XC9500 allows expansionthe macrocell up to 90 P-terms

Add additional input 36 total inputs are available connections to the FB plus FastCONNECT AND

gate capability

Technical seminar

19

XC9500 System Features

Enhanced Data Security Features— Read security bits prevent unauthorized reading— Write security bits prevent accidental program/erase

Reduced power option per macrocell

3.3v/5v outputs

24 mA, 100% PCI compliant

Output Noise Reduction— Slew rate control— User programmable ground pin capabi

lity

User Programmable Ground Pin

User I/O Pin

Ground Pin

User I/O Pin

Internal Logic

Additional Ground Pin• Lower ground inductance• Reduce ground noise

Technical seminar

20

Advanced System Features

Enhanced Data Security Features— Read security bit prevents unauthorized reading— Write security bit prevents inadvertent user program/

erase

System Power Reduction— Reduced power option per macrocell

Output drive capability— 3.3v/5v outputs— 24 mA, 100% PCI compliant outputs

Output Noise Reduction in High-Pincount PQFP Packages— Slew rate control — User programmable ground pins

Technical seminar

21

Planned FastFLASH™ CPLD Family

XC9536 XC9572 XC95108 XC95144 XC95180 XC95216

Macrocells

UsableGates

tPD (ns)

Registers

Max. UserI/Os

36 72 108 144 180 216

800 1600 2400 3200 4000 4800

5 7.5 7.5 7.5 10 10

36 72 108 144 180 216

34 72 108 133 168 168

Packages 44PC44PQ

84PC100PQ

84PC100PQ160PQ

100PQ160PQ 160PQ

208PQ

XC95288

288

6400

10

288

192

208PQ304PQ

XC95432

432

9600

12

432

240

304PQ

XC95576

576

12800

15

576

240

304PQ

Phase II Expansion0.6µ Phase I Family

160PQ208PQ

Technical seminar

22

The Next Generation CPLD

The Industry’s first 5V Flash CPLD

Highest program/erase reliability of 10,000 cycles

The best Pin-Locking CPLD architecture

Most complete manufacturing and engineering JTAG support

Support for the Total Product Life Cycle