Digital Systems Design with FPCAs and CPLDs

Ian Grout

AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO

SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Newnes is an imprint of Elsevier Newnes

%

Table of Contents

Preface xvii

Abbreviations xxiii

Chapter 1: Introduction to Programmable Logic 1 1.1 Introduction to the Book 1 1.2 Electronic Circuits: Analogue and Digital 10

1.2.1 Introduction 10 1.2.2 Continuous Time versus Discrete Time 10 1.2.3 Analogue versus Digital 12

1.3 History of Digital Logic 14 1.4 Programmable Logic versus Discrete Logic 17 1.5 Programmable Logic versus Processors 21 1.6 Types of Programmable Logic 24

1.6.1 Simple Programmable Logic Device (SPLD) 24 1.6.2 Complex Programmable Logic Device (CPLD) 27 1.6.3 Field Programmable Gate Array (FPGA) 28

1.7 PLD Configuration Technologies 29 1.8 Programmable Logic Vendors 32 1.9 Programmable Logic Design Methods and Tools 33

1.9.1 Introduction 33 1.9.2 Typical PLD Design Flow 35

1.10 Technology Trends 36 References 38 Student Exercises 40

Chapter 2: Electronic Systems Design 43 2.1 Introduction 43 2.2 Sequential Product Development Process versus Concurrent

Engineering Process 52

viil Table of Contents

2.2.1 Introduction 52 2.2.2 Sequential Product Development Process 53 2.2.3 Concurrent Engineering Process 54

2.3 Flowcharts 56 2.4 Block Diagrams 58 2.5 Gajski-Kuhn Chart 61 2.6 Hardware-Software Co-Design 62 2.7 Formal Verification 65 2.8 Embedded Systems and Real-Time Operating Systems 66 2.9 Electronic System-Level Design 67 2.10 Creating a Design Specification 68 2.11 Unified Modeling Language 70 2.12 Reading a Component Data Sheet 72 2.13 Digital Input/Output 75

2.13.1 Introduction 75 2.13.2 Logic-Level Definitions 79 2.13.3 Noise Margin 81 2.13.4 Interfacing Logic Families 83

2.14 Parallel and Serial Interfacing 89 2.14.1 Introduction 89 2.14.2 Parallel I/O 95 2.14.3 Serial I/O 97

2.15 System Reset 102 2.16 System Clock 105 2.17 Power Supplies 107 2.18 Power Management 109 2.19 Printed Circuit Boards and Multichip Modules 110 2.20 System on a Chip and System in a Package 112 2.21 Mechatronic Systems 113 2.22 Intellectual Property 115 2.23 CE and FCC Markings 116

References 118 Student Exercises 121

Chapter 3: PCB Design 723 3.1 Introduction 123 3.2 What Is a PCB? 125

3.2.1 Definition 125 3.2.2 Structure of the PCB 127 3.2.3 Typical Components 139

3.3 Design, Manufacture, and Testing 144 3.3.1 PCB Design 144

Table of Contents ix

3.3.2 PCB Manufacture 150 3.3.3 PCB Testing 151

3.4 Environmental Issues 152 3.4.1 Introduction 152 3.4.2 WEEE Directive 153 3.4.3 RoHS Directive 153 3.4.4 Lead-Free Solder 154 3.4.5 Electromagnetic Compatibility 154

3.5 Case Study PCB Designs 155 3.5.1 Introduction 155 3.5.2 System Overview 157 3.5.3 CPLD Development Board 158 3.5.4 LCD and Hex Keypad Board 160 3.5.5 PC Interface Board 163 3.5.6 Digital I/O Board 166 3.5.7 Analogue I/O Board 168

3.6 Technology Trends 171 References 173 Student Exercises 175

Chapter 4: Design Languages 777 4.1 Introduction 177 4.2 Software Programming Languages 177

4.2.1 Introduction 177 4.2.2 С 179 4.2.3 C + + 181 4.2.4 JAVA™ 183 4.2.5 Visual Basic™ 186 4.2.6 Scripting Languages 189 4.2.7 PHP 191

4.3 Hardware Description Languages 193 4.3.1 Introduction 193 4.3.2 VHDL 194 4.3.3 Verilog®-HDL 196 4.3.4 Verilog®-A 199 4.3.5 VHDL-AMS 202 4.3.6 Verilog®-AMS 205

4.4 SPICE 205 4.5 SystemC® 208 4.6 System Verilog 209 4.7 Mathematical Modeling Tools 210

References 214 Student Exercises 216

;

\

x Table of Contents

Chapter 5: Introduction to Digital Logic Design 217 5.1 Introduction 217 5.2 Number Systems 222

5.2.1 Introduction 222 5.2.2 Decimal-Unsigned Binary Conversion 224 5.2.3 Signed Binary Numbers 226 5.2.4 Gray Code 231 5.2.5 Binary Coded Decimal 232 5.2.6 Octal-Binary Conversion 233 5.2.7 Hexadecimal-Binary Conversion 235

5.3 Binary Data Manipulation 240 5.3.1 Introduction 240 5.3.2 Logical Operations 241 5.3.3 Boolean Algebra 242 5.3.4 Combinational Logic Gates 246 5.3.5 Truth Tables 248

5.4 Combinational Logic Design 256 5.4.1 Introduction 256 5.4.2 NAND and NOR logic ZZZZZZZ...269 5.4.3 Karnaugh Maps 271 5.4.4 Don't Care Conditions 277

5.5 Sequential Logic Design 277 5.5.1 Introduction 277 5.5.2 Level Sensitive Latches and Edge-Triggered

Flip-Flops 282 5.5.3 The D Latch and D-Туре Flip-Flop ZZZZZZZZ..2S3 5.5.4 Counter Design 288 5.5.5 State Machine Design 305 5.5.6 Moore versus Mealy State Machines 316 5.5.7 Shift Registers 317 5.5.8 Digital Scan Path 319

5.6 Memory 322 5.6.1 Introduction 322 5.6.2 Random Access Memory 324 5.6.3 Read-Only Memory 325 References 327 Student Exercises 328

Chapter 6: Introduction to Digital Logic Design with VHDL 333 6.1 Introduction 333 6.2 Designing with HDLs 334

Table of Contents xi

6.3 Design Entry Methods 338 6.3.1 Introduction 338 6.3.2 Schematic Capture 338 6.3.3 HDL Design Entry 339

6.4 Logic Synthesis 341 6.5 Entities, Architectures, Packages, and Configurations 344

6.5.1 Introduction 344 6.5.2 AND Gate Example 346 6.5.3 Commenting the Code 353

6.6 A First Design 355 6.6.1 Introduction 355 6.6.2 Dataflow Description Example 356 6.6.3 Behavioral Description Example 357 6.6.4 Structural Description Example 359

6.7 Signals versus Variables 366 6.7.1 Introduction 366 6.7.2 Example: Architecture with Internal Signals 368 6.7.3 Example: Architecture with Internal Variables 372

6.8 Generics 374 6.9 Reserved Words 380 6.10 Data Types 380 6.11 Concurrent versus Sequential Statements 383 6.12 Loops and Program Control 383 6.13 Coding Styles for VHDL 385 6.14 Combinational Logic Design 387

6.14.1 Introduction 387 6.14.2 Complex Logic Gates 388 6.14.3 One-Bit Half-Adder 388 6.14.4 Four-to-One Multiplexer 389 6.14.5 Thermometer-to-Binary Encoder 397 6.14.6 Seven-Segment Display Driver 398 6.14.7 Tristate Buffer 409

6.15 Sequential Logic Design 414 6.15.1 Introduction 414 6.15.2 Latches and Flip-Flops 416 6.15.3 Counter Design 422 6.15.4 State Machine Design 426

6.16 Memories 440 6.16.1 Introduction 440 6.16.2 Random Access Memory 441 6.16.3 Read-Only Memory 444

6.17 Unsigned versus Signed Arithmetic 447 6.17.1 Introduction 447

xii Table of Contents

6.17.2 Adder Example 448 6.17.3 Multiplier Example 449

6.18 Testing the Design: The VHDL Test Bench 453 6.19 File I/O for Test Bench Development 459

References 471 Student Exercises 472

Chapter 7: Introduction to Digital Signal Processing 475 7.1 Introduction 475 7.2 Z-Transform 496 7.3 Digital Control 509 7.4 Digital Filtering 524

7.4.1 Introduction 524 7.4.2 Infinite Impulse Response Filters 532 7.4.3 Finite Impulse Response Filters 534 References 535 Student Exercises 536

Chapter 8: Interfacing Digital Logic to the Real World: A/D Conversion, D/A Conversion, and Power Electronics 537

8.1 Introduction 537 8.2 Digital-to-Analogue Conversion 543

8.2.1 Introduction 543 8.2.2 DAC Characteristics : 548 8.2.3 Types of DAC 555 8.2.4 DAC Control Example 559

8.3 Analogue-to-Digital Conversion 565 8.3.1 Introduction 565 8.3.2 ADC Characteristics 568 8.3.3 Types of ADC 572 8.3.4 Aliasing 577

8.4 Power Electronics 580 8.4.1 Introduction 580 8.4.2 Diodes 581 8.4.3 Power Transistors 585 8.4.4 Thyristors 593 8.4.5 Gate Turn-Off Thyristors 603 8.4.6 Asymmetric Thyristors 604 8.4.7 Triacs 604

8.5 Heat Dissipation and Heatsinks 606 8.6 Operational Amplifier Circuits 610

Table of Contents xiii

References 612 Student Exercises 613

Chapter 9: Testing the Electronic System 615 9.1 Introduction 615 9.2 Integrated Circuit Testing 621

9.2.1 Introduction 621 9.2.2 Digital 1С Testing 624 9.2.3 Analogue 1С Testing 629 9.2.4 Mixed-Signal 1С Testing 633

9.3 Printed Circuit Board Testing 633 9.4 Boundary Scan Testing 636 9.5 Software Testing 642

References 645 Student Exercises 646

Chapter 10: System-Level Design 647 10.1 Introduction 647 10.2 Electronic System-Level Design 654 10.3 Case Study 1: DC Motor Control 661

10.3.1 Introduction 661 10.3.2 Motor Control System Overview 662 10.3.3 MATLAB®/Simulink® Model Creation

and Simulation 665 10.3.4 Translating the Design to VHDL 666 10.3.5 Concluding Remarks 674

10.4 Case Study 2: Digital Filter Design 686 10.4.1 Introduction 686 10.4.2 Filter Overview 688 10.4.3 MATLAB®/Simulink® Model Creation

and Simulation 690 10.4.4 Translating the Design to VHDL 692 10.4.5 Concluding Remarks 698

10.5 Automating the Translation 702 10.6 Future Directions 703

References 704 Student Exercises 705

Additional References 707 Index 777

;