Stephanie Allison LCLS Event System [email protected] 14 June 2006 1 LCLS Event System Outline HW Block Diagram Timing Requirements Time Lines EVG

Stephanie Allison

LCLS Event System [email protected]

14 June 20061

LCLS Event System

OutlineHW Block Diagram

Timing Requirements

Time Lines

EVG to EVR Data Transfer

Beam-Synchronous Acquisition and Control

Issues/Comments

Status/To-Do

Stephanie Allison


14 June 20062

PNETExistingControlSystem

119MHz RF Clock

Trigger Delays and Pulse Widths, Event Codes per Output Channel

BPM IOCs

EVR

ADC

LLRF IOCs

HW Block Diagram

IOCMasterEVG

PNET

Timing Pattern,Timestamp, Event Codes

EVR

Channel Access

Beam Rate, Beam Path

Trigger

Trigger

360Hz Fiducial

IOCDownstreamEVG

To Downstream EVRs

Beam Rate, Beam Path

FutureMPS

Camera IOCs

EVR

Trigger

EVGFanOut

Camera

EVGFanOut

EVGFanOut

RFTiming

ModulatorTriggers

P/A Acq& Cntrl

Stephanie Allison


14 June 20063

Timing Requirements

Maximum trigger rate 360 Hz Clock frequency 119 MHzClock precision 20 psCoarse step size 8.4 ns ± 20 psDelay range >1 secFine step size 20 psMax timing jitter w.r.t. clock 2 ps rmsDifferential error, location to location 8 nsLong term stability 20 ps

Stephanie Allison


14 June 20064

Event Time Line – 120 Hz Beam

F0 F1 F2 F3 F4 F5 F6 F7

0 2.8 5.6 8.3 11.1 13.9 16.7 19.4

360Hz Fiducial

Time (msec)

B0 B1 B2Beam

S0 S1 S2Kly Standby

CX0 CX1CX2

BPM Calib CY0 CY1

T1 T1a T1b T2 T2a T2b T3Timing data for next Beam pulse

Stephanie Allison


14 June 20065

Event Time Line – 1 Beam Pulse (B1)

F3

0

Fiducial

Time (msec)B1 S1

Acq – BPM, Toriod, PMT,

Camera

T2

11-b 1+d

Laser Control

1-a

Beam

Post-Beam Acq

Kly Standby

1+c 1+e

B2 Timing Data

Received

Record processing (event, intr)

B1 Timing Data in

records, waiting to be used

Stephanie Allison


14 June 20066

EVG-to-EVR Data Transfer (Dayle Kotturi)

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e

. . .. . .

EVG EVR

8-b

it Eve

nt C

od

e

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

8-b

it Eve

nt B

uffe

r

8-b

it Eve

nt C

od

e

8-b

it Eve

nt C

od

e

8-b

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nt C

od

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Time (nsec)

8.4 16.8 25.2 33.6 42.0 50.4 58.8 65.2

8-b

it Eve

nt B

uffe

r

8-b

it MP

S D

ata

(Sh

are

d D

ata

Bu

s)

Stephanie Allison


14 June 20067

EVG-to-EVR Data Example (Dayle Kotturi)

Event Buffer byte17Timestamp byte 1


Event Buffer byte23Timestamp byte7

Event Buffer byte24Operator Requests

Event Buffer byte25Other data

.

.

.

Max Buffer is

2048 Bytes(34.42 µs)

LCLS expected

size is < 30 bytes

(0.5 µs)

Event BufferSequence RAM

Events queued to send

Event Code360 Hz fiducial

Event CodeBeam On

Event CodeRF On

Event CodeLaser Trigger

.

.

.

MPS Data

MPS DataStatus byte N

MPS DataResend byte N

MPS DataResend byte N

8-bit MPS DataResend byte N

MPS DataStatus byte N+1

Event CodeSBBD

Event Code10 Hz event

Event Code1 Hz event

Event CodeHLA DAQ


Event Buffer byte 1PNET byte 1

Event Buffer byte 0PNET byte 0

Event Buffer byte15PNET byte 15

No change in MPS status

MPS DataResend byte N+1

MPS DataResend byte N+1

change in MPS status

.

.

.

No change in MPS status

Countdown to send0.00 ms

Event CodeBPM Trigger

Event CodeDump Circ Buffers

Countdown to send8.4 ns




Countdown to sendOperator request

Countdown to sendOperator request




Event CodeSBBD


Two SBBD event codes shown. First is case to send beam to undulator; second is timed to

prevent beam from reaching undulator. It’s one OR the other, per seq RAM.

Stephanie Allison


14 June 20068

Trigger from Event Code (Dayle Kotturi)

Programmable Delay

Event Code

Trigger

Event Data in EVR

Stephanie Allison


14 June 20069

Beam-Synchronous Control: rules and algorithm for creating EVG trigger sequences on a pulse-to-pulse basis

Algorithm change on-the-fly based on user requestsSingle-Shot vs continuous beam pulses – enforce minimum delay between single-shot requestsBunch length measurementRate limitBeam destination

MPS rate limit and destination requestsSend out calibration, standby, and software triggers during non-beam time slots

Event Applications

Stephanie Allison


14 June 200610

Beam-Synchronous Acquisition: mechanism for users to request pulse-by-pulse acquisition across multiple IOCs:

Single-shot or multiple contiguous pulses

Include or exclude a pulse from resultant waveforms based on information in the timing pattern for that pulse

Can be implemented by either data mining of large data/timing-pattern arrays

…or use the timing system to trigger data copy to special records based on preset conditions, requires reserve/release of special records

Event Applications (cont)

Stephanie Allison


14 June 200611

Immediate Issues/CommentsEVG RF input divider – new circuit added to EVGDo we need EVR with RF recovery (EVR with clock)? 119Mhz availability throughtout?Fiber plant:

Match network bulk cable where possibleWhere is single mode fiber needed? Between fanouts? To EVR w/RF recovery?How much EVR daisy-chaining can we do?Daisy chain vs tap to split No plans for redundancy

TTL triggers – long trigger cables need designNot enough testing has been doneSchedule…….

Stephanie Allison


14 June 200612

Future IssuesModulator triggers on existing control system – how to rate-limit from new system Handling non-LCLS beams – add more beam-pulse-dependent info (ie, bunch charge) to timing pattern for IOC appsHow to upgrade PMC-EVR firmware

Stephanie Allison


14 June 200613

Status (Dayle Kotturi)

Received the EVG/EVR 200 series VME hardware (which sends up to 2K data buffer)

Received the EVR 200 series PMC module

Adapted driver and device support to: send the PNET data buffer (measured 66 µs transfer)

be OSI (running on mvme6100, RTEMS4.7)

with help from Till Straumann, Eric Bjorklund, Timo Korhonen, Jukka Pietarinen and Bob Dalesio

Stephanie Allison


14 June 200614

Status (cont)

Stephanie Allison and Mark Crane coming up to speed

Test stands for HW folks not yet ready

Rack/cable design for injector/BC1 well underway

Procurement underway

Stephanie Allison


14 June 200615

To-DoFinish PMC-EVR driver and test (share PMC-EVR and VME-EVR driver as much as possible)EVG sequence RAM programming at 360 HzEVG rules and algorithm definition for Jan commissioningAdd support for EVR timing pattern data records (in place well before next beam pulse)Jitter testingInterface with other subsystems needs reviewCommissioning test plan

Documents

Stephanie Allison LCLS Event System [email protected] 14 June 2006 1 LCLS Event System Outline HW Block Diagram Timing Requirements Time Lines EVG