Resistive MeFabien Clermidy, Natalija JovanovicOnkaraiah, Houcine Oucheikh, Olivie

Ogun Turkyilmaz, Elisa VianCEA-LETI, Minatec Campus

Grenoble, FRANCE fabien.clermidy@cea.fr

Abstract— Recent announcement of

memory from Sony shows the trend to quicmemories as an alternative to DRAM. Howevfor embedded computing is still a futuristicapproaches two applications based on Regaining area, performance or power consuapplication is FPGA, one of the first architectuthe most from ReRAM integration to reduce energy. The second application relates tosystems and the way to obtain an instantaneoudevices for Internet of Things.

Keywords— NVM, ReRAM, FPGA, FlipFlop

I. INTRODUCTION

The wireless communication field phenomenal growth during the last decadestrong driver for semiconductor products. resulted in a large and steady increase in dacenters, with billions of mobile devices coThis trend is not going to decline in the futuultra-low power (ULP) embedded systemInternet of Things) expected, culminating inenvironments and self-aware things for digitaclimate, food, energy, mobility, and health ap

Improving energy efficiency has becomeand research challenge for all the microelectrservers to ULP embedded systems. On onemore energy hungry as they become more pooperating expenses and investments in datacthe power dissipation. Then, the industry is mobile technologies for power saving. Omobile applications and ULP embeddehighlighted the need for circuit operating ovrange. The uniqueness of these applicaticomputing power requirement varies consid(e.g. from standby mode to video for Therefore, the circuit design has to be efficieand as well as at normal operating modeembedded system will operate frequently atcycle in burst mode. The applications in qrequire running permanently for at least 10battery or harvested energy. Minimizing draspower is a primary concern in order to enablwithout battery replacement or energy replen

CMOS technology scaling does not provsaving and require extensive power managemto optimize power saving. Design techni

978-3-9815370-2-4/DATE14/©2014 EDAA

emories: Which Applicc, Santhosh er Thomas, ello s

Jean-Michel PorUniversité d

IMMarseille

jean-michel.portal@

16Gbits Resistive kly adopt resistive ver, using ReRAM c goal. This paper eRAM-devices for

umption. The first ure that can benefit footprint and save

o ultra-low-power us “freeze” mode in

p, Memristors

N has experienced

e and has been a This growth has

ata and computing onnected to them.

ure with trillions of ms (smart devices, n creation of smart al society targeting pplications.

e a major concern ronic systems from e side, servers get owerful, increasing centers to manage considering using n the other side,

ed systems have ver a wide voltage ions is that their derably over time

mobile phones). ent even in standby e. Moreover, ULP t a very low duty

question will often 0 years on a small stically the standby le a long field time ishments.

vide enough power ment design tricks iques like Power

Gating (PG) and Adaptive V(AVFS) are commonly used tbetween 0V and its maximum stages in order to: (i) dynamiccircuit; (ii) dynamically track on-going application requiremdo not guarantee zero leakagefuture usage, with memories bpower strategy, leading to relati

Hence, increasing effort to(NVM) for the next generaggressively pursued. Emerginas magnetic RAM (MRAM Memory (PCM), and Resistivpursued, due to the advantagedensity, non-volatility, zero staand a back end of Line integratfront end (FE). Among these appear as the most promisinconsumption compared to PCMstructure compared to MRAM demonstrated with excellent scsize [1] and with the capabilcross-point array structures [2].than standard Flash technologDRAM and cache replacemenare considering ReRAM as repSolid State Disk and use it as srequire dense memory with a lo

TABLE I. NVM ELECTRICAL CHARA

However ReRAM devicesrenewal of the IC landscapembedded systems becomes aabout design opportunities fortakes the example of F(FPGA), devices currently ushighly suffering from leakage ptowards ULP devices. The rem

cations?

rtal, Marc Bocquet d’Aix-Marseille M2NP e, FRANCE @polytech.univ-mrs.fr

Voltage and Frequency Scaling o dynamically tune the voltage value with several intermediate ally switch-off any unused sub-the optimal point according to

ments. However, these solutions e, when data must be kept for being the weak link of the low-ively high sleep-mode leakage.

owards Non-Volatile Memories ration device applications is

ng memristor technologies such or STT-RAM), Phase-change

e RAM (ReRAM) are actively es of low writing voltage, high andby power from memory cells tion (BE) with no impact on the memory technologies, ReRAM ng candidate due to a lower

M and a simpler and smaller cell (TABLE I. ). ReRAM has been calability down to a 10nm cell ity of very high density using . Even if the endurance is higher gy, it remains limited for high nt. Therefore, memory suppliers placement for Flash memory in storage class memory [2], which ow access rate.

AC. VS. DRAM CELL (ISSCC, IEDM)

s hold promise for a complete pe if ReRAM integration in a reality. This paper discusses r embedded computing. It first ield-Programmable-Gate-Arrays sed in embedded systems but power. We then extend the idea ainder of this paper is organized

as follows: Section II introduces ReRAM tecIII addresses FPGA design. Section IV etowards “non-volatile” zero leakage micronon-volatile flip-flop and hybrid memory mode. Finally, section V underlines scaling c

II. RERAM TECHNOLO

The concept of memristors was originaLeon Chua in 1971 [4] and was demonstrateby a team of HP labs in 2008 [5]. A memritwo terminal resistor device with varyingresistance value changes according to ththrough the memristor over its entire histordoes not change when the power is nonvolatile. From design aspects, memrisdevice that can be used digitally where the rerefer to a binary value. A low resistance is tyas a logical ‘1’ and a high resistance as adevice includes a large variety of oxides for and PCM are also considered as memristors sare nonvolatile two-terminal devices with var

a) ReRAM principle ReRAMs are considered among the

solutions for future generation of low-cosvolatile memories. In the following, an overvresearch work on conductive-bridge memory metal oxide resistive switching memory (OxR

A ReRAM cell is generally built by a capInsulator-Metal (MIM) structure, composed resistive material ‘I’ sandwiched betweconductors ‘M’ as illustrated in Fig. 1.a. materials, these MIM cells can be easily inteend of line (BEOL) with conventional CMObasic working principle is the reversibldisruption of a conductive filament which sthe bottom electrodes through the resistive studied configurations, the filament can migration of oxygen vacancies in transit(OXRAM) (Fig. 1.b) or by the dissolutelectrode (Cu or Ag) in an oxide- or celectrolyte (CBRAM) (Fig. 1.c). Proper mmemory stack optimization and integrationpoints for the success of these technologies.

a) BEOL integration

b) Oxide-based RAM c)

Fig. 1. a) ReRAM BEOL integration; b) OxRAMvacancies migration; c) CBRAM: Chain of metal atom m

b) Conductive-Bridge RAM Among CBRAM technologies, GeS2-ba

demonstrated large programming window (Rpower consumption [6]. Fig. 2.a shows mvoltage (I/V) curves for a W/GeS2/Ag basedThe figure shows the bipolar switching behset/reset processes under positive and n

chnologies. Section extends this view ocontrollers using design for freeze hallenges.

OGIES ally envisioned by d for the first time istor is basically a g resistance. The he charge passed ry. The resistance down making it

stor is an analog esistance value can ypically considered a logical ‘0’. This

ReRAM. MRAM since these devices rying resistance.

most promising st embedded non-view of our recent (CBRAM) and on

RRAM) is given.

pacitor-like Metal-of an insulating or

een two electron Based on regular

egrated in the back S technology. The le formation and shunts the top and layer. In the most

be obtained by tion metal oxides tion of an active halcogenide-based material selection, n scheme are key

) CBRAM

M: Chain of oxygen migration

ased devices have ROFF/RON) and low measured current–d CBRAM device. havior through the negative polarity,

respectively. The memory swwhen a positive bias is applforming by electro-deposition ain the electrolyte, while a negatdissolution and thus to the OFFkinetic of programming operatithe applied voltage as well asSET time is about 10µs at 1.5compliance current of about ratio of about two/three orders o

The memory window cengineering of the interface. Asa 2nm thick HfO2 layer betwbottom electrode a memory wibe achieved. The Ag-rich CF chalcogenide layer. The role othe leakage current in the HRS in the GeS2 after the reset proce

Fig. 2. (a) Typical I-V characteristicsection of a CBRAM device with GeS2

Fig. 3. DC I-V characteristics for CBR

c) Oxide-based RAMOxRAM technologies, suc

provide higher write/erase spememory window. Fig. 4.a showide range of positive voltadifferent HfO2 thicknesses [7]the 5nm HfO2 sample is ~100nthe extracted cell behavior up 5nm HfO2 sample without failuhigh endurance [8]. The memor

witches to the ON (SET) state lied on the Ag top electrode, an Ag-based conductive filament tive voltage leads to the filament F (RESET) state (Fig. 2.b). The ons depends on the amplitude of

s the pulse width. The required 5V. As shown in Fig. 2.a for a 100μA an ON/OFF resistance

of magnitude was obtained.

can be further improved by s shown in Fig. 3, by addition of

ween the electrolyte and the W indow of about six decades can is formed/dissolved only in the

of the HfO2 layer is to suppress due to residual conductive paths

ess.

cs of GeS2 CBRAM. (b) TEM cross 2 electrolyte.

RAM devices.

ch as Ti/ HfO2 based devices, eed at the expense of a smaller ows the switching kinetics for a ages of the two samples with . The required SET voltage for ns at 1V. Fig. 4.b demonstrates to more than 108 cycles for the

ure, demonstrating their potential ry window is about 1 decade.

Fig. 4. (a) Exponential relationship of switching with 10nm-HfO2. (b) Resistance as a function of cycle numbe

Based on the defined stack, compaCBRAM brings higher off state resistanwindow at the expense of a longer switchingapplied voltage.

III. TOWARDS NV-FPGFPGA have experienced dramatic increa

flexibility, performance and commercial imp1990’s. With increasing costs of advanFPGAs are even more becoming a better altenumber of medium-volume applications thantheir non-recurring engineering cost and However, to support reconfigurability FPGAtransistors than fixed-logic ICs to perform tleading to higher leakage power consumptiFPGAs are generally not well suited for embedded applications. This section addressopportunities regarding ULP ReRAM-basfrom technology optimization to design integ

a) FPGA background In regular island style FPGAs, the logi

carried out in Logic Blocks (LB), the connected to the channels in connection bocommunication on different routing channelsswitch boxes (SB) as shown in Fig. 5. The coswitch box are the routing resources. The LBby vertical and horizontal routing channels are uniform throughout the entire FPfunctionality is stored in memory inside trouting information is in memory of the SB acan occupy almost half of the total chip arbased FPGA landscape.

Fig. 5. Island style FPGA

Therefore, the performance characteristidirectly related to the memory technology usdue to their fundamental nature as configuracan be classified according to the type of memconfiguration data. Among them, SRAM-bextensively used because they offer high comcompared to other FPGAs. They utilize SRAprogramming computational functions, usualof Look-Up Tables (LUT) and multiplexFPGAs are fast, but the volatile nature of Sreload configuration data at power-up or toretention voltage. The configuration process

V1/2 for 5nm-HfO2 and er.

ared to OxRAM, nce and memory g time for a given

GA ases in speed, size, pact since the early nced technologies, ernative for a large n in the past due to

ease of design. As must use more the same function, ion. Consequently, mobile and ULP

ses challenges and ed FPGA design

gration.

cal operations are I/Os of LBs are

oxes (CB) and the s are performed in onnection box and Bs are surrounded (or tracks) which

PGA. The logic the LBs, and the and CB. Memories rea in the SRAM-

ics of FPGAs are sed to design them able devices. They mory used to store based FPGAs are mputing capacities

AM for routing and lly through the use ers. SRAM-based SRAM requires to o maintain a data s can require high

current, while data voltage reconsumption. To overpass SRAFPGAs have been proposed. Alare store in Flash-based switchthe power is off. Nonetheless, ttechnology results in higherperformance. Besides, anti-fusecell size and can deliver fast pvolatility, but they are programm

b) ReRAM-based FPGA Considering emerging NVM

architectures recently have significant improvements on denergy efficiency (28%) [10]. Imemory to the top of the FEOLof the previously mentioned FPfast reconfigurability, low stanintegration).

The 1T2R has been thememory cell design, driven by compared to a regular 6T SRprogrammable resistors in voltshared select transistor [11]. Hoa severe requirement to really this architecture. Even if the 1by power consumption, if the hsufficient, leakage current timportant during run time, woperating power consumption.

In [12], a novel dual laydevice has been investigated. A6) has been achieved with a sonm HfO2 layer that suppresses thick GeS2 layers.

Fig. 6. Benchmark of LRS (Ron) areported in the literature obtained with

The 1T1R cell also suffconditions to set/reset the ReRselect transistor. This issue replacing the select transistor win Fig. 7. The operation modesare illustrated in Fig. 7 and sumconnected to programming voltWLB) are asserted the dual X

etention leads to standby-power AM volatility issues, Flash-based ll configuration and routing data hes that retain their states when the use of a hybrid CMOS-Flash r fabrication cost and slower e-based FPGAs offer the lowest performance in addition to non-mable only once.

M technologies many new FPGA been proposed demonstrating

density of integration (40%) and Indeed shifting the configuration L helps to merge the advantages PGA memory technologies (i.e. ndby leakage and high density

e most reported configuration its very high-density integration

RAM bit-cell. It consists of two tage divider configuration and a owever that resistance pair gives have a benefit in implementing T-2R solution eliminates stand-high resistive state (HRS) is not through the ReRAM can be

which in turn compromises the

yer HfO2/GeS2 based CBRAM A record high Roff resistance (Fig. olid electrolyte consisting of a 2 leakage current through a 30nm

and HRS (Roff) for several ReRAMs endurance test [11]

fers from unbalancing voltage RAM devices due to the single

can be easily overcome by with a transfer gate, as proposed s of the configuration 2T2R cell m up in TABLE II. The bitline is tages. After the word lines (WL, and Y lines are swing. In read

mode, X is tied to the supply voltage while Y is pulled to the ground.

Fig. 7. Proposed circuit scheme for programming and reading of CBRAM cells in resistor-divider configuration.

TABLE II. PROGRAMMING SCHEMES FOR TOP AND BOTTOM RERAM

Top and Bottom

‘0’ ‘1’

BL: ‘0’ Set Bottom Reset Top

BL: ‘1’ Set Top Reset Bottom

c) Performance gains The 2T2R cell was characterized for area and leakage

during operating mode as shown in TABLE III. The obtained results are compared to a classical 6T-SRAM cell implemented in 130nm technology design. The 2T2R cell brings an area gain of /2.6 with a leakage current of 182pA at 1.5V [13] due to the HfO2/GeS2 technology optimization. The next sub-section explains a favorable power management strategy for using CBRAM based technology exploiting the non-volatility feature of this type of ReRAM.

TABLE III. AREA COMPARISON BETWEEN 6-T SRAM AND 2T-2R

130 nm Bulk Cell Area ( m2) Leakage (pA) Volatile

SRAM 6T 11,28 25 [13] Yes

CBRAM 2T/2R 4.32 182 No

d) FPGA benchmarking In order to evaluate the overall impact of the proposed

memory cell on total area, critical path delay and power consumption, the tool flow described in [14] is used. First, SRAM-based FPGA is evaluated. After that, all the SRAM cells are replaced with the proposed non-volatile memory cell. In comparison to SRAM-based FPGA, NV-FPGA has reduced area by 32%. The smaller area leads to shorter and less capacitive wires. Therefore, improvements in critical path delay and power consumption are observed by 9% and 10% accordingly. The most important feature of the proposed FPGA is the non-volatility. As described before, the ULP goal is achieved by turning off, the FPGA when not in use. Consequently, taking advantage of the non-volatility, NV-FPGA can save the leakage power, which is otherwise wasted. Based on the activity ratio between on and off times, duty cycle can be defined. As shown in Fig. 8, decreasing the duty cycle, results in increased power gains. For applications having an

activity of 50%, the total power consumption can be reduced by 24% and more than 90% of power reduction is achieved for applications with 1% activity.

Fig. 8. Power gain according to different duty cycle values for NV-FPGA.

IV. TOWARDS ZERO LEAKAGE SYSTEMS The previous section underlined the benefits of using

ReRAM for the FPGA configuration memory. This section relates to ReRAM-based IC design toward zero standby leakage and rapid power on/off operations to extend battery life of mobile devices and ULP embedded systems.

The key idea is to design an efficient freeze state system being able to restart from the logic state when the system was powered-off. In this framework, ReRAM is employed in memory and combination logic to back up the data from the SRAM, register files down to Flip-Flops to the ReRAMs and switch the power off. This way the leakage is totally suppressed with no data loss.

Back-up and recall of data present density, consumption and timing response time challenges. This section approaches non-volatile Flip-Flop and hybrid-SRAM design.

a) ReRAM-based SRAM bit-cell To suppress memory standby power without a loss of data

while providing storage at high speed read/write operation, on-chip non-volatile memories, such as eFlash memory, have been associated to SRAMs in low power systems. To overcome the speed and supply voltage gaps between SRAM and eFlash memories, a two-macro scheme has been required, as shown in Fig. 9.a. The main drawback of such scheme is a long store/restore time due to word-by-word access, resulting in long power on/off time exposing the circuit to data loss in event of sudden power-failure.

With emerging non-volatile technologies, the concept called unified non-volatile SRAM bit-cell (NV-SRAM) has emerged and has become an important research topic in recent years to achieve fast parallel data transfer and fast power-on/off speed. Overall, the NV-SRAM solutions integrate 6T bit-cells and stacked resistive or capacitive NVM devices within a single bit-cell, forming a direct bit-to-bit connection in vertical arrangement as depicted in Fig. 9.b. In a volatile state with an active power supply, data is held in the SRAM portion, and this data is read/write accessed as standard SRAM cell. Before powering down the supply voltage, the data in the SRAM

0102030405060708090

100

020406080100Duty cycle

Pow

er G

ain

(%)

alu4apex2apex4ex1010ex5pmisex3pdcseqAverage

portion is stored into the NVM portion. Wpowered up, the stored value is restored to the

a) Two-macro scheme b) Un

Fig. 9. NV-SRAM schemes

Several emerging memristor devices havin NV-SRAM satisfying more or less the SRin terms of speed, supply voltage, stabilitytechnology constraints (voltage, current…(switching time, endurance, reliability…). ASONOS-based cells [15] require a high sstore-time and large area. The MRAM- and[16][17] consume a high current for storicapacitor-based cells [18] require minimizingdecent write access time.

a) 6T2R bit-cell [19] b) Rnv8T bit-cell [20]

Fig. 10. ReRAM-based NV-SRAM architectures

On the other hand, ReRAM-based bit-favorable position as ReRAM provides fastvoltage and set current, limiting area overheand compares three architectures. In [19], t(Fig. 10.a) connects NVMs to SRAM storaachieving the simplest bit-cell solution. Howstability issues and high leakage coming felements introduced in the cell architecture. can be improved by increasing the low- anvalues of ReRAM devices. To maintperformance, additional transistors to isolatefrom the 6T core have been integrated in [2both 8T2R (Fig. 10.b) [20] and Rnv8T (Fig. require an additional word-line (NVWL), as bit-cells, to deliver the store/restore signal, c8T2R bit-cell, to store a third source-line (Scan be shared overall the array or addressed ra NVWL is turned on, SL toggles from 0 toset and reset the ReRAM (NVML,R) devivalue of storage nodes. In Rnv8T bit-cell, achieved in two steps. Both bit-lines (BLL araised to a high voltage to set one NVM andreset the complementary NVM of the selecteschemes, during a restore operation, the data

When the circuit is e SRAM portion.

nified scheme

ve been considered RAM requirements y and area due to ) and limitations Among them, the

store-voltage, long d PCM-based cells ing. And the Fe-g the capacitor for

c) 8T2R bit-cell [21]

-cells appear in a t switching at low ead. Fig. 10 shows the ReRAM-6T2R age nodes directly

wever, it can lead to from the resistive The leakage issue

nd high- resistance tain the SRAM e ReRAM devices 20][21]. Therefore, 10.c) [21] bit-cells for regular 2 ports

consuming area. In SL) is required. SL row-by-row. When o a high voltage to ces following the store operation is and BLR) are first d then grounded to ed bit-cell. In both a are recalled from

the two NVM devices into the system power-on period. NVWas well as SL are groundedbetween NVML and NVMRrestoring the bit-cell.

Because ReRAM devices artime and low switching currpromising to suppress leakstandby/idle period with fast wtwo-macro scheme high data stand wake-up time limitatiostandby/idle period-based appli

b) ReRAM-based Flip-FlFor saving and restoring

during the power-down mode commonly employed. Typictransistors, to the Flip-Flop, from 16 to 26 [22]. It also leadsthe latch and its active power, connecting the balloon latch to

Fig. 11. An example of non-volatile mode or context saving in need based c

Following the spirit of NV-of a ReRAM-based non-volatiand NVM_R blocks are hookstandard master-slave Flip-Floplogic the control, transistors Mstore/restore the logic to/from advantage of using this approathese design topologies at themode of operation by disabHowever, when encountered wmode the non-volatile block using ReRAMs unlike the tradiwith high-Vt transistors candissipation. The device increasstacked ReRAMs making it colatch.

ReRAM-based NV-SRAM volatility zero standby leakaoperations.

SRAM storage nodes during the WL is turned on and both bit-lines d. The difference in resistance R creates a differential current

re moving toward fast switching rent, those solutions are very kage power consumption in wake-up time. It overcomes the tore/restore energy consumption ons, in particular for short ications.

lop the state of sequential circuits shadow or balloon latches are

cally, it requires ten extra increasing the transistor count s to an increase in delay through because of the extra transistors the Flip-Flop.

flip-flop circuit for introducing freeze computing systems in Internet of Things

SRAM, Fig. 9 gives an example ile Flip-Flop [23]. The NVM_L ked up to the slave part of a p. Depending on the state of the

MN1, MN2 and MN3 are used to the non-volatile ReRAMs. The

ach is that one can still employ e optimum best during normal bling the non-volatile blocks. with the need to transit to sleep is enabled. Such sleep modes

itional balloon or retention flops n ensure zero static power sing count is 6 transistors and 2 ompetitive with standard balloon

and NV-Flip-Flop unified non-age and rapid power on/off

V. SCALING CHALLENGES Design solutions for ULP embedded systems are mainly

implemented using mature CMOS technology nodes due to lower leakage currents and higher reliability. As most of the reported results on ReRAM are obtained using over-130nm nodes, it is evident that co-integration of CMOS and ReRAM technologies for these purposes is straightforward from design point of view. On the other hand, in mobile devices design the usage of most advanced technology nodes is assumed and co-integration with ReRAM encounters design issues that need to be addressed.

CMOS devices scaling is followed by reducing of nominal supply voltage, as well as maximum pin-to-pin voltage that prevents from oxide breakdown and provides reliable operation. Circuits in sub-100nm nodes operate at 1V and lower. In case of OxRAM devices, scaling of oxide thickness will potentially lead to reducing the forming voltage [1]. However, reported ReRAM operating voltages remain above the CMOS range (1V - 2.5V). Moreover, high performance systems will demand fast switching behavior which is feasible with higher voltages according to inverse relationship between set/reset switching time and applied voltage (Fig. 2).

Consequently, in order to merge low and high voltage technologies it is necessary to implement design techniques to overcome that discrepancy (e.g. level-shifters). Also, a CMOS circuitry that reliably tolerates a high supply voltage and has all transistors working in safe operating region must be implemented. One solution for high-voltage tolerant transistors is the use of thick gate-oxide devices in critical parts of the circuit which might not be easy to co-integrate with thin oxide digital transistors. The second approach includes alternative circuit topologies – transistor stacking with a bias voltage that provides limited voltages across the terminals of every cascade transistor. Both solutions come at the cost of a degraded performance and increased area.

Another challenge of ReRAM technology is both spatial (device to device) and temporal (cycle to cycle) variability. Current-based monitoring design solutions have already been proposed for high capacity memories. It can be expected that it will be one of major research topic in the coming up years.

VI. CONCLUSION ReRAM technology appears a prime candidate to save

energy in mobile devices and ULP embedded systems. It enables advanced power management and freeze mode capabilities with fast parallel data transfer and fast power-on/off speed. High speed write/erase operation, scalability and feasibility of BEOL integration have been reported for both CBRAM and OxRAM technologies. Regarding IC design, in this paper two representative applications have been approached. The high Roff state and Roff/Ron ratio of CBRAM technology enables to achieve low leakage long retention time 2T2R cell to achieve dense memory configuration and solve FPGA leakage issue. On the other hand, the lower voltage operation of OxRAM technologies enable NV-SRAM and NV-Flip-Flop design, unifying non-volatility, zero standby leakage, and rapid power on/off operations for mobile devices and ULP embedded systems.

However, the challenges to solve before the adoption of ReRAM by industry are numerous. Among them, spatial and temporal variability have to be address to achieve robust design. Addressing scaling, sub-32nm technologies open new paradigms. Research on forming-free devices and reliable design solutions has to be pursued to face up reliability issues caused by the voltage gap between CMOS technology and ReRAM.

REFERENCES [1] H. Akinaga, H. Shima, “Resistive random access memory (ReRAM)

based on metal oxides” Proc. IEEE, vol.98, No. 12, December 2010. [2] A. Kawahara et al., “An 8Mb Multi-Layered Cross-Point ReRAM

Macro with 443MB/s Write Throughput,” ISSCC, pp. 500-502 ,2012. [3] S.R. Lee et al., “Multi-level Switching of Triple-layered TaOx RRAM

with Excellent Reliability for Storage Class Memory,” VLSI Technology, pp. 2011-2012, 2012

[4] L. O. Chua, “Memristor—The Missing Circuit Element,” Transactions on Circuit Theory, vol. CT-18, pp. 507-519, 1971.

[5] Strukov et al., “The missing memristor found,” Nature, vol. 453, pp. 80-83, 2008.

[6] E. Vianello et al., “Sb-doped GeS2 as performance and reliability booster in Conductive Bridge RAM,”IEDM, pp.10-12, 2012.

[7] T. Diokh et al., “Investigation of the Impact of the Oxide Thickness and RESET conditions on Disturb in HfO2-RRAM integrated in a 65nm CMOS Technology,” IRPS, 2013.

[8] T. Cabout et al., “Temperature impact (up to 200 °C) on performance and reliability of HfO2-based RRAMs”, proc. of IMW 2013.

[9] M. Lin et al., “Performance Benefits of Monolithically Stacked 3-D FPGA,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Tran. On, vol. 26, no. 2, pp. 216-229, 2007.

[10] Y.Y. Liauw et al., “Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory,” ISSCC, pp. 406-408, 2012.

[11] S. Onkaraiah et al., “A hybrid cbram/cmos look-up-table structure for improving performance efficiency of field-programmable-gate-array,” ISCAS, 2013.

[12] G. Palma et al., “A novel HfO2/GeS2 based Conductive Bridge RAM for non-volatile reconfigurable logic applications” ESSDERC, 2013.

[13] S. Léomant, et al., “Sram dedicated pcms for leakage characterization in nanometer cmos technologies,” DTIS, pp. 316-32, 2006.

[14] O. Turkyilmaz et al., “RRAM-based FPGA for Normally Off, Instantly On Applications,” NanoArch, 2012.

[15] M. Fliesler et al., “A 15 ns 4 Mb NVSRAM in 0.13 u SONOS technology,”NVSMW, pp. 83–86, 2008.

[16] N. Sakimura et al., “Nonvolatile magnetic flip-flop for standby-power- free SoCs,” JSCC, vol. 44, no. 8, pp. 2244–2250, Aug. 2009.

[17] M. Takata et al., “Nonvolatile SRAMbased on phase change,” Non- Volatile Semiconductor Memory Workshop, Feb. 2006, pp. 95–96.

[18] T. Miwa et al., “NV-SRAM: A nonvolatile SRAM with backup fer- roelectric capacitors,” JSCC, vol. 36, no. 3, pp. 522–527, Mar. 2001.

[19] W. Wang et al., “Nonvolatile SRAM cell,” IEDM, pp. 27-30, 2006. [20] Hraziia et al., “Operation and Stability Analysis of Bipolar OxRRAM

Based Non-Volatile 8T2R SRAM as Solution for Information Back-up,” ELSEVIER Solid State Electronics, vol. 90, pp. 99-106, Dec 2013.

[21] P. Chiu et al., “Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications,” JSCC, vol. 47, no. 6, pp. 1483-1496, 2012.

[22] V. Zyuban et al., “Low Power Integrated Scan Retention Mechanism,” ISLPED, pp. 98-102, 2002.

[23] Onkaraiah, Santhosh, et al. "Bipolar ReRAM based non-volatile flip-flops for low-power architectures." New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International. IEEE, 2012