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Chapter 17 RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories

Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

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Page 1: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Chapter 17

RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories

Page 2: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 2

Common Bus OrganizationCommon Bus Organization

Page 3: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3

Outline

•• Tristate buffer and inputTristate buffer and input--out buffer out buffer on common lineson common lines

• Bus• Organization of registers on common

bus• Data bus and address buses

Page 4: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4

Tristate 4-bit Buffer Register on common Lines

RegisterOut-Enable(Read)

Commondata Lines

Page 5: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5

Tristate 4-bit Input/Output (IO)Buffer on common data Lines

Out-Enable(Read)

Common data Lines

IO Buffer

Load-Enable(Write)

Page 6: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6

Tristate 4-bits of Memory Cell array on common data Lines

Out-Enable(Read)

Common data Lines

Cell-array

Load-Enable(Write)

Page 7: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7

Read and write control signals

• Read control signal enables reading through data lines

• Write control signal enables writing (storing/loading) through data lines

Page 8: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8

Common Set of lines• A Common data Lines function for

Reading lines (output lines) when Read = 0; Write = 1 Common data Lines function for Writing (input lines) when control signals Read = 1; Write = 0

• Using tristate IO buffer register, we can write into that and read from that using four lines D0, D1, D2 and D3, and read and write signals to buffer

Page 9: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9

Outline

• Tristate buffer and input-out buffer on common lines

•• BusBus• Organization of registers on common

bus• Data bus and address buses

Page 10: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10

Data Bus and control signals

• Common Set of data lines, which can be used by several registers, memory units or ICs provided each one for each bit has a tristate buffer each and there is a common read control and another common write control signals to buffer

Page 11: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11

Address Bus

• Common Set of address lines, which can be used to select using a decoder only one of the several registers, memory units or ICs provided only one has distinct address

Page 12: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12

Bus• Data Bus facilitates connecting many

unit on common set of data lines, each unit is using it when addressed

• Address Bus facilitates selecting one of many unit through decoder in between

• Address bus has lines , which are common for decoders for all the units

Page 13: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13

Outline

• Tristate buffer and input-out buffer on common lines

• Bus•• Organization of registers on Organization of registers on

common buscommon bus• Data bus and address buses

Page 14: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14

Input/Output (IO) Registersorganised on common select line

and data lines

Out-Enable(Read)

Common 4 data Lines(Data Bus)

Four IO BufferRegisters

Load-Enable(Write)

2 to 4 lines decoder

Common 2address Lines(Address Bus)

4

2

Page 15: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15

Outline

• Tristate buffer and input-out buffer on common lines

• Bus• Organization of registers on common

bus•• Data and address busesData and address buses

Page 16: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16

Data Bus

• Data bus is bi-direction as it can function as output lines during read and as input lines during write to a buffer register or cell array of memory

• 8-bit Data bus connects 8-bit register or memory-cell array or IO buffer

Page 17: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17

Address Bus

• Address bus is unidirectional, originating and is from reading or writing unit or system to the decoders. Decoder select only one data byte for read or write from or to 8-bit data bus

• Address of 10 bits addresses one of 210

bytes for or from 8-bit data bus

Page 18: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18

Summary

Page 19: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19

• All bits are accessed through tristate buffers

• Common set of lines, which carry data for write and carry data for read connect all memory cell arrays or registers or buffers. Lines are called data bus

Page 20: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20

• Read control signal enables tristate buffers to read a memory cell arrays or registers or buffer by an external system or unit

• Write control signal enables tristate buffers to write into a memory cell arrays or registers or buffer by an external system or unit

Page 21: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21

• Common set of lines, which carry address for a memory cell array or register or buffer address to be selected for write or read

• Lines are input to decoder, which selects just one addressed cell array or register or buffer at an instance

• Lines to decoder for selecting addressed unit are called address bus

Page 22: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22

End of Lesson 2

Common Bus OrganizationCommon Bus Organization

Page 23: Digital Design: RAM, Address and Data Buses, Memory Decoding, Semiconductor Memories Part - II

Ch17L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23

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