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Lecture 12. Sequential Circuits and Finite State Machine
Prof. Hyung Chul Park & Seung Eun Lee
Logic Design
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Finite State Machine (FSM) (1)
• Logic block specifically designed to sequence through specific patterns of states in a predetermined sequential manner.
• It is necessary to design circuits that perform specific sequences of operations. Example : Controllers used to control the operation of other
circuits. FSM have proven to be a very efficient means of
modeling sequencer circuits.• Applications
Sequence Detector Traffic Light Controller Data-path controller Device interface controller etc.
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Finite State Machine (FSM) (2)
• Finite state machines (FSMs) is composed of 2 components: registers and combinational logic Registers represent one of the finite number of states
• k registers can represent one of a finite number (2K) of unique states
• An initial state (in registers) is assigned based on reset input at the (rising or falling) edge of clock The next state may change depending on the current state as
the next input comes in
Based on the current state (and input), output is determined via combinational logic
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Structure of FSM
• FSM is composed of State register that
• Store the current state• Load the next state at the clock edge
Combinational logic that• Computes the next state based on current state and input• Computes the outputs based on current state (and input)
Next State Logic(combinational)
Current StateRegister
(sequential)
Output Logic(combinational)
InputsOutputs
Feedback path
Clock
NextState
CurrentState
S? S
CLK
CL
Next StateLogic
NextState CL
OutputLogic
Outputs
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Finite State Machines (FSMs)
• Next state is determined by the current state and the inputs• Two types of FSMs differ in the output logic
Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and inputs
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CLKM Nk knext
statelogic
outputlogic
Moore FSM
CLKM Nk knext
statelogic
outputlogic
inputs
inputs
outputs
outputsstate
statenextstate
nextstate
Mealy FSM
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Moore and Mealy
• Edward F. Moore, 1925 - 2003 Together with Mealy, developed automata theory, the
mathematical underpinnings of state machines, at Bell Labs. Not to be confused with Intel founder Gordon Moore Published a seminal article, Gedanken-experiments on
Sequential Machines in 1956
• George H. Mealy Published “A Method of Synthesizing Sequential Circuits” in 1955 Wrote the first Bell Labs operating system for the IBM 704
computer
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How do I use FSMs ?
Control logic (FSM)
Control signals
start finmid
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1
00
0
Datapath (registers, muxes, adders…)
Block
ExternalInputs
ExternalInputs
ExternalOutputs
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In = 0
In = 1
In = 0In = 1
100
010
110
111001
Finite State Machine Representations
• States determined by possible values in sequential storage
elements• Transitions change of state
• Clock controls when state can change by controlling storage
elements
State
Transition
Input
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13.2 Analysis by Signal Tracing
• Assume an initial state of F/F• For the first input in the give sequence,
determine the output and F/F inputs• Determine the new sets of F/F states after the
next clock edge• Determine the output that corresponds to the
new states• Repeat 2,3,4 for each in the given sequence
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13.2 Analysis by Signal Tracing
• Moore sequential circuit to be analyzed
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13.2 Analysis by Signal Tracing
• Timing chart
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13.3 State Table and Graphs
• Determine the flip-flop input equations and the output equations from the circuit
• Derive the next-state equation for each flip-flop from its input equations, using one of the following relations:
• Plot a next-state equations for the flip-flop.• Combine these maps to form the state table. Such a
state table, which gives the next state of the flip-flops as a function of their present state and the circuit inputs, is frequently referred to as a transition table.
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13.3 State Table and Graphs
• The flip-flop input equations and output equation are
• The next-state equations for the flip-flops are
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D X BA ' D X AB Z A B
A X B' '
B X A
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13.3 State Table and Graphs
• State table and graph
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13.3 State Table and Graphs
• Serial adder
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13.3 State Table and Graphs
• Timing chart for the serial adder
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13.3 State Table and Graphs
• State graph
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13.3 State Table and Graphs
• State graph for a Mealy machine with multiple I/O
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14.1 Design of a Sequence Detector
• Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State Graph for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State Graph for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State Table for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State Table for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• K-maps for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• Circuit for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• Moore machine for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• Moore machine for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State table for Sequence Detector (101)
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14.1 Design of a Sequence Detector
• State table for Sequence Detector (101)
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14.3 Guidelines for Construction of State Graphs
• Construct some sample input and output sequences to make sure that you understand the problem statement.
• Determine under what conditions the circuit should reset to its initial state.
• If only one or two sequences lead to a non-zero output, a good way to start is to construct a partial state graph for those sequences.
• Determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly.
• Each time you add an arrow to the state graph, determine it can go to one of the previously defined states or whether a new state must be added
• Check your state graph to make sure there is one and only one path leaving each state for each combination of values of the input variables
• When your state graph is complete, test it by applying the input sequences formulated in part1 and making sure the output sequences are correct
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14.3 Guidelines for Construction of State Graphs
• Example 1: Z=1 when input sequence 0101 or 1001 occurs. The circuit resets after every four inputs. Mealy Circuit
• 0101 or 1001 The same state if either 01 or 10 is received
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14.3 Guidelines for Construction of State Graphs
• Example 1: Partial state graph
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14.3 Guidelines for Construction of State Graphs
• Example 1: Complete state graph
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