Sequential Circuits - Circuits Systems - Imperial College London

Lecture 4 - 1Introduction to Digital Integrated Circuit DesignSequential Circuits

Lecture 4

Sequential Circuits

Konstantinos MasselosDepartment of Electrical & Electronic Engineering

Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostasE-mail: [email protected]


Based on slides/material by…

P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html

J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html“Digital Integrated Circuits: A Design Perspective”, Prentice Hall

D. Harris http://www.cmosvlsi.com/coursematerials.htmlWeste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley

W. Wolf http://www.princeton.edu/~wolf/modern-vlsi/Overheads.html“Modern VLSI Design: System-on-Chip Design”, Prentice Hall


Recommended Reading

J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 7

Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”: Chapter 1 (1.4.9), Chapter 7 (7.3.1 – 7.3.5)


Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines


Combinational vs. Sequential Logic

Logic

Circuit

Logic

CircuitOut

OutInIn

(a) Combinational (b) Sequential

State

Output = f(In) Output = f(In, Previous In)


Sequential Logic

FF’s

LOGIC

tp,comb

φ

InOut

2 storage mechanisms• positive feedback• charge-based


Positive Feedback: Bi-Stability

Vi1

Vo1=Vi2Vo2

Vi1 Vo2

Vo1

Vi2

= V

o1

Vi2

= V

o1

Vi1 = Vo2

A

C

B


Meta-Stability

Vi2

= V

o1

Vi1 = Vo2

C

Vi2

= V

o1

Vi1 = Vo2

B

δ δ

Gain should be larger than 1 in the transition region


Outline


Latches

Flip – flops

Schmitt Trigger




D Latch

When CLK = 1, latch is transparent• D flows through to Q like a buffer

When CLK = 0, the latch is opaque• Q holds its old value independent of D

transparent latch or level-sensitive latch

CLK

D Q

Latc

h D

CLK

Q


D Latch Design

Multiplexer chooses D or old Q

1

0

D

CLK

QCLK

CLKCLK

CLK

DQ Q

Q


D Latch Operation

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q


Latch Design

Pass Transistor LatchPros+ Tiny+ Low clock load

Cons- Vt drop- nonrestoring- backdriving- output noise sensitivity- dynamic- diffusion input

D Q

φ

Used in 1970’s


Latch Design

Transmission gate+ No Vt drop- Requires inverted clock

D Q

φ

φ


Latch Design

Inverting buffer+ Restoring+ No backdriving+ Fixes either

Output noise sensitivityOr diffusion input

- Inverted output

D

φ

φ

X Q

D Q

φ

φ


Latch Design

Tristate feedback+ Static- Backdriving risk

Static latches are now essential

φ

φ φ

φ

QD X


Latch Design

Buffered input+ Fixes diffusion input+ Noninverting

φ

φ

QD X

φ

φ


Latch Design

Buffered output+ No backdriving

Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow- High clock loading

φ

φ

Q

D X

φ

φ


Latch Design

Datapath latch+ Smaller, faster- unbuffered input

φ

φ φ

φ

Q

D X


Outline


Latches

Flip – flops

Schmitt Trigger




D Flip-flop

When CLK rises, D is copied to QAt all other times, Q holds its valuepositive edge-triggered flip-flop, master-slave flip-flop

Flop

CLK

D Q

D

CLK

Q


D Flip-flop Design

Built from master and slave D latches

QMCLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latc

h

Latc

h

D QQM

CLK

CLK


D Flip-flop Operation

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q


Flip-Flop: Timing Definitions

DATASTABLE

DATASTABLE

In

Out

t

t

t

φ

tsetup thold

tpFF


Maximum Clock Frequency

FF’s

LOGIC

tp,comb

φ


Flip-Flop Design

Flip-flop is built as pair of back-to-back latches

D Q

φ

φ

φ

φ

X

D

φ

φ

φ

φ

X

Q

Qφ

φ

φ

φ


Enable

Enable: ignore clock when en = 0• Mux: increase latch D-Q delay• Clock Gating: increase en setup time, skew

D Q

Latc

h

D Q

en

en

φ

φLa

tchD

Q

φ

0

1

en

Latc

h

D Q

φ en

DQ

φ

0

1

enD Q

φ en

Flop

Flop

Flop

Symbol Multiplexer Design Clock Gating Design


Reset

Force output low when reset assertedSynchronous vs. asynchronous

D

φ

φ

φ

φ

Q

Qφ

φ

φ

φ

reset

D

φ

φφ

φ

φ

φ

Qφ

φ

Dreset

φ

φ

Qφ

φ

Dreset

reset

φ

φ

reset

Synchronous R

esetA

synchronous Reset

Sym

bol FlopD Q

Latc

hD Q

reset reset

φ φ

φ

φ

Q

reset


Set / Reset

Set forces output high when enabled

Flip-flop with asynchronous set and reset

D

φ

φ

φ

φφ

φ

Q

φ

φ

reset

set reset

set


SR-Flip Flop

S

R

QS

R Q

S R Q Q

0101

0011

Q100

Q010

S

R

Q

Q

QS

R Q

S R Q Q

1010

1100

Q101

Q011

Q

Q


JK- Flip Flop

S

R

Q

Q Q

J

K

φ

QJ

K Q

Jn Kn Qn+1

0011

0101

Qn01Qn

(b)

(c)

Q

(a)φ


Other Flip-Flops

QJ

K Qφ

T

φQJ

K Qφφ

D

Q

Qφ

T Q

Qφ

D

Toggle Flip-Flop Delay Flip-Flop


Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

φ

MASTER SLAVE

QJ

K Qφ

PRESET

CLEAR

SI

RI


Edge Triggered Flip-Flop

φ

S

R

Q

Q

Q

J

K

Q

QJ

KQ

>φ


Race Condition

Back-to-back flops can malfunction from clock skew• Second flip-flop fires late• Sees first flip-flop change and captures its result• Called hold-time failure or race condition

CLK1

D Q1

Flop

Flop

CLK2

Q2

CLK1

CLK2

Q1

Q2


Nonoverlapping Clocks

Nonoverlapping clocks can prevent races• As long as nonoverlap exceeds clock skew

Can be used for safe design• Industry manages skew more carefully instead

φ1

φ1φ1

φ1

φ2

φ2φ2

φ2

φ2

φ1

QMQD


CMOS Clocked SR- FlipFlop

VDD

Q

Q

RS

φφM1 M3

M4M2

M6

M5 M7

M8


Flip-Flop: Transistor Sizing

0.0 1.0 2.0 3.0 4.0 5.00.0

2.0

4.0

V Q

(1.8/1.2)(3.6/1.2)(7.2/1.2)


6 Transistor CMOS SR-Flip Flop

VDD

QQ

φ

M1 M3

M4M2

M5R

φ

S


Charge-Based Storage

D

D

φ

φ

In

φ

φ

(a) Schematic diagram

(b) Non-overlapping clocks

Pseudo-static Latch


Master-Slave Flip-Flop

φ

φ

φ

φ D

InA

B

φ

φ

Overlapping Clocks Can Cause• Race Conditions• Undefined Signals


2 phase non-overlapping clocks

φ2

φ1

φ1

φ2 D

In

φ1

φ2

tφ12


2-phase dynamic flip-flop

φ2φ1

DIn

Input Sampled

Output Enable

φ1

φ2


Flip-flop insensitive to clock overlap

DIn

φ

φ φ

φ

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

φ−section φ−section

CL1 CL2

X

C2MOS LATCH


C2MOS avoids Race Conditions

DIn

1

M1

M3

M2 M6

M7

M5

1

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

VDDVDD

(a) (1-1) overlap (b) (0-0) overlap

X X


Pipelining

RE

G

φ

REG

φ

REG

φ

log.

RE

G

φ

REG

φ

RE

G

φ

.

RE

G

φ

RE

G

φ

logOut Out

a

b

a

b

Non-pipelined version Pipelined version


Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?


NORA CMOS Modules

φ

φ

VDDVDD

PDN

φ

In1In2In3

φ

VDD

PUN

φ

φ

Out

φ

φ

VDD

Out

VDD

PDN

φ

In1In2In3

φ

VDD

In4

In4

VDD

(a) φ-module

(b) φ-module

Combinational logic Latch


Doubled C2MOS Latches

φ

VDD

Out

φ

VDD

Doubled n-C2MOS latch

Inφ

VDD

Outφ

VDD

Doubled n-C2MOS latch

In


TSPC - True Single Phase Clock Logic

φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStaticLogic

PUN

PDN

Including logic intothe latch

Inserting logic betweenlatches


Master-Slave Flip-flops

φ

VDD

D

VDD

φ

VDD

D

φ

VDD

φ

VDD

D

VDD

φ

φ

Dφ

VDD

φ

VDD

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY


Outline


Latches

Flip – flops

Schmitt Trigger




Schmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

VTC with hysteresisRestores signal slopes


Noise Suppression using Schmitt Trigger

VM+

VM–

VoutVin

t tt0 t0 + tp


CMOS Schmitt Trigger

VDD

Vin Vout

M1

M2

M3

M4

X


Schmitt Trigger Simulated VTC

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

1.0

2.0

3.0

4.0

5.0

VX (V

)

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

2.0

4.0

6.0

Vou

t (V

)

VM-

VM+


CMOS Schmitt Trigger (2)

In

VDD

VDD

Out

M1

M2

M3

M4

M5

M6

X


Outline


Latches

Flip – flops

Schmitt Trigger




Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T


Transition-Triggered Monostable

DELAY

td

In

Outtd


Monostable Trigger (RC-based)

VDD

InOutA B

C

R

In

B

Out t

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.


Astable Multivibrators (Oscillators)

0 1 2 N-1

0 1 2 3 4 5

t (nsec)

-1.0

1.0

3.0

5.0V

(Vol

t)

V1 V3 V5

Ring Oscillator

simulated response of 5-stage oscillator


Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (n

sec)

propagation delay as a functionof control voltage


Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC


Outline


Latches

Flip – flops

Schmitt Trigger




One-bit counter implementation


One-bit counter operation

All operations are performed as sφ2.XOR computes next value of this bit of counter.NAND/inverter compute carry-out.


n-bit counter structure


Sequential machines

Use memory elements to make primary output values depend on state + primary inputs.Varieties:• Mealy—outputs function of present state, inputs;• Moore—outputs depend only on state.


Sequential machine definition

Machine computes next state N, primary outputs O from current state S, primary inputs I.Next-state function:• N = δ(I,S).

Output function (Mealy):• O = λ(I,S).


FSM structure


Summary

Bi-stable sequential circuits • Latches (level sensitive circuits)• Flip – flops (edge triggered circuits)

Non bi-stable sequential circuits• Schmitt Trigger (responds fast to a slowly changing input)• Multivibrator circuits

Monostable (only one stable state – generates pulse of predetermined width)Astable (no stable states – output oscillates between two quasi stable states)

Documents

Sequential Circuits - Circuits Systems - Imperial College London