5 Chapter

Synchronous Sequential Circuits

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Logic Circuits- ReviewLogic Circuits

Sequential Circuits

Combinational Circuits

•Consists of logic gates whose outputs are determined from the current combination of inputs.•Performs an operation that can be specified by a set of Boolean functions.

•Employ storage elements in addition to logic gates.•Outputs are a function of the inputs and the state of the storage elements.•Output depend on present value of input + past input.

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OverviewStorage Elements and Analysis

Introduction to sequential circuitsTypes of sequential circuitsStorage elements

LatchesFlip-flops

Sequential circuit analysisState tablesState diagrams

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Introduction to Sequential Circuits

A Sequential circuit contains: Storage elements:

Latches or Flip-Flops Combinatorial Logic:

Implements a multiple-output switching function

Inputs are signals from the outside. Outputs are signals to the outside. Other inputs, State or Present State,

are signals from storage elements. The remaining outputs, Next State are

inputs to storage elements.

CombinationalLogic

Storage Elements

Inputs Outputs

StateNextState

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Introduction to Sequential Circuits

Sequential LogicOutput function

Outputs = g(Inputs, State)Next state function

Next State = f(Inputs, State)

Combina-tionalLogicStorage

Elements

Inputs Outputs

StateNextState

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Types of Sequential Circuits Depends on the times at which:

storage elements observe their inputs, and storage elements change their state

Synchronous Behavior defined from knowledge of its signals at discrete

instances of time Storage elements observe inputs and can change state

only in relation to a timing signal (clock pulses from a clock)

Asynchronous Behavior defined from knowledge of inputs at any instant

of time and the order in continuous time in which inputs change

If clock just regarded as another input, all circuits are asynchronous!

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5.3 Storage Elements :Latches Storage elements

Maintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit

Switch states (01 or 10) when directed by an input signal

Most basic storage element Used mainly to construct Flip-Flops Asynchronous storage circuit Types of latches:

SR Latches S`R` Latches D Latches

X = X

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Basic (NOR) S – R Latch Cross-coupling two NOR gates gives the

S – R Latch:

S (set)

R (reset)Q

Q

Graphic Symbol

R

S Q

Q

Basic (NOR) S – R Latch

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Q’ t+1 Q t+1 Q R S1 Q t+1=Q =0 0 0 00 1 1 0 01 0 0 1 01 0 1 1 00 1 0 0 10 1 1 0 1؟ Undefined 0 1 1؟ undefined 1 1 1

Q t+1 R SQ t+1=Q

No change 0 0

Reset to 0 1 0Set to 1 0 1

undefined 1 1

Basic (NAND) Ś – Ŕ Latch “Cross-Coupling” two NAND gates gives

the Ś -Ŕ Latch:

QS (set)

R (reset) Q

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Graphic Symbol

R

Q

Q

S

Basic (NAND) Ś – Ŕ Latch

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Q’ t+1 Q t+1 Q R S? ? 0 0 0? ? 1 0 00 1 0 1 00 1 1 1 01 0 0 0 11 0 1 0 11 0 0 1 10 1 1 1 1

Q t+1 R SUndefined 0 0Reset to 1 1 0Set to 0 0 1Q t+1=Q

No change 1 1

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Clocked S - R Latch Adding two NAND

gates to the basicŚ - Ŕ NAND latchgives the clockedS – R latch:

Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.

C means “control” or “clock”.

S

R

Q

C

Q

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1

S`

R`

13D Latch(Transparent Latch) Adding an inverter to the S-R Latch,

gives the D Latch: Note that there are no “indeterminate”

states! The graphic symbol for aD Latch is:

C

D Q

Q

DQ

C

Q

D Latch(Transparent Latch)

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Q D Q(t+1) 0 0 0 0 1 1 1 0 0 1 1 1

Q t+1 D0 0 1 1

Chapter 5: Sequential Circuits

5.4 :Flip-Flops

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Flip-Flops The latch timing problem Master-slave flip-flop Edge-triggered flip-flop Other flip-flops - JK flip-flop - T flip-flop

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The Latch Timing Problem In a sequential circuit, paths may exist through

combinational logic: From one storage element to another From a storage element back to the same storage

element The combinational logic between a latch output

and a latch input may be as simple as an interconnect

For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1

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The Latch Timing Problem (continued) Consider the following circuit:

Suppose that initially Y = 0.

As long as C = 1, the value of Y continues to change! The changes are based on the delay present on the

loop through the connection from Y back to Y. This behavior is clearly unacceptable. Desired behavior: Y changes only once per clock

pulse

ClockY

C

D Q

Q

Y

Clock

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The Latch Timing Problem (continued)

A solution to the latch timing problem is to break the closed path from Y to Y within the storage element

The commonly-used, path-breaking solutions replace the clocked D-latch with: a master-slave flip-flop an edge-triggered flip-flop

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Master-Slave Flip-Flop

Consists of two clockedD latches in serieswith the clock on the second latch inverted

What happened when c=1? The data from D input is transferred to the master . The slave is disabled . Any change in the input change the master output ( Y ) but

can’t effect the slave output .

CD Q

CCD QD

Master Slave

Y

What happened when C=0?

The master is disabled . The slave is enable. The value of ( Y ) is

transferred to the slave as input . The output ( Q ) is equal ( Y ) .Conclusion:The output of the F.F. can change only during the transition of clock from 1 to 0 or at Trigger .

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CD Q

CCD QD

Master Slave

Y

Timing

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A trigger: The state of a latch or flip-flop is switched by a change of the control input.

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Timing

Graphic Symbols

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Graphic Symbols

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Other flip-flops

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• Other F-Fs can be built using D F-F• There are four operation on a F-F

- set to 1- Reset to 0- toggle ( complement ) of Q - nothing

• There are tow F-F- JK F-F- T F-F

JK Flip-Flops27

JK Flip-Flops28

D = JQ’ + K’QQ t+1 K J

No changeQ t+1 = Q 0 0

Reset to 0 1 0

Set to 1 0 1

ComplementQ t+1= Q ’ 1 1

T Flip-Flops

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T Flip-Flops

T Flip-Flops

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Characteristic Table

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Characteristic Table32

Characteristic Equations

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State Equation35

State Equation

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Analysis This circuit consist of : 2 D F-F A and B Input x Output Y Qt+1 = D A= D A B = D B

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State Table

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State Diagram44

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state

Input / output

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1 D F-F ( A ) 2 Input X , Y Qt+1 = D D = A X y

Analysis 48

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2 JK F-F (A , B) Input x Q t+1 = JQ’ + K’Q

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2 T F-F ( A, B ) 1 input X 1 output Y Qt+1 = T Q The input equations are

T_A = BXT_B = X

The out put equation isY = AB

The characteristic equations are :At+1 = T_A A = BX A= BX(A’) + (BX)’A= A’BX + AB’ + AX’Bt+1 = X B

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Good Luck