IC Layout Design-Saad

7/27/2019 IC Layout Design-Saad

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IC Layout Design

Prepared By M. Saad Khan



What is MOSFET

• MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B)terminals

• In IC Layout Designing Transistors consist of multi no. of fingers



Symbol

Schematic Symbol

Layout Symbol



Capacitors

• Transistor based capacitors

• Mom capacitor

Mom Capacitor

Mom Capacitor

Transistor Based Capacitor



Resistors

Resistor (layout)



Duties

• To clean DRC & LVS

• To achieve accurate results of Post Layout



How to make a very first layout

• Id and password will be provided by the network administrator

• Sign in to your account via putty and then vnc, thesoftware cadence virtuso will be open.

• Schematic is provided by the circuit designer

• Then follow these steps shown in below diagrams:



Step 1: After sign in to your account via VNC this window will be open



Step 2: Right click then “open terminal” window will appear



Step 3: This is called “terminal window”



Step 4:Now write “launch” then press enter and select your desired project



Step 5: icfb window will appear now select tools menu then library manager



Step 6: now library manager windows will appear



Step 7: now go to “edit” then press library path to add library



Step 8: these window shows library paths



Step 9: how to add library



Step 10: now “go up a directory”



Step 11: let suppose we have to add library consisting name “fqureshi ”



Step 12: from “fqureshi ” library copy “siso40n”



Step 13: press “refresh”



Step 14: now siso40n will be appear in your library



Step 15: now browse your desired circuit let suppose (inverter)



Step 16: now open “schematic”



Step 17: this window will be appear



Step 18: now select “tools”



Step 19: now open “layout XL”



Step 20: now select create new



Step 21: the new window will be open



Step 22: now go to connectivity then select update the components and nets



Step 23: now layout generation window will be open



Step 24: now set the pin type to symbolic ….



Step 25: then the components will be updated in your layout window



Step 26: to set pin label



Step 27: general picture of schematic and layout



Step 28: select display to set “grid”



Step 29: set grid to “0.005”



Step 30: “final layout”



Mandatory things you have to ask the

designer1. What does this circuit do ?

2. How much current does it take ??

3. Where are the high and low currents??

4. What matching requirements are there?

5. What is the frequency of this circuit???

6. How much gain does it have?





Shortcuts and Layer Separation



Types of Circuits:• Digital

Digital Circuit consist of inverters, mux, adders, flip flop, ripple counter etc Digital circuits containing low currents

Digital circuits in 40nm may route easily with width 0.1 (minimum)

Power routing of digital circuits may be done maximum (width)

No symmetry and matching may required in digital circuits

We may connect poly connections with the poly (not always)



AnalogDifferential

Matching required

Symmetry requiredGate connected transistor may placed nearly

Mirror

Power routing (maximum)

Signal routing (on higher metal)Differential cap and resistor may placed correctly



Introduction to Custom IC Design

We are using cadence custom IC Design software for layout designing

HOT KEYS:

MmoveR rectangle

S stretchQ information regarding desired objectF2 For saving layout

Tips: ask your colleagues for more



Process Diagram:



DRC

• Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry insilicon

• Compromise designer - tighter, smaller

•The created mask layout must conform to a complex set of design rules, in order to ensure a lowerprobability of fabrication defects.

• A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design.

• The detected errors are displayed on the layout editor window as error markers, and the

corresponding rule is also displayed in a separate window.

• The designer must perform DRC (in a large design, DRC is usually performed frequently - beforethe entire design is completed), and make sure that all layout errors are eventually removed fromthe mask layout, before the final design is saved.

read more:http://lsmwww.epfl.ch/Education/CadenceTutorial/examples/layout.20.html

http://lsmwww.epfl.ch/Education/CadenceTutorial/examples/layout.20.html









DRC RULES• There are number of rules we have to follow for clear the DRC

• Some DRC errors may ignore

• Major rules included

N well spacing/width

Metal spacing/width

Deep n-well spacing /width etc Poly spacing/ width

PP/NP Overlapping errors/spacing



EXTRACTIONS

• Circuit extraction is performed after the mask layout design is completed, in order tocreate a detailed net-list (or circuit description) for the simulation tool.

• The circuit extractor is capable of identifying the individual transistors and their

interconnections (on various layers), as well as the parasitic resistances andcapacitances that are inevitably present between these layers.

• Thus, the "extracted net-list" can provide a very accurate estimation of the actualdevice dimensions and device parasitic that ultimately determine the circuitperformance.

• The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layoutsimulation).



LVS• After the mask layout design of the circuit is completed, the design should be checked against the

schematic circuit description created earlier.

• The design called "Layout-versus-Schematic (LVS) Check" will compare the original network with

the one extracted from the mask layout, and prove that the two networks are indeed equivalent.

• The LVS step provides an additional level of confidence for the integrity of the design, andensures that the mask layout is a correct realization of the intended circuit topology.

• Note that the LVS check only guarantees topological match: A successful LVS will not guaranteethat the extracted circuit will actually satisfy the performance requirements.

• Any errors that may show up during LVS (such as unintended connections between transistors,or missing connections/devices, etc.) should be corrected in the mask layout - before proceedingto post-layout simulation.

• Also note that the extraction step must be repeated every time you modify the mask layout.



Post-layout Simulation

• The electrical performance of a full-custom design can be best analyzed by performing a post-layout simulation on the extracted circuit net-list.

• At this point, the designer should have a complete mask layout of the intendedcircuit/system, and should have passed the DRC and LVS steps with no violations.

• The detailed (transistor-level) simulation performed using the extracted net-list willprovide a clear assessment of the circuit speed, the influence of circuit parasitics

(such as parasitic capacitances and resistances), and any glitches that may occur dueto signal delay mismatches.



• If the results of post-layout simulation are not satisfactory, the designer shouldmodify some of the transistor dimensions and/or the circuit topology, in order to

achieve the desired circuit performance under "realistic" conditions, i.e., taking intoaccount all of the circuit parasitic.

• This may require multiple iterations on the design, until the post-layout simulationresults satisfy the original design requirements.

• Finally, note that a satisfactory result in post-layout simulation is still no guaranteefor a completely successful product; the actual performance of the chip can only be verified by testing the fabricated prototype.

• Even though the parasitic extraction step is used to identify the realistic circuitconditions to a large degree from the actual mask layout, most of the extraction

routines and the simulation models used in modern design tools have inevitablenumerical limitations. This should always be one of the main design considerations,from the very beginning.

• After all, there is no substitute for the "real silicon" !



Layout Design Rules• To allow reliable fabrication of each structure, the mask layers must conform to a set

of geometric layout design rules.

ƒ

• Usually, the rules (for example: minimum distance

• and/or separation between layers) are expressed

• as multiples of a scaling factor – lambda (λ).

• For each different fabrication technology, lambda factor can be different.

Note: The lambda factor methodology was developed as a unified theory for calculating the weight benefits of converting from one material to another(e.g. converting from steel to aluminum).

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IC Layout Design-Saad