Analog Ic Layout 1 1385

Workshop on Fully Layout Technology 2002 / 03 / 23

林正松 / 矽拓科技有限公司

主講㆟：林正松主講㆟：林正松主講㆟：林正松主講㆟：林正松

矽拓科技有限公司矽拓科技有限公司矽拓科技有限公司矽拓科技有限公司

TEL：：：：03-5101949

THE ART OF ANALOG LAYOUT


林正松 / 矽拓科技有限公司2

前言前言前言前言

• 瞭解Analog佈局元件• 熟悉analog matching guide• 適當技巧性的放置• Design 與 layout 的共識



ANALOG LAYOUT

• CMOS ANALOG LAYOUT

• BIPOLAR ANALOG LAYOUT

• BICMOS ANALOG LAYOUT



CMOS ANALOG LAYOUT• CMOS Component Layout Guide

• CMOS Layout Application• Transistor• Capacitor• Resistor• Bipolar• Mos power transistor

• CMOS Layout Case Study



s G D S G D

CMOS LAYOUT STRUCTURE

LV NMOS：(poly)&(active)&(nplus)&(psub)

LV PMOS：(poly)&(active)&(pplus)&(nwell)



Asymmetric HV12V Device LayoutCMOS LAYOUT STRUCTURE

NMOS PMOS

N+

HV

POLYN+N++DIFF

DRAIN GATESOURCE DRAIN GATE SOURCE

CONTACT

NWELLP+POLY

PDD

HV

P+

MT1

DIFF



Asymmetric HVP30V Device LayoutCMOS LAYOUT STRUCTURE

PMOS NMOS

DRAIN GATE SOURCE

DIFF

POLYHPF+BL

P+

HV

CO

NWELL+BLNWELL+HPF

POLYN+

HV

DIFFDRAIN GATE SOURCE

LL



CMOS-RESISTOR LAYOUT STRUCTURE

>>Diff Resistor

>>Poly register >>Nwell ResistorCONTACT

DIFF

POLY1

NWELL

Ndiff

DUMMY DUMMY

NWELL

P+



1、P1-P2 LAYOUT STRUCTURE

2、MOS LAYOUT STRUCTURE

poly1

M1

CO

POLY2M2

poly1

P+CO

N+

DIFF

CMOS-CAPACITOR LAYOUT STRUCTURE



CMOS-CAPACITOR LAYOUT STRUCTURE3、MIN TOPMETAL 與 TOPMETAL-1之間加-MINLAYER

4、METAL POLY STRUCTURE

M5M4

VIA4

MIM

NWELLCONTACT

TOP=M1+M3BOTTOM=POLY1+M2



CMOS-PNP LAYOUT STRUCTURE

NWELL

CONTACT

DIFFM1

P+



CMOS-FUSE LAYOUT STRUCTURE

STYLE -3STYLE-1 STYLE-2

METAL FUSE POLY1 FUSE POLY1 FUSEM1

POLY1CONTACT

PASS

CONTACT

M1

POLY1



CMOS LAYOUT APPLICATION -TRANSISTOR

>>MOS Matching Mirror M2

VIA

M1

CONTACT

P+

DIFFPOLY



CMOS LAYOUT APPLICATION -TRANSISTOR>>交叉對稱（1）

OUT P

OUT N



>>交叉對稱（2）

CMOS LAYOUT APPLICATION -TRANSISTOR

DUMMY POLY



CMOS LAYOUT APPLICATION-CAPACITOR

DUMMY

>>Unit Capacitor

DUMMY

Well contact

poly



CMOS LAYOUT APPLICATION-CAPACITOR

>>Unit Capacitor –Input Stage Matching

POLY1

POLY2

M1

WELL CONTACT



CMOS LAYOUT APPLICATION-RESISTOR

>> Normal Resistor-兩端拉出即可兩端拉出即可兩端拉出即可兩端拉出即可



CMOS LAYOUT APPLICATION-RESISTOR

>>Crocess ResistorM2 VIA WELLCONTACT

CONTACT

POLY

M1



CMOS LAYOUT APPLICATION -RESISTOR>>交叉對稱

DUMMYDUMMY



CMOS LAYOUT APPLICATION –PNP X 10

NWELLP+N+

P+



CMOS LAYOUT APPLICATION –PNP X 9

NWELL

P+

P+

N+


林正松 / 矽拓科技有限公司23STYLE -1 STYLE -2

CMOS LAYOUT APPLICATION-Power MOS Transistor(1)

ESD PROTECTION 佈局方式不影響面積面積效益是最好ESD PROTECTION 能力差㆒點



CMOS LAYOUT APPLICATION –Power MOS Transistor(2)

阻抗考量，正方面型最好N+ DIFF NWELL

P+ DIFF

POLY



CMOS LAYOUT APPLICATION- Power MOS Transistor（（（（3））））

N+DIFFP+DIFF

NDIFF

POLY



CMOS LAYOUT APPLICATION –Power MOS Transistor（（（（4））））

>>M2 Finger Structure

M2

M1



CMOS LAYOUT CASE STUDY >>OP1

NWODP+

N+P1P2

COM1

VIAM2



CMOS LAYOUT CASE STUDY>>OP2

6 5

5 6

44 24 3

3 41

7 78 8

IP

IN

NWODP+N+P1P2COM1

VIAM2



CMOS LAYOUT CASE STUDY-CIRCUIT



BIPOLAR ANALOG LAYOUT

• BIPOLAR Component Layout Guide

• BIPOLAR Layout Application

• BIPOLAR Layout Case Study



BLDCSPSNCOM1

VIAM2TOCAPIR

BIPOLAR LAYOUT STRUCTURE-VNPN

STYLE-1 STYLE-2



BLDCSPSNCOM1

VIAM2TOCAPIR

BIPOLAR LAYOUT STRUCTURE-LPNP

STYLE-1 STYLE-2 STYLE-3



BIPOLAR –CAPACITOR LAYOUT STRUCTURE

MT1

BIPOLAR-RISISTOR LAYOUT STRUCTURE

IR SP

>>Sn-cap type

cap

BL

SN

TO



BIPOLAR LAYOUT APPLICATION-VNPN



BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-1 STYLE-2



BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-3



BIPOLAR LAYOUT APPLICATION-Power Transistor

EMIT 面積效應最大電流平均分散讓熱不會集㆗

矩型工字型



BIPOLAR LAYOUT APPLICATION-VNPN增加EMIT的周長，提昇趨動能力

梯型



BIPOLAR LAYOUT CASE STUDY



BIPOLAR LAYOUT CASE STUDY -CIRCUIT



BIPOLAR LAYOUT CASE STUDY



BICMOS ANALOG LAYOUT

• BICMOS Component Layout Guide

• BICMOS Layout Application

• BICMOS Layout Case Study



BICMOS LAYOUT STURCTURE



BICMOS LAYOUT STURCTURE-VPNP

DIFF PW

P+

CONTACT

NWELL

N+

>>Double Base



BICMOS LAYOUT STURCTURE-LPNP

PDIFF

NDIFF

NWELL

N+BL

POLY



BICMOS LAYOUT STURCTURE-VNPN

>>Double Base-降低Base 阻抗



BICMOS LAYOUT STURCTURE-RESISTOR

>>Base Resistor ＞>P2 resistor＞>P1 resistor



BICMOS LAYOUT STURCTURE

>>SNK Capasistor >>P1-P2 Capasistor

N+BLNWELLN+INP



BICMOS LAYOUT APPLICATION-VNPN

>>交叉對稱



BICMOS LAYOUT APPLICATION-VNPN增加Driver 趨動能力，節省面積



BICMOS LAYOUT CASE STUDY-CASE 1>>OP1

R2R2

R2R2

R2 R2 R2 R2

M5 M5

M1

M3

M3

M4

M4

M2

R1 R1 R1 R1 R1

DU

MM

Y

DU

MM

Y

Q2 Q1

Q2Q1

INIP



BICMOS CASE STUDY –OP CIRCUIT



BICMOS LAYOUT CASE STUDY-CASE 2AMP

G1

DU

MM

YD

UM

MY

DU

MM

YD

UM

MY

DU

MM

Y

DU

MM

YD

UM

MY

DU

MM

YD

UM

MY

DU

MM

Y

DU

MM

YD

UM

MY

DU

MM

YD

UM

MY

COLLECT

IN

M7

Q2 Q1Q3

R1 R1

R1 R1 R1 R2 R3

R1 R1 R1 R1 R1 R1 R1 R2

R1 R1 R1 R1 R2 R2 R2 R2

R4 R3 R4 R3

R3 R4 R3 R4

R3

M6M6

M4M5

M1M1

M1M1

M5M4

M6M6

M3M2

M2M3

M2M3

M3M2



BICMOS CASE STUDY –AMP CIRCUIT

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Analog Ic Layout 1 1385