Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout

Adapted from Digital Integrated Circuits, 2nd Ed. 1

IC Layout


Contents

Software overview Design Rules and Design rules check (DRC) Layers

N-well Active Metals Poly

Interconnects R, L, C Propagation speed of signals in lines


Design Software

L-EditCircuit at the mask

(layout) level

S-EditCircuit at the

Schematics level

LVSconsistency

mask = schematic ?

Simulation: T-Spice or any Spice based engine


Design Software

L-EditCircuit at the mask

(layout) level

S-EditCircuit at the

Schematics level

LVSconsistency

mask = schematic ?

Simulation: T-Spice or any Spice based engine

1

2

3

4

5


Process Layers


The N-Well

Assuming a p-type wafer, n-channel transistors are fabricated directly in the wafer; p-channel are fabricated in an “n-well”

Processes with n-well over p-substrates are called n-well processes

Substrate is also known as bulk or body

N-well forms a diode (normally reverse biased) with the substrate


N-Well: Design rules

Every layer has certain rules to satisfy in order to be safely built

MOSIS webpage data for AMI 0.5 R(N_Well) = 810Ω/□

Exercise: Layout and extract a resistor (minimum width) of 8K


N-well diode capacitance

m

d

jj

v

CC

0

0

1

20 lni

DAT n

NNV

sjbjj CCC 000

bjC 0Capacitance per area × bottom area

sjC 0 Capacitance per area × depth of well × perimeter

When the diode is reverse-biased (typical situation)

Two components: bottom capacitance and sidewall capacitance


N-well diode capacitance2

0 /40 maFC j

fFmaFmm

maFC j

1.5/407.356.3

/40119122

20

From MOSIS data, we know: Our resistor has a bottom capacitance

And no more data …

Approximate worst case RC

ps40


Active Layer


Active Layer

Active layers, both n+ and p+ are used to make the source and drain of MOSFET’s

Active defines the oxide mask where doping will take place: Regions outside Active have FOX (LOCOS)

N select and P select define the doping mask


Act Design Rules


N+ and P+ rules


Act contact rules

In this case, there is a special contact to join metal and active


Poly


Poly Layer

Polysilicon is made up of small crystalline regions of silicon Poly is used for the gates of MOS transistors They can make resistors and local connections for transistors


Poly rules


Poly contact rules


Metal Layers


The Metal layers

Metal layers are used to interconnect devices (transistors, resistors, inductors and capacitors)

Vias are used to interconnect the different metal layers Example: AMI 0.5 (three metals)


Metal Design rules

Metals 1, 2 and 3 rules Spacing rules Overlap rules

Vias 1 and 2 rules In general, higher metal layers require bigger dimensions and

spacing


Metal 1 Design Rules: Separation


Metal 1 Design Rules: Cnt Overlap


Metal 2 rules: Separation


Metal 2 Design Rules: via1 Overlap


Metal 3 rules: Separation


Metal 3 Design Rules: via2 Overlap


Via 1 rules


Via 2 rules


Interconnects


The Wire

transmitters receivers

schematics physical


Interconnect Impact on Chip


Wire Models

All-inclusive model Capacitance-only


Impact of Interconnect Parasitics

Interconnect parasitics reduce reliability affect performance and power consumption

Classes of parasitics Capacitive Resistive Inductive


10 100 1,000 10,000 100,000

Length (u)

No

of

ne

ts(L

og

Sc

ale

)

Pentium Pro (R)

Pentium(R) II

Pentium (MMX)

Pentium (R)

Pentium (R) II

Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

So

urc

e:

Inte

l


INTERCONNECT: Capacitance


Capacitance of Wire Interconnect

VDD VDD

Vin Vout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model


Capacitance: The Parallel Plate Model

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

diint

LLCwire SSS

SS

1


Permittivity


Fringing Capacitance

W - H/2H

+

(a)

(b)


Fringing versus Parallel Plate

(from [Bakoglu89])


Interwire Capacitance

fringing parallel


Impact of Interwire Capacitance

(from [Bakoglu89])


Wiring Capacitances (0.25 mm CMOS)


AMI 0.5µm process capacitances

Area capacitance (all values in aF/m2 )

Fringe capacitances (all values in aF/m)

M1 M2 M3

substrate 32 16 10

M1 31 13

M2 31

M1 M2 M3

substrate 76 59 39

M1 51 33

M2 52


INTERCONNECT: Resistance


Wire Resistance

W

L

H

R = H W

L

Sheet ResistanceRo

R1 R2


Interconnect Resistance


Dealing with Resistance

Selective Technology Scaling Use Better Interconnect Materials

reduce average wire-length e.g. copper, silicides

More Interconnect Layers reduce average wire-length


Polycide Gate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly


Sheet Resistance


Modern Interconnect


Example: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric


Resistance in AMI 0.5µm process

Resistance

A line of minimum width and 1mm long (1100 and 666 □ long, resp.)

M1 M2 M3

Rs 0.09Ω/□ 0.09 Ω/□ 0.05 Ω/□

M1 M2 M3

Rs 100 Ω 100 Ω 33 Ω


Vias parasitics

Vias exhibit a contact resistance given by the process

They also have a current limitation given by the electromigration phenomenom. Typically, 0.5mA/cnt

P+ N+ Poly M1 M2 M3

Contact R [Ω]

126 57.5 16 □ 0.82 0.79


Metal Current Capacity

Due to Electromigration, wire can be damaged For Aluminum, the maximum current density (rule of thumb)

is:

m

mA

1


INTERCONNECT: Inductance


Metal Parasitics: L

A metal line exhibits an inductance that can be estimated as:

Assumption: w > h L is proportional to w and inversely prop. to h

)/(44.1ln667.0393.1

25.1mmnH

hw

hw

L


Metal Parasitics: L

Ground bounce: The dI/dt along power lines actually produce a voltage drop due to the inductance

Increase the width of the conductors supplying current Increase the capacitance of the conductors supplying current


InterconnectInterconnectModelingModeling


The Lumped Model

Vout

Driver

cwire

VinClumpe d

RdriverVout


The Lumped RC-Model: Elmore Delay


The Ellmore Delay: RC Chain


Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:


The Distributed RC-line


Step-response of RC wire as a function of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge (V

)

x= L/10

x = L/4

x = L/2

x= L


RC-Models


Driving an RC-line

Vi n

Rs Vo ut(rw,cw,L)


Design Rules of Thumb

rc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> tpgate/0.38rc

rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RC when not met, the change in the signal is slower than the

propagation delay of the wire

© MJIrwin, PSU, 2000


Appendix


AMI 0.5 typical parameters (T36s)


Appendix

Poly resistor layout


Poly: Resistor Design

MOSIS webpage data for AMI 0.5 R(N_Well) = 22Ω/□ Exercise: Layout and extract a resistor (minimum width) of

1K. Try to make a square design Number of squares to achieve the desired resistance =

1000/22 □ = 45.5 Setting W = 2 then L = 91 Run DRC, extract and verify


Folded Resistor Design:

Folding the resistor leads to compact designs Squares and corners contribute partially to the material

resistance



Calculation for a square layout

Assume Ns segments of width Ws, length Ls and spacing Wg

The number of squares is:

For a square design:

Ws

WgNs

Ws

LsNs

Ws

WsLsN )56.0(2)1()2(

22)8.0(2

WsWgWsNsWsLs ))(1(2



For the 1K resistor, N□ = 45.5 Ns=5.1 Ls=4.53

Documents

Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout