Homework Assignment 06 - University of Iowas-iihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55041_2013/... · 2013. 10. 13. · Homework Assignment 06 . Question 1 (Short Takes). 2 points

55:041 Electronic Circuits. The University of Iowa. Fall 2013.

Homework Assignment 06

Question 1 (Short Takes). 2 points each unless otherwise noted.

1. A single-pole op-amp has an open-loop low-frequency gain of 𝐴 = 105 and an open loop, 3-dB frequency of 4 Hz. If an inverting amplifier with closed-loop low-frequency gain of �𝐴𝑓� = 50 uses this op-amp, determine the closed-loop bandwidth. Answer. The gain-bandwidth product is 4 × 105 Hz. The bandwidth of the closed-loop amplifier is then is 4 × 105/50 = 8 kHz.

2. When researching part numbers for three-terminal regulators, an engineer encounters the term “LDO”. What does “LDO” stand for? Answer: “Low Drop Out”

3. Define load regulation of a voltage regulator. Answer:

Load Regulation = 𝑉𝑜(𝑁𝐿) − 𝑉𝑜(𝐹𝐿)

𝑉𝑜(𝑁𝐿)× 100 (%)

“NL” means “No Load”, and “FL” means ‘Full Load”

4. Define line regulation of a voltage regulator. Answer:

Line Regulation = Δ𝑉𝑜𝑉𝐼

× 100 (%)

Here 𝑉𝐼 is the input (line) voltage.

5. The output voltage of a three-terminal voltage regulator is 5 V @ 5 mA load, and 4.96 V @ 1.5 A load. What is the regulator’s output resistance? (a) ≈ 27 mΩ (b) ≈ 1K (c) ≈ 3.3 Ω

Answer: 𝑅 = Δ𝑉 Δ𝐼 = 0.04 1.495 = 27 mΩ⁄⁄ , so (a)

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6. The output voltage of a three-terminal voltage regulator is 5 V @ 5 mA load, and 4.96 V @ 1.5 A load. What is the regulator’s load regulation? Answer:

Load Regulation = Vo(NL) − Vo(FL)

Vo(NL)× 100 =

5 − 4.965

× 100 = 0.8%

7. Assume that your SPICE simulation software (such as Micro-Cap SPICE) do not have a photodiode “part”. Explain in 1–2 sentences how you can nevertheless simulate a photodiode.

Answer: One can model a photodiode with a current source.

8. Below are the characteristics for a MOSFET. What type of FET is this (circle one)?

(a) Enhancement PMOS (b) Depletion PMOS (c) Enhancement NMOS (d) Depletion NMOS

Answer : The subscript “SG” indicates a p-channel FET (the more common n-channel MOSFET has “GS” as in 𝑉𝐺𝑆) and note that increasing 𝑉𝐺𝑆 increases 𝐼𝐷, so this is an enhancement PMOS, so option (a) is the answer.

9. True or false: the threshold voltage (𝑉𝑇𝑁,𝑉𝑇𝑃) for a particular MOSFET is, as is the case with the cut-in voltage (𝑉𝛾) of diodes, well-defined and not subject to large variation between samples of the same part number. Answer: False: 𝑉𝑇𝑁,𝑉𝑇𝑃 varies significantly between parts.

10. True or false: the MOSFET parameter 𝐾𝑛 (NMOS) or 𝐾𝑝 (PMOS) varies between samples of the same part number, but essentially constant for specific MOSFET. Answer: False.

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11. A MOSFET is biased such that 𝑔𝑚 = 1.78 mA/V and 𝐼𝐷 = 1 mA. If 𝑣𝐺𝑆 changes with 1 mV, by how much does the drain current change?

𝛿𝐼𝐷 = 𝑔𝑚δ𝑉𝐺𝑆 = (1.78 × 10−3)(1 × 10−3) = 1.78 µA

12. True or false: given the symmetrical construction of MOSFETs one can, in principle, at least, interchange the drain and the source terminals without affecting device behavior. Answer: True. However, in practice there is a hidden “body diode” that can complicate interchanging the source and drain.

13. With respect to MOSFETs, the units of 𝐾𝑝 and 𝐾𝑛 are (circle one)

(a) A V2⁄ (b) 𝐾𝑝 = +A V2⁄ (PMOS) 𝐾𝑛 = −A V2⁄ (NMOS) (c) V A2⁄ (d) A V⁄

14. In the following circuit, the MOSFET is (circle one)

(a) In saturation (b) In the Ohmic region (c) Always off (d) Can’t say without knowing component values including 𝑉𝑇𝑃

Answer: Option (a) because since no current flows through 𝑅𝐺 , 𝑉𝑆𝐺 = 𝑉𝑆𝐷 and 𝑉𝑆𝐷 > 𝑉𝑆𝐷(𝑠𝑎𝑡) = 𝑉𝑆𝐷 + 𝑉𝑇𝑃.

15. The units for the 𝜆 parameter for a MOSFET is ______

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Question 2 Provide a circuit that uses a 5-V, three-terminal voltage regulator, to implement a 250-mA constant current source. Assume that in addition to the regulator and a selection of resistors and capacitors, you have a regulated 9-V power supply available. What is the maximum power the regulator will dissipate? (6 points)

Solution In the circuit shown , the 5-V regulator maintains a constant 5-V voltage across 𝑅𝑆𝐸𝑇, so the current through the resistor is 𝐼𝑆𝐸𝑇 = 5 𝑅𝑆𝐸𝑇⁄ . Neglecting the regulator’s quiescent current this is also the load current 𝐼𝐿 = 0.25 A. Thus, 𝑅𝑆𝐸𝑇’s value must be 𝑅𝑆𝐸𝑇 = 5 0.25⁄ = 20 Ω. Note that 𝑅𝑆𝐸𝑇 will dissipate 𝐼2𝑅𝑆𝐸𝑇 = 1.25 W. The capacitors are required for stability and their value will depend on the model of 5-V regulator.

The worst-case power dissipation for the regulator is when the load resistance is 0 Ω. In this instance there is 9 V across and 0.25 A flowing through the regulator, so 𝑃𝑚𝑎𝑥 = 9 × 0.25 =2.25 W

Question 3 Consider the voltage regulator below, implemented with a reference voltage 𝑉𝑅𝐸𝐹 = 1.25 V and the input voltage is 𝑉𝐶. Determine the output voltage 𝑉𝑂 to 4 significant figures. (4 points)

Solution The amplifier and feedback loop maintains a voltage 𝑉𝑅𝐸𝐹 across 𝑅1 so the current through both resistors is 𝐼 = 𝑉𝑅𝐸𝐹 𝑅1⁄ . The output voltage is then

𝑉𝑂 = 𝐼(𝑅1 + 𝑅2) =𝑉𝑅𝐸𝐹𝑅1

(𝑅1 + 𝑅2) = 4.959 V

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Question 4 What is 𝑣𝑜 in the following circuit if 𝑣𝑅𝐸𝐹 = 1.2 V, 𝑅1 = 680 Ω, and 𝑅2 = 200 Ω? (4 points)

Answer: The current through 𝑅2 is 1.2/200 = 6 mA, which also flows through 𝑅1. Thus, the output voltage is 1.2 + 0.006× 680 = 5.28 V

Question 5 The op-amp in the circuit is ideal except for non-zero input bias current 𝐼𝐵 = 10 nA. In the circuit, 𝑅𝐹 =10K,𝑅1 = 1K, and 𝑅2 = 100 Ω. Determine the maximum and minimum output voltage 𝑉𝑂 resulting from 𝐼𝐵. Remember that 𝐼𝐵 could be positive or negative. (6 points)

Solution

The op-amp is ideal with respect to gain so that 𝑉𝑃 = 𝑉𝑁 and we assume the input bias current is the same for both the non-inverting and the inverting inputs. For the case where 𝐼𝐵 flows into the op-amp

𝑉𝑁 = 𝑉𝑃 = −𝑅3(𝐼𝐵) = −(100)(10 × 10−9) = −1 𝜇V.

KCL at the inverting input, assuming current flows away from the node gives

𝑉𝑁1K

+𝑉𝑁 − 𝑉𝑂

10K+ 𝐼𝐵 = 0

Substitution of 𝑉𝑁 = −1 𝜇V yields

−1 × 10−6

1K+−1 × 10−6 − 𝑉𝑂

10K+ 10 × 10−9 = 0

⇒ 𝑉𝑂 = 89 𝜇V

For the case where 𝐼𝐵 flows out of the op-amp, 𝑉𝑂 = −89 𝜇V. Thus, the maximum output voltage is −89 𝜇V and the minimum output voltage is +89 𝜇V.

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Question 6 For the amplifier shown, determine

(a) The ideal closed-loop voltage gain. (2 points) (b) The actual closed-loop voltage gain if the open-loop

gain is 𝐴𝑜𝑑 = 150,000 and the op-amp is otherwise ideal? Give your answer to 6 significant digits. (4 points)

(c) The minimum open-loop gain such that the closed-loop gain is within 1% of the ideal? (4 points)

Solution

Part (a) For an ideal op-amp, 𝑣+ = 𝑣− and 𝑖𝑖 = 0 so that the circuit is a follower and 𝐴𝑣 = 1.

Part (b) With finite open-loop gain, there is a voltage difference 𝑣𝑂 𝐴𝑜𝑑⁄ between the 𝑣+ and 𝑣− inputs. Assuming 𝑣𝑂 > 0, an equivalent circuit that captures the voltages is shown in (a) below.

(a) (b) Applying KVL around the loop shown in (b) gives

−𝑣𝐼 +𝑣𝑂𝐴𝑜𝑑

+ 𝑣𝑂 = 0 ⇒ 𝐴𝑣 =𝑣𝑂𝑣𝐼

=𝐴𝑜𝑑

1 + 𝐴𝑜𝑑= 0.999993

Part (c) From part (b) we have

𝐴𝑣 =𝑣𝑂𝑣𝐼

=𝐴𝑜𝑑

1 + 𝐴𝑜𝑑

This must be within 1% of the ideal case (𝐴𝑣 = 1), or

𝐴𝑜𝑑1 + 𝐴𝑜𝑑

> 0.99

Solving yields 𝐴𝑜𝑑 > 99.

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Question 7 Consider the current-to-voltage converter circuit shown. The current source has a finite output resistance 𝑅𝑆, and the op-amp is ideal except for a finite open-loop gain 𝐴𝑜𝑑. Show that the input resistance indicated in the figure is given by 𝑅𝑖𝑛 = 𝑅𝐹 (1 + 𝐴𝑜𝑑)⁄ . (4 points)

Solution Turn off independent sources add a test voltage 𝑣𝑥 and determine the resulting current 𝑖𝑥. Then 𝑅𝑖𝑛 = 𝑣𝑥 𝑖𝑥⁄ . To turn off a current source, we remove it from the circuit. The circuit to the right indicates the setup to determine 𝑅𝑖𝑛.

The output voltage is 𝑣𝑂 = −𝑣𝑥𝐴𝑜𝑑, no current flows into the inverting input and applying Ohm’s law yields

𝑖𝑥 =𝑣𝑥 − 𝑣𝑂𝑅𝐹

=𝑣𝑥 − (−𝑣𝑥𝐴𝑜𝑑)

𝑅𝐹= 𝑣𝑥

1 + 𝐴𝑜𝑑𝑅𝐹

Since 𝑅𝑖𝑛 = 𝑣𝑥 𝑖𝑥⁄ , it follows that 𝑅𝑖𝑛 = 𝑅𝐹 (1 + 𝐴𝑜𝑑)⁄ .

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Question 8 For the circuit shown, determine 𝐼𝐷 and 𝑉𝐷if the diode has 𝐼𝑆 = 5 × 10−15 A. Assume 𝑉𝑇 = 26 mV. Your answer should be correct to three decimal places. Hints: consider replacing the linear part of the circuit with a Thevenin equivalent; use trial and error for the numerical solution. (6 points) Solution

The Thevenin equivalent voltage and resistance seen by the diode are

𝑉𝑇𝐻 =3080

× 12 = 4.5 V, 𝑅𝑇𝐻 = 𝑅1‖𝑅2 = 18.75K

Original circuit Linear part of circuit replaced with Thevenin equivalent KVL for the equivalent circuit (see figure above) is

−𝑉𝑇𝐻 + 𝐼𝐷𝑅𝑇𝐻 + 𝑉𝑇 ln �𝐼𝐷𝐼𝑆�

⇒ 4.5 = 𝐼𝐷(18.75K) + 0.026 ln �𝐼𝐷

5 × 10−13�

By trying different values for ID we find that with ID = 212 µA the right hand side of the equation above is 4.492 ≅ 4.5 V, so that 𝐼𝐷 = 212 𝜇A is the solution for the current. Then

𝑉𝐷 = 𝑉𝑇 ln �𝐼𝐷𝐼𝑆� = 0.026 ln�

212 × 10−6

5 × 10−13� = 0.517 V

One can also find the diode voltage from the Thevenin equivalent circuit:

𝑉𝐷 = 𝑉𝑇𝐻 = 𝐼𝐷𝑅𝑇𝐻 = 4.5 − (212 × 10−6)(18.75 × 103) = 0.525 V

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Question 9 Consider the 5 V linear power supply below. The load current is 200 mA. The three-terminal regulator has a 50 dB ripple rejection ratio at 120 Hz. The forward voltage for the 1N4002 rectifier diodes is 1 V, and the 680 𝜇F smoothing capacitor has an ESR of 0.75 Ω. (a) Estimate the ripple and average (dc) voltage just before the linear regulator. That is, at point A. (4 points). (b) Estimate the output ripple voltage. (3 points) (c) Estimate the worst-case inrush current through the diodes. Ignore the transformer winding resistance. (4 points) (d) Estimate the efficiency 𝜂 = 𝑃𝐿 (𝑃𝐿 + 𝑃𝑑𝑖𝑠𝑠)⁄ of the power supply. (3 points)

Solution

Part (a) The ripple voltage just before the regulator is

𝑉𝑟 = 𝐼𝐿 (2𝑓𝐶)⁄ = 0.2 (120 × 680 × 10−6) = 2.45 V⁄

The peak voltage before the linear regulator is √2 × 9 − 2𝑉𝐷 = 10.7 V, so the dc voltage is 10.7−𝑉𝑟 2⁄ = 9.5 V

Part (b) The regulator suppresses the ripple voltage by 50 dB, which is the same as a factor 102.5, so that the output ripple voltage is 𝑉𝑟𝑜 = 2.45 102.5 = 7.75 mV⁄

Part (c) The worst-case inrush current occurs when the smoothing capacitor is uncharged and power is applied right when the input voltage to the bridge rectifier crests. This voltage is √2 × 9 = 12.72 V and the current through a pair of diodes and the capacitor is

𝐼inrush =12.72 − 2𝑉𝐷

0.75=

12.72 − 20.75

= 14.33 A

Part (c) 𝑃𝐿 = 𝐼𝐿𝑉𝐿 = (0.2)(5) = 1 W. The power dissipated in the bridge rectifier is 2𝑉𝐷𝐼𝐿 =(2)(1)(0.2) = 0.4 W. The power dissipated by the linear regulator is (9.5 − 5)𝐼𝐿 = 0.98 W. The efficiency is then

𝜂 =1

1 + 0.3 + 0.98= 43.8%

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Question 10 For each op-amp in the circuit show below, the supply voltage is ± 15 V and the slew rate is 3 V/𝜇s. Sketch the output voltages 𝑣𝑂1 and 𝑣𝑂2 for input (b). (8 points)

Solution

For input (a), |𝑣𝑂1|max = 1.5 V. The resulting slew rate at the output of the first amplifier is 1. 5 𝑉/𝜇s, which is less that the amplifier slew rate so the waveform is undistorted, and 𝑣𝑂1 is:

For |𝑣𝑂2|max = (3)(1.5) = 4.5 V. The resulting rate of change at the output of the second amplifier is 4. 5 V/𝜇s. However, this is more than the slew rate, so that the actual rate of change at the output will be 𝟑 𝐕/𝝁𝐬, and 𝑣𝑂2 is

Note carefully the intercept of the voltage waveform with the time axis at 𝑡 = 20.5 𝜇s. The additional 0.5 𝜇s is a result of the slewing of the second amplifier.

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Question 11 An inverting amplifier has a closed-loop gain of −25. The op-amp used has an open-loop gain of 2 × 104, a dominant-pole open-loop response, and a unity-gain bandwidth of 1 MHz.

(a) What is the frequency the op-amp’s dominant pole? (2 points) (b) What is the 3 dB frequency 𝑓3dBof the closed-loop amplifier? (2 points) (c) What is the magnitude of the voltage gain for the closed-loop amplifier at 𝑓 =

0.25 𝑓3dB? (4 points)

Solution

Part (a) Open-loop dominant pole response implies constant GBP, which is 1 × 106. Thus, the dominant pole is at

𝑓𝐷 =1 × 106

2 × 104= 50 Hz

Part (b)

𝑓3dB =1 × 106

25= 40 kHz

Part (c) The closed-loop frequency response is

𝐴(𝑓) = −251

1 + 𝑗(𝑓 (𝑓3dB)⁄ )

At 𝑓 = 0.25𝑓3dB the magnitude is

|𝐴(𝑓)| = 251

√1 + 0.252= 24.25

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Question 12 Find 𝑉𝐷𝑆,𝑉𝐺𝑆 and 𝐼𝐷 for the following MOSFET if 𝐾𝑛 = 100 𝜇A V2⁄ . Assume 𝑅𝐷 = 10K and 𝑉𝑇𝑁 = 1 V. (8 points)

Solution

Solution

KVL around the 3.3 V power supply, load resistor, and MOSFET gives

−3.3 + (𝐼𝐷)(10K) + 𝑉𝐷𝑆 = 0

Note that 𝑉𝐷𝑆 = 𝑉𝐺𝑆 (the gate and the drain are connected together) so that the MOSFET is operating in the saturation region and 𝐼𝐷 = 𝐾𝑛(𝑉𝐺𝑆 − 𝑉𝑇𝑁)2 so that the KVL equation becomes

−3.3 + 𝐾𝑛(𝑉𝐺𝑆 − 𝑉𝑇𝑁)(10K) + 𝑉𝐺𝑆 = 0 −3.3 + (100 × 10−6)(10 × 103)(𝑉𝐺𝑆 − 1)2 + 𝑉𝐺𝑆 = 0

One can solve this quadratic equation using the familiar formula for the roots of a quadratic equation, or using the “solve” capability on many modern calculators, or by graphing the function. Alternatively, one can use a trial-and-error method, trying several values of 𝑉𝐺𝑆. Regardless of the method, the solution is 𝑉𝐺𝑆 = 2.095 ≅ 2.1 V. Then

𝐼𝐷 = 𝐾𝑛(𝑉𝐺𝑆 − 𝑉𝑇𝑁)2 = (100 × 10−6)(2.1− 1)2 = 120 𝜇A

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Homework Assignment 06 - University of Iowas-iihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55041_2013/... · 2013. 10. 13. · Homework Assignment 06 . Question 1 (Short Takes). 2 points