Enabling Double Patterning - Applied Materials · of over 5% with no degradation in electromigration. Special Focus: Enabling Double Patterning 12 Scaling Non-Gridded Layouts with

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Semiconductor

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Enabling Process

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Manufacturers

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Enabling Process

Technology

V o l u m e 7 , I s s u e 1 , 2 0 0 9

In This Issue:• OptimizedHF-BasedHigh-kFilms

• NewLowkBarrierMaterialsforSub-45nmNodes

• BilayerDARCfor30nmLithographyPatterning

• AerialImagingMask-BasedWaferCDUMapping

– New Design Techniques and Patterning Films

Enabling Double Patterning

NTJ71_Cover_v08 LN.indd 1 7/27/09 4:39:53 PM

Publisher: Betty Newboe

Email: [email protected]

Chief Editor: Connie Duncan


Editor: Richard Lewington


Assistant Editor: Priya Gopalakrishnan

Advisory Board: David Kyser, Ph.D.,

Omkaram Nalamasu, Ph.D.

Nanochip Technology Journal is published by Applied Materials, Inc. in cooperation with United Business Media LLC © Copyright Applied Materials, Inc. 2009, for external use.

Cover Art: Jason Sweis, Cadence Design Systems

All trademarks so designated or otherwise indicated as product names or services are trademarks of Applied Materials, Inc. in the U.S. and other countries. All other product and service marks contained herein are trademarks of their respective owners.

Front Cover: Sidewall spacer double patterning design tools decompose a layout into three masks in order to create the final wafer result. From top to bottom, the image shows core mask, resulting spacer pattern, trim mask, pad mask and final wafer result.

www.appliedmaterials.com

Historically, many of the developments in our industry stem from the continued progress in lithography. However, the high risk of next genera-tion patterning methods using alternative exposure and/or mask solutions has made processes that extend optical lithography, such as spacer-based double patterning (SSDP) more attractive. While double patterning process techniques have found adoption in the NAND flash memory products, enhanced design tool capability is needed for more general applications.

In this issue, we report progress in advanced, process-aware design tools that can decompose a random circuit layout into a 3-mask SSDP solution, making DRAM and logic manufacturable at 32nm and 22nm with conven-tional immersion lithography. Meanwhile, an alternative layout technique, gridded design rules (GDR), has gained maturity since we reported the feasibility of this approach last year. In this issue we publish new results that extend the technique to an amazing 11nm half pitch.

We also report on critical supporting technologies for SSDP. A novel bilayer DARC structure simplifies the patterning film stack and reduces the all-important line edge roughness. Aerial imaging technology can help the scanner to compensate for photomask degradation, improving patterning accuracy and squeezing as many wafers as possible from each highly expensive mask.

Aggressively scaled features require further innovation to function correctly. This edition contains a study of different ways to deposit Hf-based, high-k gate material, which is necessary to control leakage current and device switching speed. We also examine the use of plasma nitridation to enhance data retention and minimize crosstalk in flash memory cells. For intercon-nects, a new barrier layer integration scheme has been developed that offers significant k-value reduction and increases electromigration resistance.

I hope that you find all the articles in this issue interesting and stimulating. Please contact me or the article authors if you have any questions.

A Message from Hans StorkGroup Vice President and Chief Technology Officer, Applied Materials' Silicon Systems Group

To receive extra copies of the Nanochip Technology Journal or to add colleagues to the mailing list, please email the following information to:

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Nanochip Technology Journal Issue One 2009 1

Volume 7, Issue 1, 2009

2 Optimizing Hafnium-Based High-k Dielectrics Choice of deposition method, precursor type, interface

layer and post-deposition processes are crucial to successful integration.

7 Enhancing NAND Flash Floating Gate Performance

Increasing densities and decreasing feature sizes require plasma nitridation to improve performance.

22 Improved Patterning Using New Bilayer DARC New DARC process for high NA immersion lithography

demonstrates excellent reflectivity control.

26 Mask CDU Mapping Raises Lithography Cell Efficiency

Aerial imaging-based mask CDU mapping can increase productivity and yield in a wafer production environment.

30 New Low k Barrier Film Reduces RC Delay New k=4.0 film achieves an overall capacitance reduction

of over 5% with no degradation in electromigration.

Special Focus: Enabling Double Patterning 12 ScalingNon-GriddedLayoutswithSidewall

SpacerDoublePatterning

17 GriddedDesignRuleScalingfor22nmand16nmLogic

TOC_v06_LN.indd 1 7/27/09 7:28:41 PM

2 Issue One 2009 Nanochip Technology Journal

Optimizing Hafnium-Based High-k Dielectrics

High-k

In the decade-long search for a suitable high-k gate stack material to enable continued transis-tor scaling, hafnium oxide and hafnium silicates have emerged as the preferred choices to replace SiO2.[1,2] Though both are Hf-based, HfO2

and HfSiO/HfSiON each have specific advan-tages and integration challenges.[3] This article examines how the choice of deposition methods, precursor types, interface layers and post-deposi-tion processes are critical for optimizing high-k integration.

Keywords: High-k, Gate Sta ck, Gate Dielectrics, Hafnium Oxide, Hafnium Silicates, MOCVD

Hafnium oxide (HfO2), due to its higher dielectric constant (k≈25), has captured the majority of high-k interest. However, efforts to develop hafnium silicate (HfSiOx) and hafnium silicon oxynitride (HfSiON) have increased, as low-power device and DRAM makers seek to meet more strin-

gent leakage requirements. Though lower in k-value than HfO2, the greater thermal stability offered by HfSiON is an overrid-ing advantage for these applications.

Deposition TechniquesFor high-k f ilms requiring a thickness range of 15-35Å, metal-organic chemi-cal vapor deposition (MOCVD) has been the standard deposition method. In the MOCVD process, two separate reactants are introduced at the wafer surface. The resulting reaction deposits the desired film, while the residual reactants and byproducts are pumped away.

For thin f ilms, atomic-layer deposition (ALD) provides an attractive alternative. By alternately pulsing the two halves of the chemical reaction, film deposition can be controlled to one sub-angstrom thickness layer at a time. ALD is inherently capable of better thickness control and f ilm uni-

formity than MOCVD, but the process is slower, which presents productivity con-cerns for films thicker than 25Å. In addi-tion, ALD operates at lower temperatures where the elimination of trace elements is more difficult.

Precursor SelectionIn addition to Hf f ilm type and deposi-tion method, there are many Hf precur-sors to choose from. The precursor must be compatible with the deposition method and desired final gate dielectric stack per-formance. For HfSiOx and HfSiON films, the Hf precursor must also be compatible with a Si precursor. The deposition process must also be stable, repeatable, and cost-effective.

Commercially available and production-ready Hf precursors fall into the alkoxy, alkylamino, and halide ligand families (Table 1).[4] The alkoxy group, though compatible with capacitor applications, is generally not used for gate dielectrics due to the possibility of self-oxidation. Both the alkylamino and the halide groups have been used for metal-insulator-metal (MIM) applications in DRAM fabrication and are the primary candidates for depos-iting Hf-based materials. The key differ-ence between these two groups lies in the composition of the ligand: The alkylamino uses an amino-hydrocarbon ligand, and the halide uses halogen species. This difference in chemical formulation leads to different trace elements within the final Hf-bearing film. Trace carbon is the key concern for the aklylaminos. The generation of HCl

Table 1. Production-ready precursors.

Precursor Choices Characteristics Advantages Disadvantages

Alkylamino TEMA-Hf,TDEA-Hf, TDMA-Hf,

• Liquid at ambi-ent temp

• Amino hydro-carbon ligand

• Thermally stable• Low temp delivery• Mature chemistry for

MIM applications

• Carbon byproduct restricts use to high operating temps

Alkoxy HTB • Volatile liquid at ambient temp

• Butal alcohol ligand

• Mature chemistry for MIM applications

• Carbon byproduct restricts use to high operating temps

• Contains oxygen—higher chemi-cal volatility due to potential self-oxidation

Halide HfCl4 • Solid at ambi-ent temp

• Chlorine ligand

• No carbon byproduct • Requires high temp delivery system and chlorine compatible hardware

07-Highk_v07_LN.indd 2 7/29/09 2:51:30 PM


■ Advanced Gate Dielectrics

is the key concern for the HfCl4 halide. Additional hardware is required to pre-vent corrosion and maintain defectivity performance.

ALD of HfO2

Transistor per for-mance is fundamen-tal ly judged by its switching speed and leakage current. The speed i s inver sely related to the equiv-a lent oxide thick-ness (EOT) of the gate dielectric; faster speeds are achieved with thinner EOTs. In contrast, leakage is inversely related to the physical thickness of the gate dielectric. The EOT of a given thickness of material is inversely propor-tional to the material’s dielectric constant relative to SiO2.

EOT = (εSiO2/εhigh-k) Thigh-k

The best combination of speed and leak-age requires a material with the highest dielectric constant. HfO2 with its higher dielectric constant relative to HfSiO is the necessary choice for devices where the highest transistor speed and therefore lowest EOT is most important. Because the film thickness is relatively low (~15Å), ALD is the preferred deposition method.

ALD HfO2 Process OptimizationTo determine the best precursor, MOS capacitors were processed with HfO2

f ilms generated from both alkylamino (TDEA-Hf ) and halide (HfCl4) precur-sors. Results show much higher leakage current ( Jg) from the TDEA-Hf precursor (Figure 1). This may be caused by trace carbon, which generates a higher interface trap density (Dit). The incorporation of trace carbon is also thought to contribute to the degradation of device mobility.[5]

On the other hand, Cl appears to play

l itt le role in determin-ing the f i lm electr ica l per formance, mak ing HfCl4 the preferred pre-cursor to provide an ALD HfO2 f ilm with the low-est EOT.

Deposition temperature has a signif icant impact on the elect r ica l per-formance. Results from MOS capacitor s ind i-cate that the opt ima l deposition temperature is approximately 300°C (Figure 2). Both lower and higher temperatures degrade the electrical per-formance.

Performance degradation below 300°C is believed to be caused by an increase in trace Cl due to insufficient thermal energy to drive complete reaction of the HfCl4. To better understand the degradation at higher temperatures, a physical character-ization using AFM, AR-XPS, RBS, and XTEM was conducted to study the rough-ness, density, and growth rate at 300°C and 500°C (Figure 3). Results show that the 300°C process provides a sl ightly higher growth rate (AR-XPS and XTEM)

and density (RBS) than the 500°C pro-cess. The greatest difference observed is the substantial increase in surface rough-ness for the 500°C process after 40 cycles whereas the surface roughness remains relatively stable at 300°C.

Auger Electron Spectroscopy (AES) mea-surements conducted after 60 cycles show a greater f ilm discontinuity at the higher deposition temperature (Figure 4). Studies demonstrating the suppression of crystal-lization at thinner f ilm thicknesses [6,7]

suggest that the change in surface rough-

1.5E+12

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Figure 2. HfO2 film deposited with HfCl4 precursor at dif-ferent temperatures.



ness indicates the onset of crystallization. Though these high cycle counts represent a film that is much thicker than that typi-cally targeted for current advanced tran-sistor technology, the results highlight

differences in the nucleation and growth behavior at lower cycle counts.

ALD HfO2 Process IntegrationGood HfO2 f ilm characteristics alone are

not suff icient in isolation for suc-cessful integration of the HfO2 f ilm into the high-k dielectric stack. To minimize the tendency of the high-k material to degrade mobility by phonon-induced scattering,[8,9] a thin interface layer is deposited between the silicon channel and the HfO2.

A chemically-grown oxide has com-monly been used to form a thin 5–7Å interface layer. Thermally-grown oxides have historically been less pop-ular due to unacceptable uniformities below ~10Å, but the higher quality and greater stability offered by a ther-mally grown oxide has provided the impetus to develop thinner thermally-grown oxides. By utilizing N2O as the source gas in a radical oxidation pro-cess, thin films can be achieved with equivalent uniformity to a chemical-ly-grown oxide (Figure 5).

Recently, efforts have focused on utilizing an anneal process to further improve EOT scaling. Proper selec-tion of the anneal conditions results in an increase in k-value and subse-quent slight EOT reduction. Results from MOS capacitors show that the EOT shift is about 0.5Å. Work con-tinues in this area.

MOCVD of HfSiOx and HfSiONIn cases where the scaling require-ments are less stringent, HfSiON offers a strong and practical alterna-tive to HfO2. Though the k value is lower, the addition of Si greatly increases the thermal stability ver-sus HfO2, providing more resistance to the downstream processes such as high temperature dopant anneal. The addition of nitrogen into the

f ilm further improves the thermal stabil-ity. The tendency to crystallize has been shown to be completely suppressed for nitrogen content above approximately 10% (Hf,Si =1).[10] The greater thermal

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Figure 4. The film deposited at lower temperature shows a complete absence of the underly-ing Si (blue). The higher temperature HfO2 film exhibits a mixture of both Si and Hf (green), indicating that the underlying Si substrate remains visible.

Figure 3. Measurements for HfO2 deposited with HfCl4 precursor for films at 300°C and 500°C. (Top, left) AR-XPS, (top, right) RBS, (bottom, left) XTEM, (bottom, right) AFM.



stability of HfSiOx/HfSiON makes it the preferred material for gate-first integration.[1,3]

The higher operat ing tem-peratures associated with the MOCVD process (550–700°C) removes the restrictions to pre-cursor selection that affect the low-temperature ALD process. Carbon is burned off at these higher temperatures, thereby making alkylamino precursors acceptable. Both Hf-based and Si-based precursors are readily available.

HfSiON Process OptimizationThe electrical performance of HfSiON can be modulated through changes in the Hf/Si ratio and nitrogen content (Figure 6). Raising the proportion of Hf raises the k-value and decreases EOT at the expense of decreased mobility.[10] Hf content targets currently being pursued are between 50% and 80%, striking a balance between k-value and mobility degradation.

Further improvements to the k-value and sub-sequent EOT scaling can be achieved through the introduction of nitrogen. To avoid addi-tional mobility degradation through the dif-fusion of nitrogen to the channel interface, a

plasma nitridation process is preferred over thermal nitridation processes. The former process is able to limit the nitrogen injected into the top surface of the HfSiO film. This minimizes the generation of interface states and fixed charges associated with thermal nitridation processes that lead to mobility degradation.

The optimal nitrogen content is dictated by its impact on the integration of HfSiON into the CMOS flow. MOSCAP data shows that increasing nitrogen up to 12% provides continuous improvement in leakage and EOT (Figure 7, left). At 20% nitrogen, leak-age reduction is continued at the sacrifice of

EOT scaling. Dit extraction shows that up to 10% N, Dit remains stable and is comparable to values obtained for SiON gates (Figure 7, right). Above 10% nitrogen, Dit increases lin-early—suggesting that the additional nitrogen is leading to increased mobility degradation and that the optimal nitrogen level is approxi-mately 10%.

HfSiON Process IntegrationAn N2O radical oxidation process is the favored choice for the interface layer treat-ment before HfSiON deposition. The resulting SiON interface layer has been well-characterized in volume production for SiON gate technology and provides a stable

WiW Non-Uniformity = 1.77%

≤5.950≤6.000≤6.050≤6.100≤6.150≤6.200≤6.250>6.250

Figure 5. Thickness profile maps for (left) a SC1 chemically-grown oxide and (right) a thermally-grown oxide using a N2O-based radical oxidation process. Both films were targeted for a nominal 6Å thickness.

WiW Non-Uniformity = 0.88%

≤6.050≤6.075≤6.100≤6.125≤6.150≤6.175≤6.200≤6.225>6.225

1E-2

1E-4

1E-6

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EOT (Å)

J g (A

/cm

2 )

75% Hf50% Hf25% Hf

Figure 6. Increasing the Hf/Si ratio reduces EOT at the expense of reduced mobility.

Figure 7. Increasing nitrogen improves (left) Jg/EOT performance at the expense of Dit.(Right) The optimal N content is approximately 10%.

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surface for subsequent HfSiOx deposition. Following the high-k deposition, a plasma nitridation plus post-nitridation anneal is conducted to generate the f inal HfSiON f ilm (Figure 8). All chambers required to complete this process sequence can be completed on a single processing system enabling the full HfSiON dielectric gate stack to be generated without exposing the wafer to the ambient environment.

HfSiON for 3-D Transistors3-D transistor structures such as FinFET designs will require deposition by ALD in order to obtain uniform thickness cover-age along both the sidewall and trench bot-tom. By replacing every other Hf-precursor pulse described with a Si-precursor pulse, a hafnium-silicate film can be deposited in a “nano-laminate” fashion. Despite differences in deposition method, both MOCVD and ALD-deposited HfSiON films demonstrate similar electrical properties.[11,12] Excellent

step-coverage performance is seen with the ALD process.

ConclusionsA number of choices are available when depositing an Hf-based high-k dielectric film. Proper selection of deposition method and precursor type is necessary to best optimize the dielectric film. Additionally, the choice of interface layer and post-deposition processes can be critical to the successful integration of the high-k dielectric gate stack into a CMOS device. The complete f ilm stack including the high-k dielectric film, the preceding thermal-based inter-face layer, and post-deposition pro-cessing can be completed on a single system. Eventually, to continue scal-ing, transistor high-k dielectrics with even higher k-values will be required. Derivatives of HfO2 such as HfZrO[13]

are being investigated, as well as other materials, including HfCeO, HfLaO, HfTiO and Zr-based oxides. The ultra-thin gate dielectric requirement will require ALD to be used as the deposition method, but each of the

candidate materials will introduce their own integration challenges. ■

AcknowledgementsThe authors thank the engineers in Applied’s Maydan Technology Center group, the Defect and Thin Film Characterization Laboratory group and the Metal Deposition Products group for their contributions.

References[1] E.P. Gusev et al., IBM J. Res. & Dev., vol. 90, no. 4/5,

p. 387, 2006.[2] R. Chau et al., IEEE Elect. Dev. Lett., vol. 25, no. 6, p.

408, 2004.[3] R. Arghavani et al., Nanochip Technology Journal,

Vol. 5, no. 2, p. 2, 2007.[4] A. Soulet et al., Semicondutor Fabtech, Vol. 27,

2005.[5] D. Triyoso et al., J. Appl. Phys., Vol. 97, 2005.[6] H. Kim et al., Appl. Phys. Lett., vol. 84, no. 12, p.

2064, 2004.

[7] S.C. Song et al., IEEE Trans. Elec. Dev., vol. 53, no. 5,

2006.[8] M.V. Fischetti et al., J. Appl. Phys., vol. 90, no. 9 p.

4587, 2001.[9] Z. Ren et al., Symp. VLSI Technol., p. 793, 2003.[10] K. Sekine et al., IEDM Tech. Digest, p. 102, 2003.[11] A. Rothschild et al., Symp. VLSI Technol., 2007.[12] W. Deweerd et al., Future Fab International, vol. 20,

p. 96, 2006.[13] D.H. Triyoso et al., J. Vac. Sci. & Tech., vol. 25, p.

845, 2007.

AuthorsDavid Chu is in global product management with Applied’s Front End Products (FEP) group. He received his Ph.D. degree in materials science and engineering from the University of California, Berkeley.

Steven Hung is an integration engineer in Applied’s FEP group. He is responsible for process integration in metal gate and high-k applications. Steven received his M.S. and Ph.D. degrees in elec-trical engineering from Stanford University.

Houda Graoui is a process technologist focusing on HfSiOx gate stack applications in Applied’s FEP group. She earned her Ph.D. degree in materials science from the University of Marseille, France.

Article Contact: [email protected]

Applied Centura® Advanced Gate Stack

Process System Used

• Combines high-k, DPN, oxidation and anneal on a single platform

• Innovative high-k chamber designed for thermal and flow stability

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Avg: 47.80ÅWTWNU: 0.21% WIWNU: <1.6%

Figure 8. Results of a fully integrated process sequence including interface layer formation through a N2O based radical oxidation, MOCVD HfSiOx deposition (50% Hf target), plasma nitri-dation (15% N target) and post-nitridation anneal demonstrate excellent process stability.

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N%


Enhancing NANDFlash Floating Gate Performance

DPN

To ensure device performance while decreasing the feature sizes in advanced NAND f lash devices, additional process steps such as plasma nitridation have been introduced. This article reviews the challenges of integrating plasma nitridation and the solutions being pursued to overcome them.

Keywords: Plasma Nitridation, NAND Flash Floating Gate

A NAND f lash f loating gate (FG) memory cell is comprised of a thick tunnel oxide (TO), a polysil icon FG, an inter-poly dielectric (IPD) and a control gate (CG) (Figure 1). The poly FG is isolated from the channel by the TO and from the CG by the IPD. A program/erase (P/E) operation is used to set the memory state of the device. During the program operation a positive voltage is applied to the CG, injecting elec-trons from the channel into the FG. The stored electrons shift the threshold voltage (Vt) of the transistor, indicating the “1” state. During the erase operation a nega-tive voltage is applied to the CG to expel the stored electrons from the f loating gate into the channel, resetting the Vt to the “0” state.

The difference between the program Vt and erase Vt is referred to as the memory win-dow and is a key device parameter defining the range of operation. At all other times, the memory cell is in retention mode, where the cell terminals are grounded.

The FG should retain the stored charge for at least 10 years. However, charge loss can occur when charge leaks through defects in the dielectric films (either TO or IPD) surrounding the FG, causing a Vt shift that will eventually compromise the iden-tification (read-out) of the memory state. Therefore, retention of the FG charge is a key requirement for reliable operation.

Meeting device reliability requirements becomes more diff icult with the physical scaling of the FG array. At each technol-ogy node, the number of electrons stored in the FG decreases from, for example, approximately 1,000 electrons at the 90nm node to ~100 electrons at the 30nm node. Therefore, the impact on Vt for each elec-tron lost from the FG will be much greater at 30nm than at 90nm. One consequence of this has been that the TO thickness has

not been reduced with device scaling and has even increased in thickness slightly to improve charge retention.

Another challenge is the scaling of the IPD film stack thickness — typically from 150Å at the 50nm node to 125Å at the 30nm node. This results in a correspond-ing reduction in equivalent oxide thick-ness (EOT), or capacitance, a change that is required to maintain good electrical cou-pling between the CG and FG. However, as the thickness of the IPD stack is reduced, leakage from the FG is more likely to occur. Hence, improvements in the IPD electrical properties are essential to limit leakage with continued scaling.

To enable continued physical and electrical scaling of the f lash device, plasma nitrida-tion can be used to improve the properties

Channel

Control Gate

Floating Gate

Tunnel Oxide

IPDBottom Nitridationof IPD

Top Nitridation ofTunnel Oxide

Top Nitridationof IPD

Source Drain

Figure 1. Floating gate memory cell structure in the bitline direction showing plasma nitridation applications.


■ Nitrided Gate Dielectrics

of the TO, bottom IPD, and top IPD layers of the FG device (Figure 1). In the following sections we examine the methods of integrating nitride for each of these key applications.

Tunnel OxideThe tunnel oxide presents a scaling chal-lenge with conf licting requirements. The f ilm must be of high quality and capa-ble of retaining a charge for >10 years. Because leakage is a tunneling phenome-non, charge retention is better for thicker oxides and decreases exponentially with reduced f i lm thickness. On the other hand, thinner TO enables shorter P/E times for a given operating voltage. Also, every P/E cycle places electrical stress on the tunnel oxide. This stress may gen-erate defects or traps in the oxide or at the interfaces, causing additional leakage paths and reducing FG retention. Typical specif ications require suf f icient post-cycling retention after 105 P/E cycles.

Incorporat ing nitrogen with thermal processes such as NO or N2O anneals at the interface between TO and the sili-con channel has been used historically to improve tunnel oxide reliabil ity. [1]

Nitrogen at the Si/SiO2 interface replaces weak Si-H or dangling interface bonds

with a strong Si-N bond. This improves the interface stability and makes it more resistant to defect generation during P/E operation. However, incorporating nitro-gen in the bulk of the tunnel oxide is undesirable since it becomes a trap gen-eration site during P/E operation. This constrains how much nitrogen can be incorporated at the interface.

Incorporation of nitrogen at the interface between TO and FG polysilicon is expect-ed to offer a similar reliability benefit as observed with nitrogen at the bottom of TO. In addition, bird’s beak reduction is observed with nitrogen at the TO and FG polysilicon interface. Plasma nitridation is the ideal process for incorporating nitrogen on the top surface of a SiO2 film since the process is surface dominated as opposed to other techniques such as thermal nitri-dation (e.g., NH3 anneals). However, the process must be carefully designed to minimize plasma damage to the SiO2 film and reduce N2 incorporation into the bulk oxide. A “soft” plasma with low ion ener-gy and low electron temperatures can be achieved by pulsing the RF power supply (Figure 2). The low ion energy of this pro-cess, called Decoupled Plasma Nitridation (DPN), reduces plasma damage and results in surface nitridation of the SiO2.

EOT scaling can be achieved by incorpo-rating nitrogen into the top of the tunnel oxide. Increasing the nitrogen content on the top of the TO by DPN has the same effect on memory window as physically scaling the tunnel oxide (Figure 3). As shown in Figure 3, the plasma nitrided TO follows the same memory window vs. EOT trend as physically scaling the TO. However, rather than decreasing the physical thickness to achieve a smaller EOT, the plasma nitrided TO will have a physically thicker f ilm due to the incor-poration of nitrogen. This thicker dielec-tric f ilm can maintain the retention while scaling EOT. This benef it can be seen in Figure 4 which shows the post-cycling retention of the plasma nitrided TO is improved compared to TO’s without plasma nitridation for the same EOT or memory window.

The integration scheme and unit pro-cess conditions strongly affect the oxide quality and device performance. Figure 5 shows stress-induced leakage current (SILC) for a number of different inte-gration schemes. Sequences with DPN show better SILC performance compared to the basel ine SiO2, RTNO anneal-only conditions, or NH3 annealed SiO2. Post-nitr idat ion annea l (PNA) using

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Continuous RF

kTe

(eV)

Duty Cycle10%20%30%40%50%60%70%100%

10.4

10.3

10.2

10.1

10.0

9.9

9.8

9.7

9.6

9.5

9.4Memory window (Fresh device)VP/E-VFB=±16V (100µs/1ms)

9.367 69 71 73 75 7765

EOT (Å)

14%

7%

0%

SiO2 baseline

Anneal + DPN

Mem

ory

Win

dow

(V)

70Å SiO265Å SiO2

70Å SiO2 + RTNO anneal + 14% DPN

70Å SiO2 + RTNO anneal (no DPN)70Å SiO2 + RTNO anneal + 7% DPN

Figure 2. Langmuir probe data showing how plasma pulsing can be used to produce low ion energies at low pressure.

Figure 3. Reduction of EOT with DPN nitridation offers a similar memory window improvement vs. physical scaling; however, this is achieved without degrading the retention performance.



N2 at 950°C after the DPN process also improves SILC. Overall, the condition with DPN followed by RTNO (1100°C) anneal shows the best SILC. Further study is required to determine if this improvement is f rom the NO chem-istry or the much higher temperature (1100°C) of the RTNO anneal com-pared to the PNA step (950°C).

Inter-Layer Poly DielectricFuture scaling of the IPD to reduce EOT can be accomplished through modif i-cation of IPD with plasma nitridation. The standard IPD f i lm is an ox ide/nitride/oxide (ONO) dielectric stack. Using plasma nitridation below the bot-tom oxide and above the top oxide, an N-ONO-N f ilm is formed.

IPD Bottom Nitridation The FG polysilicon is doped with phos-phorus to provide a conducting f i lm. Dur ing subsequent high temperature processing in forming the IPD stack, the phosphorus can diffuse out from the FG polysi l icon sur face. Loss of phos-phorous results in depletion of the poly at the poly/IPD interface; this creates a thin insulating poly f ilm and increas-es the overa l l EOT of the IPD stack. Suppressing phosphorous out-diffusion is thereby equivalent to reducing the IPD EOT. A nitr ided polysi l icon sur-face serves as a diffusion barrier to pre-vent phosphorous out-dif fusion from the polysilicon during subsequent high temperature IPD deposition.

Ni t r id a t ion o f t he po l y i s e a s i l y accompl i shed with DPN. However, dur ing th i s proces s n it rogen i s a l so incorporated in the STI ox ide f i lm. Unfortunately, nitrogen incorporated in the STI oxide between neighboring FG cel ls can provide a charge leakage path. [2] The degree of charge leakage wil l depend on the amount of nitrogen incorporated in the STI and this wil l set an upper l imit on the bottom IPD nitr idat ion process achievable on the

FG poly. Therefore, the most desi r-able process should resu lt in h igh N incorporation into the FG poly while having little N incorporation into the STI oxide.

There are two approaches to increase the selectivity of nitr idation (amount of nitrogen in the FG poly compared to the amount of nitrogen in the STI oxide). One approach is by process and hardware optimiza-t ion o f t he DPN step it sel f . A more ef fect ive approach is a 2-step approach (“select ive removal sequence”) consist-ing of DPN plasma nitridation followed by a selective nitro-g en r emova l s t ep t o r emove n i t r o -gen f rom the STI regions.

The selective remov-a l sequence use s a therma l ox id at ion p r o c e s s ( R a dO x ) after the DPN nitri-dation. The RadOx

process removes most of the nitrogen f rom the STI SiO2 reg ions w ithout s ign i f icant ly chang ing the n it rogen in the FG poly. When oxid izing the nitr ided si l icon, the nitrogen stays at the Si inter face, a l lowing the growth of SiO2 above the nitrided interface. As a result, a thin SiO2 f i lm with nitro-gen at the SiO2/Si interface is formed. Figure 6 shows nitrogen prof i les for a DPN of Si, and DPN of Si fol lowed by

0%

7%14%

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.09.4 9.6 9.8 10 10.2 10.49.2

Memory Window (V)

Improved retention atsame memory window

Post

-Cyc

ling

Rete

ntio

n Lo

ss (V

)

SiO2 baseline

Anneal + DPN

Memory window at VP/E-VFB=±16V (100µs/1ms)

Post 104 cycles retention loss after 100hrs at25°C with starting ∆VFB =8V

70Å SiO265Å SiO2

70Å SiO2 + RTNO anneal + 14% DPN

70Å SiO2 + RTNO anneal (no DPN)70Å SiO2 + RTNO anneal + 7% DPN

10-11

10-12

10-13

68 70 72 74 7666

EOT (Å)

SILC

(A)

SiO2 BaselineRTNO annealRTNO anneal + DPNRTNO anneal + NH3 annealRTNO anneal + DPN + PNA (950°C)DPN + RTNO anneal (1100°C)

Figure 5. Of several integration schemes tested, DPN followed by RTNO anneal showed the best leakage current performance.

Figure 4. Plasma nitridation of top tunnel oxide improves the post-cycling retention for the same fresh (uncycled) memory window (i.e. same EOT).



RadOx. The RadOx proce s s u sed for select ive removal did not signif i-cantly affect nitrogen dose (Ndose) in

Si. A comparison of selectivity for the two approaches is shown in Figure 7. Changing processes (A vs. B) or using

d i f ferent chamber hardware (B) can slightly improve the “as-nitrided selec-tivity” but the selective removal pro-cess can virtually eliminate nitrogen on the SiO2 without losing the nitrogen in the polysi l icon. One consequence of the select ive removal approach is the smal l growth of an oxide f i lm on the Si region. However, by optimizing the thermal ox idat ion process condit ion this addit iona l th ickness growth can be restr icted to a few angstroms.

IPD Top NitridationThe main requirement for top nitrida-tion is to reduce the EOT of the oxide f i lm without sacrif icing the reliability or retention properties of the dielectric f ilm. When incorporating nitrogen into SiO2 the dielectric constant of the SiO2

increa se s w ith increa s ing n it rogen, reducing the f ilm’s EOT. The reduction of EOT fol lows a fa i r ly l inear t rend with increasing nitrogen. Electrical ly, the incorporation of nitrogen reduces the high f ield leakage (Figure 8). For an actual f lash device it is expected that the FG retention wil l begin to degrade at high levels of nitrogen incorporation because more of the nitrogen wil l be incorporated below the oxide sur face into the bulk and wi l l provide leak-age paths and trap generation sites. By using a “soft” plasma, the DPN process can mitigate plasma damage to the SiO2

f ilm. In addition, the DPN process can ef fect ively incorporate nitrogen into the top IPD SiO2 f ilm at very high rates (<60s recipe times) — a key benef it in volume manufacturing.

ConclusionsPlasma nitr idation has multiple appli-cat ions in the format ion of the FG device gate stack and can enable con-t inued sca l ing to the 3Xnm technol-ogy node and beyond. By using DPN and process integration sequences for the tunnel oxide, a more reliable tun-nel oxide can be formed compared to

2 4 6 8 10 12 140

Depth (nm)

DPN of SiNitrogen at Top Surface

DPN of Si followed by RadOxNitrogen at SiO2/Si Interface 102

103

104

105

101

100

SIM

S Co

ncen

trat

ion

(ato

ms/

cm3 )

Coun

ts P

er S

econ

d

Oxygen count before processOxygen count after processSilicon count before processSilicon count after process

Figure 6. SIMS Nitrogen profile of silicon surface after DPN and after selective nitri-dation sequence. Nitrogen is retained at SiO2/Si interface after the selective removal sequence.

6

5

4

3

1

2

05 10 150

Ndose on Silicon (x1015 atoms/cm2)

Selectiveremoval

Increasingas nitridedselectivity

Ndos

e on

SiO

2 (x1

015 a

tom

s/cm

2 )

Process AProcess B Single step (DPN)Hardware B2 step Selective removal process(DPN + RadOx)

Figure 7. Comparison of selectivity (N on Si vs. N on SiO2) of single step DPN processes and the selective removal sequence. Superior selectivity is obtained with the selective removal sequence as almost no N remains in the SiO2 film while high N remains in the Si.



the conventional tunnel oxide without plasma nitr idat ion. Using both DPN and thermal oxidation, a highly selec-t ive process sequence can be used to incorporate high levels of nitrogen into the FG poly with very little nitrogen in the STI oxide. DPN can also quickly incorporate h igh level s of n it rogen with high throughputs into the top IPD oxide for additional EOT scaling of the IPD stack.

AcknowledgementsThe authors would like to thank Dirk Wel lekens, Jan Van Houdt, and Aude Rothschild from IMEC for their col-laborat ion on f la sh device electr ica l test ing and ana lysi s of f loat ing gate foundry lot devices from IMEC.

References [1] J-G Lee et al., Int. Rel. Phys. Symp., 2007.[2] C.Y. Ho et al, IEEE Elect. Dev. Lett., 2008

Johanes Swenberg isglobalproduct

manager of Appl ied ’s Gate Stack and

DielectricProductsunit,responsiblefor

productmarketing , l inemanagement

andproductdevelopment.Hereceived

his Ph .D. in appl ied physics from the

CaliforniaInstituteofTechnology.

David Chu iswithglobalproductman-

agementinApplied’sFrontEndProducts

group.HereceivedhisPh.D. inmateri-

als scienceandengineering from the

UniversityofCalifornia,Berkeley.

Theresa Guar in i i s a process eng i -

n e e r i n A p p l i e d ’ s G a t e S t a c k a n d

DielectricProductsunit .Shereceived

aPh.DinappliedphysicsfromStanford

University.

Yonah Choisamemberoftechicalstaff

inApplied’sRTPProductsunit,focused

onapplicationdevelopmentand f lash

customerengagement .He receiveda

Ph.D.inmaterialsscienceandengineer-

ing from theUniversityofCalifornia ,

Berkeley.

Udayan Ganguly iscurrentlyadevice

and integrationengineer inApplied’s

Ga te Stack and D ie lec t r i c P roduc t s

un i t , r e spons i b l e fo r t h e deve l op -

mentofapplicationsforflashmemory

technologies .HeearnedaPh .D. from

CornellUniversityandaB .Tech. from

IIT,Madras.

Lucien Date isaprocesstechnologist

with Appl iedMater ia ls in Europe . He

is involved ingatestackdevelopment

andintegration.HereceivedhisPh.D.in

electricalengineeringattheUniversity

ofPaulSabatierinFrance.

Authors

Article contact: [email protected]

Process System Used in Study

• Combines oxide growth, gate

nitridation (DPN), post-gate

nitridation (PNA) and poly-

silicon deposition on a single

platform

• Demonstrated 10x leakage

reduction

• Provides high Ndose within-

wafer uniformity resulting in

tighter Vt distributions

-8

-9

-10

-11

-12

-13

-14

-1555 65 857545

EOT (Å)

Leakage reductionfor same EOT

Leak

age

Indi

cato

r

Top surface nitridationSiO2 trendline

Figure 8. Top IPD nitridation improves leakage performance compared to SiO2 at the same EOTs. EOT measured by Corona-Oxide-Semiconductor method.

Feature : S i dewa l l Space r Doub l e Patte rn ing

Sidewall spacer double patterning, also known as self-aligned double patterning (SADP), is now the primary double pat-terning approach adopted by f lash memory manufacturers. It is particularly suitable for regular one dimensional designs and cur-rently delivers the best pitch control of the three double patterning techniques.[1,2,3]

Furthermore, it can be implemented with existing factory equipment and low capi-tal spending for development and volume manufacturing.

Many manufacturers are now looking to migrate SSDP to DRAM and logic lay-ers. However, these layers do not have the repeating features that have made SSDP so well-suited for f lash devices. DRAM and especially logic have far more complex layout requirements than f lash—which requires a more sophisticated use of the SSDP technique.

The SSDP process f low includes:

• Lithographytodefineasacrificialtem-plate or core pattern.

• Resisttrimandtemplateetch.• Spacerdepositionandetch.

• Removalof the sacrificial template(positive flow) or removal of spacer after gapfill/planarization (negative flow).

• Deviceetchingandhardmaskstrip.

One attribute of SSDP is that for each single line (resist) in the template, there are two lines formed (spacers) that ulti-mately form a closed loop at the ends of the line. Therefore a designer must determine where to position the original template and where to trim away sec-tions of the spacer in the second mask. An automated electronic design (EDA) tool is required to optimize the 2-mask combinations.

After the sidewall spacers are formed, all features contain only one linewidth, determined by the sidewall spacer width. A third mask (periphery or pad) is some-times applied to create two dimensional shapes that cannot be formed by a side-wall spacer pattern alone. An EDA tool can automatica l ly ca lculate the opti-mized mask set for template, trim and periphery. Examples of layout optimiza-tion for DRAM gate and random logic patterns are shown in Figures 1 and 2.

Automatic Decomposition for SSDPLayout Decomposition SoftwareThere are many considerations that go into developing a production-worthy software tool to support an SSDP f low. The f inal layout artwork data (typically GDS format) is a physical representa-tion of a well-characterized electr ical schematic that must account for manu-facturing constraints. For example, an SSDP decomposit ion tool, OPC, and l itho simulat ion tools f rom Cadence have been ful ly integrated to create a “virtual fab” at the early development stages when design rule checks (DRC) and mask constra int s are f i r st being examined.

SSDP requires three f inal masks after a single drawn layer has been decomposed. These are the core, trim, and pad masks. Core is the f irst step (Figure 1)—that creates the smal lest pitch features. To pattern core features smaller than can be printed by the scanner, the mask is made with features larger than target (positive bias) and the PR on the wafer is subse-quently shrunk to the f inal CD.


An automated layout separation tool for sidewall spacer double patterning (SSDP), capable of solving 2-mask and

3-mask features has been successfully demonstrated. This development brings the capability of SSDP to the application

of DRAM and logic patterns at the 32nm and 22nm technology nodes.

Keywords: Sidewall Spacer, Double Patterning, Self-Aligned, Layout Decomposition, SSDP, SADP.

Sidewall Spacer Double PatterningSidewall Spacer Double PatterningSidewall Spacer Double PatterningSidewall Spacer Double PatterningScaling Non-GriddedLayouts with

04_Sidewall_v06_LN.indd 12 7/29/09 2:37:55 PM

■ Non-Gridded SSDP ■ Non-Gridded SSDP

Trim is the second mask step performed after the spacer has been created, which trims away unwanted material, particu-larly around the core end loops. Trim can be very complicated because it is the most constrained by mask and scanner rules for minimum polygon aspect ratio. This minimum aspect ratio dictates the minimum pitch lines that can have sec-tions tr immed. As in the core mask, a positive CD bias is applied to the trim mask features to make printing easier. The overlay offsets and CD biases must be factored into the size of the trim poly-

gon when considering design rules for wet or dry scanners. A trim mask is then generated considering process window, overlay, and mask rules in the parameter setup of the decomposition tool.

The pad mask contains the features on the target layer that were not created with spacers. To ease manufacturing, the mask set should be as minimally criti-cal as possible. Thus the design software should minimize the complexity of cer-tain features such that only one mask (usually the core) requires an immersion

tool, while the remaining masks can be done with dry scanners.

Design Decomposition and Compliance for Logic and Memory The SSDP full-chip decomposition tool takes the layout target, automati-cally generates the 3 mask layers and returns them to the design database. A re-composition step is performed to verify that all the masks recombine cleanly to form the target layer as drawn. In addition, overly constrained areas where MRC or DRC rules can-not be met are f lagged with markers so the user can go back and quickly edit or measure.

An interactive decomposition followed by OPC and l itho simulat ion is then possible within the same environment. This workf low al lows rapid develop-ment of design and mask ru les for a given technology node. The decompo-sition process is extremely fast and pro-vides many heuristic methods to tackle design types such as logic or memory patterns. The decomposed layers are designed to be OPC-friendly, especially in SRAF placement. This is achieved by extending core lines or adding trim length where appropriate. In general, it is more eff icient to make a design library SSDP compliant from the lower cells up to reduce design rework.

Core MaskTarget Pattern

Spacer Trim Mask Pad Mask Final

Figure 2. Example of an EDA layout split for a hypothetical 2-D logic pattern with 3-mask flow.

Core Mask Spacer Trim Mask Pad Mask Final Target Pattern

Figure 1. Example of an EDA layout split for a hypothetical DRAM bitline pattern with 3-mask flow.


Sidewall Spacer Double PatterningScaling Non-GriddedLayouts with

04_Sidewall_v06_LN.indd 13 7/29/09 2:37:57 PM

■ Non-Gridded SSDP

Experimental WorkLithography ProcessThe core mask is typically the most aggres-sive, requiring resolution two times the f inal device critical pitch. In the case of 22nm half-pitch, the core mask would require a 44nm half-pitch, requiring an immersion scanner tool. The trim mask and the pad mask, however, will have resolution requirements that are highly dependent on

the design. To minimize manufacturing costs, it is desirable to use a dry scanner for these masks. Therefore, separate litho and MRC parameters are used in the EDA tool for the trim and pad mask to repre-sent the characteristics of a dry scanner. A 6% attenuated phase shift mask with core, trim, and pad features in different areas of a single mask plate was taped out for this work. The performance of an immersion

scanner versus a dry scanner for the trim mask was compared to explore process window and cost tradeoffs.

For l ithography, we used an ASMLXT:1900i immersion scanner (maximum NA=1.35) linked to a Sokudo RF3S track system to pattern the core and test trim masks.AnASMLXT:1400edryscan-ner (maximum NA=0.93) l inked to a Sokudo RF3S track system was used to pattern the tr im mask and pad masks. The tr im mask occasional ly required post-lithography chemical shrink tech-niques to reduce the trench or contact hole CDs by 10-15nm.

Deposition and Etch ProcessesThe project focused on proving the lay-out separation and process f low for poly gate or STI patterning. A stack compris-ing a gate oxide, polysilicon and oxide hardmask typical for this layer was used, on which we deposited CVD amorphous carbon as the template. After etching the template, a CVD nitride spacer f ilm was deposited. The spacer was etched and the remaining amorphous template removed with an oxygen ash. The trim mask was then applied using a BARC to partially planarize the sidewall spacer topography before exposing the trim pattern.

When per forming the tr im etch, we developed two processes. The standard production process is a single-step etch that removes BARC and the n it r ide spacer with the same etch rate, stopping on the oxide hardmask. A second etch process was developed that etched the BARC, yet was highly selective to the nitride spacer. This process was used for recessing the BARC enough to al low alignment inspection of the resist pat-tern to the sidewall spacers.

DiscussionTrim Mask ResultsAll SSDP designs need a trim mask to rework the landscape of spacers into the target circuit structures. Some designs

Sidewall Spacer Pattern Trim Mask (BARC Etched) Transfer Etch

Core Mask Splitwith Spacer Simulated

Trim Mask Design Target

Figure 3. (Top) EDA split and (bottom) on-wafer results for 35nm half-pitch DRAM STI pattern.

Trim Mask Design Trim Litho & Etch

Etch

Pad Mask Design Comb-Serpent

Figure 4. 3-Mask process flow for patterning a 26nm half-pitch comb-serpentine test structure.

Figure 5. EDA layout separation for making H-Bar structures common in logic applications.

H-Bar Example A H-Bar Example B Line Resistance



can be formed without the third pad mask, using only the trim mask, includ-ing DRAM STI islands, logic SRAM poly, and gr idded design rule (GDR) layouts. Figure 3 shows the layout split and on-wafer results for 35nm half-pitch DRAM STI islands. To obtain a f inal ha l f-pitch a f ter SSDP, the f i r st core mask requires a l ithographic pitch of 140nm, patterned with cost-ef fective dry l ithography. The tr im mask had a dense array of contact holes at a pitch of 140nm, reaching the dense contact hole re solut ion l im it of the ASML1400e. However, despite the aggressive design, we observed suff icient depth-of-focus (DoF) of 180nm. Therefore, 35nm half-pitch STI islands can be manufac-tured using only dry 193nm lithography tools.

Pad Mask ResultsFigure 4 shows the mask design and wafer results for a comb-serpentine test structure. Parallel lines formed by SSDP trimming are referred to as “tines”. The SSDP process forms a l l the t ines at a 26nm half-pitch, after which the tr im mask removes line-end sections. Finally, the pad mask links the tines to create the serpent and def ine the probe pads and comb attachments. The CD on this pad mask is the space between the adjacent serpent l inks, which is approximately 1.5 pitches or 78nm. The a l ignment requirements fol low simi lar rules for the trim mask, which is 1/4 pitch max-imum, though 1/6 or 1/8 pitch is bet-ter to give higher manufacturing yield. The key process challenge is obtaining the correct f inal post-etch CD, which should be compensated for by applying post-etch OPC. Figures 5 and 6 show the formation of generic “H-Bar” and line resistance test structures achieved by using a 3-mask SSDP process f low.

The cha l lenges of OPC in SSDP are mainly in trim and pad mask. Figure 7 shows overlapped GDS v iews of the target, OPC layer, and simulated con-

tours for the tr im and pad mask in 2 and 3-mask f lows, using STI islands and comb-serpentine patterns as examples.

ConclusionsWe have demonstrated the development of an SSDP automated layout separation tool capable of solving for 2-mask and 3-mask features for DRAM and logic patterns. Designers select the lowest cost l itho tool set, input appropriate MRC rules, and the tool will notify the design-er of rule violations requiring modif ica-tion to f it within the low-cost patterning strategy. On-wafer data shows that dry 193nm lithography has suff icient DoF to pattern all three masks for 32nm half-pitch SSDP process f lows. The alignment tolerance was tested to 10nm which is near the per formance of modern dry scanners. Thus, an all-dry litho approach is within reach for the 32nm node. For the 22nm half-pitch node, immersion scanners are required for template and

trim mask, but dry lithography may be used for the pad mask 2.

AcknowledgementsThe authors would like to thank the engi-neers at Applied’s Maydan Technology Center, the Advanced Patterning Solution group at Cadence for OPC and layout sup-port,andSokudoCo.,Ltd.andSpansion,Inc.for immersion lithography process support.

References[1] Chris Ngai et al., “32nm Self-aligned double patterning

for flash and DRAM”, Semicon Europe, Oct. 2008.

[2] M.C.Chiuetal.,“Challengesof29nmhalf-pitchNAND

FlashSTIpatterningwith193nmdrylithographyand

self-aligneddoublepatterning”,Proc.SPIELithography

Asia-Taiwan,2008.

[3] Woo-YungJungetal.,“Patterningwithamorphous

carbonspacerforexpandingtheresolutionlimitof

currentlithographytool”,Proc.ofSPIE,Vol.6520,2007.

Line Resistance Tester H-Bar Example A H-Bar Example B

Figure 6. On-wafer examples of H-Bar structure formation. Half-pitch ranges from (left) 26nm to (center, right) 32nm.

2-Mask STI Patternat Trim Mask

3-Mask Comb-Serpentineat Trim Mask and Pad Mask

Figure 7. Examples of trim and pad mask target, OPC layer, and simulated contours. The simulated contours matched very well with wafer images.



Huixiong Daiisaseniormemberofthetech-nicalstaffatApplied’sMaydanTechnologyCenter (MTC), responsible for advancedlithographyprocessdevelopment,includingimmersionlithography,RET/OPC,anddoublepatterning.HereceivedhisM.S.degreefromtheRochesterInstituteofTechnology,NY.

Jason SweisistheseniorproductengineeringmanagerofAdvancedPatterningSolutionsatCadenceDesignsystems.HeholdsaB.S.E.E.fromManhattanCollegeinNY.

Chris Bencher isamemberofthetechnicalstaffatAppliedMaterials,exploringmultipleformsofdoublepatterning.HegraduatedfromtheRensselaerPolytechnicInstituteandU.C.Berkeley.

Yongmei Chen isaprocessengineerwithApplied’sMTCgroup,responsiblefor32nmandbeyondSADPetchprocessdevelopment.SheearnedherPh.D.insemiconductorphysicsanddevicesfromtheInstituteofSemiconductors,ChineseAcademyofScience,P.R.C.

Jen Shu is thedirectorof technologyatApplied’sMTC,responsiblefordevelopingshort loopsfornextgenerationtechnolo-gies.JenreceivedherB.S.inchemicalengi-neeringfromCaltechandherM.S.andPh.D.degreesinchemicalengineeringfromCornellUniversity.

Xumou XuisaseniormemberofthetechnicalstaffandalithographymanageratApplied’sMTC.HeearnedhisPh.D.insolidstatephysicsfromFloridaAtlanticUniversity.

Chris Ngai isthedirectorofprocessandlithoengineeringatApplied’sMTC,focusedondevelopingdoublepatterningschemestoextendlithotothe32nmhalfpitchandbeyond.ChrisreceivedhisM.S.degreefromSantaClaraUniversity.

Judy Huckabay isamanufacturingtoolsdeveloperatDirect2Silicon,Inc.,workingondoublepatterningandRETsolutions.JudyhasbeenamemberoftheIEEEforover20years.

Milind Weling isanengineeringdirectoratCadencewiththeImplementationProductsgroup,leadingmanufacturingproductsandsolutionsaddressingdesigntosiliconpro-ductizationchallenges.MilindhasanM.S.E.E.fromtheUniversityofHawaiiandaB.TechinEEfromIIT,Bombay.

Authors


© SPIE. Republished with permission from SPIE Proceedings Vol. 7275, Design for Manufacturability through Design-Process Integration III, 2009.


Systems Used in Study

Applied VeritySEM™ 3 Metrology

• Robust pattern recognition, automation for high production throughput

• High-resolution imaging for fea-ture edge roughness monitoring, feature shape control

• Proven capabilities for lithogra-phy and SSDP control

Applied Centura® AdvantEdge™ G5 Silicon Etch

• Enables SSDP with optimized LER, CD uniformity and profile control

• On-board WIW control supports patterning technology for 3X and beyond

• Delivers <± 1% depth uniformity for STI using SSDP flow

Applied Producer® GT

• High productivity for >30 CVD applications

• Flexible process integration for thin and thick film deposition

• Excellent particle performance

Sokudo RF3S Track

• Flexible system design supports immersion ArF lithography pro-cesses

• High reliability platform capable of 180WPH throughput


■ TSV Etch TechnologyAdvanced Patte rn ing

Gridded Design Rule Scaling for 22nm and 16nm Logic

The scaling capability of gridded design rules (GDR) to 16nm and 22nm logic nodes was dem-onstrated. 1-D layout examples, such as the Intel 45nm Penryn polysilicon layer[1,2] and metal layer design clips from Tela Innovations[3–5,7,9]

were scaled to a final pitch of 64nm, 52nm and 44nm using sidewall spacer double patterning (SSDP). Mask sets were made to enable demon-stration of both polysilicon gate layer (clearfield) and damascene (darkfield) GDR layouts.

Keywords: Sidewall Spacer, Double Patterning, Self-Aligned, SADP, SSDP, Gridded Design Rules.

The term gridded design rules refers to a layout architecture in which each device layer has circuits snapped to a pre-deter-mined grid with a f ixed pitch. The most litho-friendly version of GDR further conf ines the layout to para l lel l ines printed in one direction, of one CD, on one pitch (Figure 1). Line ends, contact holes and vias are positioned only at pre-determined grid points.[3,4,5] There are several well-documented advantages to designing with GDR:

• Simplif iedphotolithography [4] suit-able for specia l ized i l luminat ion modes.

• E l im inat ion of many prox im it yef fects complicat ing l itho, [4] etch and OPC.

• Improved linewidth control in etchand litho.[6]

• Reduced number of design rules.[2]

• Reduced leakage current.[6,7]

• Neut r a l impac t or reduced d iesize.[2,4]

• Ease of scaling.

At the 45nm node and below, most 1-D GDR-like designs are being made with a “line-and-cut” double patterning tech-nique.[2,3,8,9] This results in very pre-cise tip-to-tip spacing, prevents line-end shortening/bridging issues and enables closer tip-to-tip designs leading to cell area reduction opportunities. The line-and-cut double patterning technique is alsokeytoenablingthe i l luminationoptimization (dipole) for the para l lel lines.Thecutmaskbecomesthechal-lenge when sca l ing these GDR l ine-and-cut designs. However, simulation results have shown that available immer-sion scanners should be adequate down

to the 22nm logic node.[5] This paper presents on-wafer results for 22nm and 16nm logic nodes.

GDR Scaling TechniquesScaling 1-D GDR line and cut layoutsrequires independent solutions for scal-ing the paral lel l ine pitch, and the cut maskandassociatedalignment.

Parallel Line ScalingThe scaling of parallel lines has already been solidly demonstrated down to 22nm half-pitchusingSSDPtechniquesandhasbeenimplemented in mass production by memory chip manufacturers whose critical layers are dominated by large regular arrays of paral-lel lines.

According to the scaling roadmap (Table 1), theindustryisshrinkingata“70%ofpreviouspitch” model for each advancing technology node. This table summarizes the lithogra-phy tool and strategy transition points and

Figure 1. (Left) An example of a logic cell designed in GDR by Tela Innovations.[4] (Right) Detail of the Intel 45nm Penryn poly gate layer with a GDR-like layout.[2]


■ Gridded Design Rule Scaling

shows that GDR enable one set of scanners to be used for three technology nodes.

Cut Mask ScalingThe scaling of the cut mask is far morecomplicated. For the polysi l icon gate layers,thecutmaskwouldbeadarkf ieldmaskcomposedmostlyofisolatedslotsand holes. The minimum CD of the slot or hole would be approximately the same as the pitch. This can be achieved when combining immersion lithography withstrongRETandpost-lithographychemicalshrinktechniques.

For the metal layers 1&2, constructed us ing Cu damascene and requ i r ing

trenchetch, thecutmaskwouldbeabr ightf ieldmaskcomposedmostlyofisolatedresist“plugs”toblocktrenchetch where copper l i ne break s a rerequired(Figure2).Inthistone,apho-toresisttrimstepcanbeusefultoshrinkthe resist plug to size.

The alignment specif ication of the cut maskcanbeapproximatedby1/8thepitch. This assumes that the edge of a slot is located in the center of a space, and has the freedom to be misal igned ha l f the distance to the nearest l ine. Thus, for the 32nm, 22nm and 16nm logic nodes, the most aggressive align-ment requirements for the cutmask

would be roughly 12nm, 8nm and 5nm based on anticipated meta l 1&2 layer pitches (90 –100nm for 32nm log icnodeshrinkingwith70%scalingrule).These alignment values are well within published values for scanners currently available or announced.

Poly Gate Patterning for 22nm, 16nm Logic NodesThe goal of this demonstration was to takesome1-Dlayoutexamples, sucha s the polys i l icon l ayout shown by Intelfromtheir45nmPenryn™CPU2(Figure 1) and test the sca l ing to the 22nm and 16nm technology nodes. We electedtoshrinkthepolypitchdownto 65nm and 52nm, which is far more aggressive than what is forecast for these layers.WealsolookedatshrinkingtheSRAMtoaf inalpitchof44nm.ThesepitchesrequireSSDPtoachieveparallelline density.

Weusedaphase-shiftmaskonanASML1900iimmersionscannertopatterntheinitialcoreatpitchesof128nm,104nmand 88nm simultaneously. The resist pattern result s for the pitch of 88nm (Figure 3, f a r lef t) were : l inewidth (CD) uniformity less than 2nm (3σ) and aline-edgeroughness(LER)lessthan2.5nm (3σ). We then followed a typical SSDPprocess f low [9-15] (Figure 3) to double the l ine density. The pattern-ingresultsofSSDP [9-15] readily deliver linewidth CD uniformity and linewidth roughnesslessthan5%ofhalf-pitch.

ThecutmaskwasalsoexposedonanASML1900iimmersionscanner,usingadarkf ieldphase-shiftmask,planarizingthe spacer topography with a spin-on BARC.Themaskwasdesignedtofabri-cate 1, 2 and 5 line cuts (Figure 4), which mimic the 45nm clip seen in Figure 1. Afterexposingthecutmask,thepro-cess f low continued with a BARC etch, spacer cut etch, ash and poly etch. This left us with the f inal 1-D GDR line-and-cut polysil icon pattern, at pitches

Table 1. Anticipated pitch requirements for GDR parallel line scaling (Foundry Logic).

Figure 2. (Top) Schematic of darkfield cut mask for poly gate patterning and (bottom) bright-field cut mask for metal 1 and 2 damascene trench.

Resist

Oxide HardmaskPoly

Gate Oxide

BARC

Resist

M1, M2 Oxide

BARC

Parallel Line Pitch (nm)

Process Flow Litho TechniqueLogic Technology Node

45nm 32nm 22nm 16nm

200 — 120 Single exposure 193nm dryPoly, M1, M2

Poly

120 — 80 Single exposure 193nm immersion M1, M2 Poly

80 — 60 SSDP 193nm dry M1, M2 Poly

60 — 40 SSDP 193nm immersion M1, M2



representative of the 22nm and 16nm nodes (Figure 4).

To explore the process tolerance to mis-al ignmentandcutsize, themaskwasdesigned with f ive a l ignment of f-set combinat ions (zero, ±3, ±5nm) and maskdrawnCDbiascombinationsof±5nm. We analyzed the results of the cutmaskpatterningacrossthesealign-mentandmaskCDbiases.Inthe32nmhalf-pitch (22nm logic node) case, we see successful cut formation across the entire process window indicating that this process f low has robust tolerance for CDcontroloftheslots(atleast10nm)and can accept misa l ignments up to ±5nm (Figure 5).

Inasimilarprocesswindowstudyfor26nm half-pitch poly patterning (16nm node), we started to observe some acci-denta l cut migrat ion to neighbor ing lines. This is noticeable in the +3nm and +5nmoffset(+5nmmaskbias)seeninFigure 6. The root cause of the migra-tion of the cut to the neighboring lines was determined to be CD gain (con-tact hole enlargement) observed during etch processes. We believe this can be eliminated using a combination of etch process optimization, optimization of the(post-lithography)chemicalshrinkprocess(SAFIER™andCSX™)forCDand resist prof ile, and post-etch optical proximity correction.

Metal 1&2 Damascene Trench Patterning for 22nm and 16nmMetal layers 1 and 2 have traditionallyhad the most aggressive pitch require-ments for patterning. Current designs at the 32nm node are showing metal layer pitchnear100nm.Ifoneweretoshrinkbythe70%rule,thenoneshouldplanfor~70nmpitchforthe22nmnodeand~50nmpitchforthe16nmlogicnodes.We demonstrated damascene trench pat-terning in the context of 1-D GDR lay-outs at a pitch of 52nm, close to 16nm noderequirements(Figure7).SSDPwas

Litho88nm pitch

Etch CoreDeposit Spacer

Etch SpacerAsh Core

22nm Half-Pitch

Sidewall Spacer Image22nm line and space

Cut Mask afterChemical Shrink & BARC Etch

22nm Node Poly Pattern(64nm Line Pitch)

16nm Node Poly Pattern(52nm Line Pitch)

-5nm Offset

+5nmDesign

Bias

-5nmDesign

Bias

-3nm Offset 0nm Offset +3nm Offset +5nm Offset

-5nm Offset

+5nmDesign

Bias

-5nmDesign

Bias

-3nm Offset 0nm Offset +3nm Offset +5nm Offset

Figure 4. Examples of poly gate patterns, fabricated by line-and-cut double patterning using SSDP to achieve pitches of 64nm (22nm node) and 52nm (16nm node).

Figure 3. SEM images at key steps of the SSDP process flow.

Figure 6. Process window study for cut mask patterning for poly at 26nm half-pitch (16nm node). Some cut migration is observed (yellow arrows).

Figure 5. Process window study of cut mask patterning for poly at 32nm half-pitch (22nm node). Results show successful patterning across the entire process window.



performed over silicon oxide and bright-f ieldcutmaskpatterning(Figure2)wasperformed to create the oxide bridges. A process window study showed successful patterning across the ±5nm alignment offsetrangeandacrossa7%dosevaria-tion (Figure 7).

SRAM Scaling to 16nm and 11nm In high-performance logic, SRAM mayconsume over half of the overall die area. MostSRAMstructuresalreadyuse1-Dpatterning for the poly layer, and several designs have implemented line-and-cut double patterning starting at 45nm.[2,8]

TheIBMalliancehaspreviouslyshownexamples of 22nm technology node (90nmpitch)polypatterningforSRAMcellsof0.1µm2 size (Figure 8). Using theline-and-cutSSDP,wescaledthosepolypatterns down to the 11nm technology node (44nm pitch).

Conclusion1-D GDR layout architecture offers the opportunity to reduce die size, improve electricalperformanceandmakelayoutseasier to scale for lithography and etch. By combining the exceptional performance of SSDP,with a l ine-and-cut processf low, this paper demonstrates the ease of scaling with GDR circuit layouts to the 16nm consumer logic node and below. We have demonstrated successful patterning oflogicandSRAMGDR-likepatternsinhalf-pitch ranges of 32nm/26nm/22nm. Through the study we demonstrated an acceptable patterning process window (litho and etch) that could be improved further by employing additional resolu-tion enhancement techniques.

AcknowledgementsThe authors would like to thank the sci-entistsatApplied’sMaydanTechnology

Center and the double patterning team, ourcollaboratorsforuseoftheASML1900i,TelaInnovationsforadvancingthedesign tools and capabilities of GDR, and Cadence for automated sidewall spacer layout fracture and OPC support.

References[1] K. Mistry et al., IEDM December 2007.

[2] Clair Webb, Proc. of the SPIE Vol. 6925, 692503,

2008.

[3] M. Smayling, Proc. of the SPIE Vol. 6925, 69250B,

2008.

[4] M. Smayling, Nanochip Technology Journal,

Volume 6, Issue 2, 2008.

[5] M. Smayling, Proceedings of the SPIE Vol. 7274,

7274-19, 2009.

[6] Ewoud Vreugdenhila, Proc. of SPIE Vol. 6925,

69250D-2, 2008.

[7] S Kornachuk and M. Smayling, International

Symposium on Physical Design, March 30, 2009,

slides available from http://www.ispd.cc/slides09/

s3p2.pdf.

[8] H. Zhuang et al, Semiconductor Technology ISTC

2007, Proc. Vol. 2007-01, 154, 2007.

[9] M. Smayling et al., Proc. of SPIE Vol. 6925, 69251E,

2008.

[10] C. Bencher, SEMI Technology Symposium, Chiba,

Japan, December 2007.

[11] C. Bencher, SEMI Technology Symposium, Chiba,

Japan, December 2008.

[12] C. Bencher et al., Proc. of SPIE Vol, 6924, 69244E,

2008.

[13] C. Bencher, Semiconductor International,

September 2008.

[14] Christopher Borst et al., 24th Proc. Advanced

Metallization Conference, Albany, NY 2007.

[15] C. Bencher, SEMI Technology Symposium, San

Francisco, July 2008, http://www.semiconwest.

org/cms/groups/public/documents/web_content/

ctr_024381.pdf

[16] B.S. Haran et al., paper #27.1, IEDM, December

2008.

-5nm Offset

26mJ

30mJ

0nm Offset +5nm Offset

90nm Gate Pitch Actual Pitch 52nm Actual Pitch 44nm

0.1µm2 SRAM cell22nm Technology

16nm Node

11nm Node

Figure 7. 26nm half-pitch damascene trench patterning demonstration for 16nm logic node GDR. Successful patterning was observed across entire process window.

Figure 8. (Left) State-of-the-art example of SRAM poly patterning.[16] (Center and right) Scaling demonstrations using SSDP plus line-and-cut double patterning down to the 11nm technology node.



Systems Used in Study

Applied Centura® AdvantEdge™ G5 Silicon Etch

Applied SEMVision® G2 FIB Defect Analysis

• Automatic defect review and root cause analysis

• On-board automated FIB cross-sectioning

• Patented ClearCut technology optimizes SEM, FIB and EDX

Applied Producer® PECVD

APF Process

• High etch selectivity, CD control and reduced LER

• Integrated with DARC in bilayer stack for excellent reflectivity

• Extends conventional photore-sist trim processes

Nitride Spacer Process

• Deposits highly conformal nitride spacer film with low thermal budget

Sokudo Track RF3S

• Flexible system design supports immersion ArF lithography processes, including top-coat coating and removal

• High reliability platform sup-ports throughput of 150WPH

• Flexible modular hardware and electrical design reduce manufacturing lead time and set up

Applied VeritySEM™ 3 Metrology

• Robust pattern recognition and automation

• High resolution imaging for fea-ture edge roughness monitoring, feature shape control

• Lithography and SSDP control

• Minimal ArF shrinkage enables tight resist metrology


© SPIE. Reproduced with permission from Proceedings Vol. 7274, Optical Microlithography XXII, 72740G, SPIE 2009.

Authors

• Optimized LER, CD uniformity and profile control

• On-board WIW control supports patterning technology for <3Xnm

• Delivers <± 1% depth uniformity for STI using SSDP flow

Christopher Bencher is a member of the technical staff at Applied Materials, explor-ing multiple forms of double patterning. He is a graduate from Rensselaer Polytechnic Institute and UC Berkeley.

Huixiong Dai is a senior member of techni-cal staff with Applied’s Maydan Technology Center (MTC) group, responsible for advanced lithography process development, including immersion lithography, RET/OPC and double patterning. He received his M.S. degree from the Rochester Institute of Technology, NY.

Yongmei Chen is a process engineer with Applied’s MTC group, responsible for 32nm and beyond SADP etch process development. She earned her Ph.D. in semiconductor physics and devices from the Institute of Semiconductors, Chinese Academy of Science, P.R.C.


PECVD

A PECVD bilayer dielectric anti-ref lective coating (DARC) process has been developed for high numerical aperture (NA) immer-sion lithography. The scheme demonstrated excellent ref lectivity control and was capable of patterning 30nm linewidths with a wider lithography depth of focus (DoF) than conven-tional bottom anti-ref lective coating (BARC) schemes and comparable line edge roughness (LER).

Keywords: DARC, PECVD, Immersion Lithography

Immersion lithography has been increas-ingly adopted by semiconductor manu-facturers to extend feature sizes to 50nm half-pitch and beyond. With increasing NA and decreasing DoF, thinner pho-toresist is required, especially in double patterning processes. This poses a consid-erable challenge because high selectivity to underlayers is required to complete the pattern transfer without resist clear-ing. Another chal lenge resulting from

increased NA is maintaining low ref lec-tivity over a wider range of incidence angles. As the NA exceeds 1.0, a tradi-tional organic BARC alone is not suf-f icient to keep ref lectivity below 1.0 — which is critical for CD control.

A new bilayer DARC scheme has been designed to addres s these h igh NA lithography chal lenges. In addition to acting as an anti-ref lective layer, the DARC layer can also serve as a hard-mask for underlayers such as Advanced Patterning Film (APF), an amorphous carbon material. APF is widely used as a hardmask in memory devices and as a core material for sidewall spacer double patterning (SSDP) schemes for 32nm half-pitch and beyond.

ExperimentsFilm PropertiesThe bi layer DARC f i lm is deposited in a parallel-plate capacitively-coupled

plasma reactor. The process chemistry consists of SiH4, an oxidizer and inert gases. The oxidizer and process condi-tions can be tailored for different photo-resist types to prevent resist poisoning.[1]

The DARC f ilm is a non-stoichiometric si l icon oxide with tunable refract ive index (n) and ext inct ion coef f icient (k) achieved by varying the gas f low ratio. As the ratio of SiH4 to oxidizer is increased, the number of Si-O-Si bonds decreases and the number of Si-H bonds increases. The k value is mainly driven by Si-H bonds, which absorb l ight in the deep UV range of the spectrum. The effect of gas f low ratio on f ilm compo-sition is shown in the FTIR spectra in Figure 1. The n and k correlation of the DARC f ilm follows a tight distribution that represents the achievable process regime with a given process chemistry. The achievable range of n and k val-ues for two typical DARC processes is shown in Figure 2.

0.25

0.20

0.15

0.10

0.05

0

0.30

1250 1200

Si-O-Si

IncreasingSiH4: oxidizer ratio

1150 1100 1050 1000 950 9001300Wave Number (cm-1)

Abso

rban

ce (a

.u.)

-0.010

-0.015

-0.020

-0.025

-0.030

-0.035

-0.040

-0.045

-0.005

2350 2300

Si-H

IncreasingSiH4: oxidizer ratio

2250 2200 2150 2100 2050 20002400Wave Number (cm-1)

Abso

rban

ce (a

.u.)

Figure 1. FTIR spectra of DARC film with varying SiH4 to oxidizer ratios.

Improved Patterning Using New Bilayer DARC


Reflectivity ControlA lithography simulator was used as a design guide to determine the opt i-ca l propert ies of the f i lms to achieve minimum ref lectivity from the DARC-photoresist interface. To study the most aggressive patterning step, a poly-gate etch f ilm stack was used for the simula-tion, consisting of a 105nm-thick photo-resist layer over the bilayer DARC f ilm, deposited on top of 60nm of APF.

Two methods for minimizing ref lectivity were studied. One method used graded DARC material where the optical proper-ties varied continuously from the bottom to top interface to enable complete light absorption. The disadvantage of graded DARC is that the f ilm properties cannot be easily monitored due to the diff iculty of creating a complex ellipsometry model. The second approach used a bilayer DARC f ilm where the bottom layer acts as an absorbing layer while the top DARC layer enables phase shift cancellation.

Simulation results showed that a bilayer DARC f ilm i s c apable of reduc ing ref lect ivity below 0.5% , a requ i rement for h igh NA immersion l ithogra-phy. We opt im ized the upper DARC layer based on a bottom DARC layer with a higher k value. A ref lectivity below 0.3% is achievable for a 1.35 NA immer s ion l i thog raphy process with a total DARC thickness of 40nm. In com-parison, the ref lectivity of 40nm-graded DARC was found to be 2%. In fact, the ref lectivity of graded DARC falls below 0.5% only at thicknesses above 100nm. Such DARC thickness may pose a considerable chal-lenge for pattern transfer from photoresist to DARC, where the typical photoresist thickness for immersion lithography is 100nm.

With the bilayer DARC scheme, the total DARC thickness is 40nm and eliminates the BARC layer (typically 25–90nm) so that the etch margin is greatly improved for pattern transfer from photoresist to the DARC layer. This scheme also elimi-nates the need for an additional BARC etch step. A cost benefit would be realized

■ DARC for Immersion Lithography

Split B

44

36

3432

30

28

38

40

42

Dose in mJ/cm2

-0.09 -0.06 -0.03 0 0.03 0.06 0.09 0.12-0.12Defocus (µm)

CD (n

m)

262728293031

Split C

44

36

3432

30

28

38

40

42

-0.09 -0.06 -0.03 0 0.03 0.06 0.09 0.12-0.12Defocus (µm)

CD (n

m)

2425262728

Dose in mJ/cm2

Figure 4. Lithography process window comparison for DARC schemes. Bilayer DARC exhibits the widest DoF and smallest achievable feature size. (Top) Split A: Bilayer DARC, minimum CD 30nm with DoF > 150nm, (middle) Split B: single layer DARC, minimum CD 32nm, (bottom) Split C: single layer DARC+BARC, minimum CD 36nm.

1.90

1.85

1.80

1.75

1.70

1.65

1.95

0.20 0.4 0.6 0.8 1 1.2k at 193nm

n at

193n

m

DARC ADARC B

36

3432

30

28

38

40

42 Split A

44

-0.09 -0.06 -0.03 0 0.03 0.06 0.09 0.12-0.12Defocus (µm)

CD (n

m)

Dose in mJ/cm2

24252627282930

-0.010

-0.015

-0.020

-0.005

0

-0.025-50 -100 -150 -2000

Film Stress (MPa)

Chan

ge in

k V

alue

Figure 3. Correlation between k value stability and film stress in the DARC film.

Figure 2. Range of n and k values for two DARC processes.


by eliminating the spin-on BARC material and BARC coating pro-cess steps.

DARC Film StabilityThe opt ica l proper t ies of the bilayer DARC were tuned based on simulation results. Without a BARC layer on top of the DARC layer, it is important to ensure that the DARC film is resistant to moisture absorption and oxidation. This is especially important dur-ing the photoresist rework process when the DARC f ilm surface is

exposed to oxygen plasma. The shelf life of the DARC film was found to be correlated with film stress where a high compressive stress is desirable for stable optical proper-ties. The correlation between the k value stability over 3 days and film stress is shown in Figure 3. Based on this data, we devel-oped a DARC process with a compressive stress of -190MPa. This film had a k change of <0.02 over 10 days.

Immersion Lithography EvaluationThe patterning performance of the bilayer DARC scheme versus other conventional DARC and BARC schemes with a 1.35 NA immersion lithography process was compared. In each case, the DARC opti-cal properties and BARC thickness were optimized for minimum ref lectivity. The single layer DARC with BARC stack is commonly used with APF where the DARC f ilm acts as a hardmask for pat-tern transfer from photoresist to APF. The

APF is then used as a hardmask for pattern transfer to dielectric underlayers. Since the BARC layer also promotes adhesion between the photoresist and the DARC layer, the adhesion performance between the DARC layer and the photoresist was also evaluated.

Results and DiscussionImmersion Lithography PerformanceThe immersion lithography process was per-formed on an ASML 1900i scanner with 1.35 NA, using TOK Pi6001 photoresist material and a 90nm pitch line/space pattern. A focus exposure matrix (FEM) was performed on each split to determine the lithography process window (Figure 4).

The measured CD values of the printable lines are plotted as a function of focus condition for different exposure doses. The process window is commonly defined as the DoF for a given feature size. For example, comparing bilayer DARC (Split A) to single layer DARC (Split B), the bilayer DARC shows larger DoF at the 30nm linewidth. The minimum linewidth has a robust process window of 30nm for the bilayer DARC, as compared to 32nm for the single layer DARC. For DARC+BARC (Split C), the minimum linewidth is 36nm. The improvement in the process window and CD control may be attributed to the low reflectivity of the bilayer DARC stack.

The lithography performance on a full wafer was also evaluated. A summary of the data is shown in Table 1. The minimum CD achieved


56

54

52

50

48

461 2 3 40

Rework Cycle

5

4

3

2

1

0

Aver

age

CD (n

m)

CDU

3 σ (%

)

CD CDU

a

b

c

Figure 5. Cross-section SEM images of 90nm line/space pattern of (a) bilayer DARC; (b) single layer DARC; (c) single layer DARC+BARC.

5.0

4.5

4.0

3.5

2.5

3.0

2.01 2 3 40

LER

(nm

)

Rework Cycle

Figure 6. (Left) CD variation, CD uniformity and (right) LER performance of bilayer DARC after multiple rework cycles.

Split StackSimulated

Reflectivity

90nm Pitch Line/Space

Average CD (nm)

CD Unif (3s, nm)

LER (nm)

LWR (nm)

ABilayer DARC

<0.3% 34 2.0 2.3 3.8

BSingle layer DARC

<1.5% 33 1.8 2.2 3.8

C

Single layer DARC + BARC

<0.5% 40 1.7 2.4 4.2

Table 1. Summary of patterning performance of DARC schemes.


for single and bilayer DARC is 33–34nm, as compared with 40nm for the DARC+BARC scheme. The CD uniformity, LER and lin-ewidth roughness (LWR) are comparable between the DARC and BARC splits.

Cross-section SEM images of a 90nm pitch line and space pattern are shown in Figure 5. The photoresist profile of bilayer DARC is

vertical without footing, which is comparable to the DARC+BARC split. On the other hand, the single layer DARC split shows a slightly tapered profile. The difference in profile between the bilayer and single layer DARC may be attributed to the lower ref lectivity of the bilayer DARC stack.

Rework PerformanceAnother merit of the DARC material is its rework capa-bility. The DARC film is an inorganic material that is resistant to oxygen-based ashing chemistry. After pho-toresist stripping, there is no need to redeposit a DARC layer as would be required in the case of a BARC scheme.

The patterning performance of bilayer DARC was evaluated after up to 4 rework cycles. The average CD variation was 1nm, overall CD uniformity was <2nm and LER was <3.5nm (Figure 6). The effect of DARC shelf life on patterning performance was also evaluated. The adhesion of photoresist to the DARC remained good after 3 weeks of exposure to atmosphere.

DARC Film ManufacturabilityA 2,000-wafer marathon was conducted to prove the manufacturability of the bilayer DARC process (Table 2). Film properties, uniformity and defects were stable during the marathon, validating the manufacturability and feasibility of bilayer DARC as a cost-effective solution for immersion lithography applications.

ConclusionsA bilayer DARC process has been developed for high NA immersion lithography. The pro-posed scheme demonstrated excellent ref lec-tivity control and was capable of patterning 30nm linewidths with a wider lithography DoF than conventional BARC schemes and comparable LER. The bilayer DARC also demonstrated stable CD performance after multiple rework processes and excellent shelf life. By eliminating the need for a BARC layer, the etch margin is greatly improved for pattern transfer from photoresist to the DARC layer. Additional benefits include cost savings of spin-on BARC material and coat-ing process steps. Finally, the manufactur-ability of a bilayer DARC process was proven with a 2,000-wafer marathon.

AcknowledgementsThe authors would like to thank Dena Blanco and Ricardo Ramirez of Applied Materials for the cross-section SEM images.

References[1] S. Ahn et al., “Resist poisoning-free advanced PECVD

anti-reflective coating (ARC) for 90 nm technology and beyond,” Materials Research Society Proceedings, Symposium A, Vol. 782, Fall 2003.


Authors

2,000-Wafer Marathon Performance

Bottom DARC Layer

Top DARC Layer

Thickness

Within-wafer thickness non-uniformity (range/2%)

1.4 1.5

Within-wafer thickness non-uniformity (1 s %) 0.8 0.8

Wafer-to-wafer thickness range (range/2%) 1.7 0.8

Optical properties at 193nm

Within-wafer n range 0.004 0.008

Within-wafer k range 0.0 1 1 0.025

Wafer-to-wafer n range 0.005 0.003

Wafer-to-wafer k range 0.0 14 0.009

Stack film defects

Average particle adders >90nm 7

Maximum particle adders >90nm 15

Shelf life (193nm)

Change in n value 10 days after deposition <0.01 <0.01

Change in k value 10 days after deposition <0.01 <0.02

Table 2. Summary of bilayer DARC 2,000-wafer marathon.

Applied Producer™ DARC

Process System Used

• Reduces reflectivity to <0.5%• Offers wide tuning range of refractive

index and extinction coefficient values• Compatible with advanced integration

schemes• Minimizes photoresist poisoning

interaction

Betty Tang is a member of technical staff with Applied’s Blanket Dielectric Films division work-ing on DARC process technology development. She received her M.S. in chemical engineering from Stanford University.

Martin Seamons is a senior process technology manager with Applied’s Thin Films group. He has a B.S. in chemical engineering from UC Berkeley and has completed his master’s coursework in chemical engineering and materials science from San Jose State University.

Michael Lin is a process engineer with Applied’s Blanket Dielectric Films division, responsible for the development of APF and DARC films. He

received his masters degree in chemical engi-neering from UC Berkeley.

Huixiong Dai is a senior member of technical staff with Applied’s Maydan Technology Center (MTC) group, responsible for advanced lithogra-phy process development, including immersion lithography, RET/OPC, and double patterning. He received his M.S. degree from the Rochester Institute of Technology, NY.

Yijian Chen is a process engineer with Applied’s MTC group, responsible for lithographic R&D. Yijian earned a Ph.D. in EECS department from UC Berkeley.


Presented at the 215th meeting of the Electrochemical Society (ECS). Reproduced with permission of the ECS.


Mask CDU Mapping Raises Lithography Cell Efficiency

Lithography

Critical dimension uniformity (CDU) map-ping of photomasks based on high-density aerial imaging technology has been demonstrated to increase productivity and yield in a wafer pro-duction environment. Feeding these maps for-ward to advanced process control (APC) systems significantly reduced the amount of traditional CD metrology required for robust wafer CDU correction. This in turn improved the lithography process window and yield, and contributed to lowering the cost and cycle time of mask quali-fication. In addition, the CDU fingerprint cor-rection of environmentally-induced mask changes extended mask cleaning intervals and overall mask life.

Keywords: Photomask, Reticle, IntenCD, CDU, DoseMapper, Scanner, Haze Defects

The contribution of photomasks to wafer CDU and overlay budget becomes signifi-cant in the extreme low k1 regime. This is due to an increase in the mask error enhancement factor (MEEF) for single-shot lithography and overlay, and CDU sensitivity between layer mask set pairs in double patterning. Significant amounts of within-die, or intrafield CD variations, in addition to CD variation across the wafer, create unevenly distributed line variations on the wafer.

Interfield variations have low-order spatial frequency distributions while intraf ield variations can consist of both low and high

order distributions. For low frequency variation, a small amount of sampling across the wafer using CD-SEM or OCD metrology can satisfy the CDU monitor-ing and correction mechanisms. As long as the mask error contribution is small, low frequency across-wafer sampling is adequate. But as the mask error contribu-tion increases, CDU errors must be cor-rected to meet the ITRS requirement (e.g., 2.8nm for the 40nm generation).[1]

To reach this requirement, the combined interfield and intrafield fingerprint modu-lations must be monitored and translated to optimize corrections in the slit and scan directions via the scanner dose recipe. The latest scanners permit higher order poly-

nomial corrections in both directions. In order to take full advantage of the hard-ware correction potential, the latest APC systems now accept a direct input of the mask fingerprint.

Aerial Imaging Technology for CDU MappingInnovative IntenCD technology is now available that uses aerial imaging data to cre-ate a high-density mask-based wafer CDU map. Averaging the aerial image intensity, or grey level (GL), over a pre-defined area (Figure 1), the technology utilizes a direct linear relation between the CD error and the average intensity in the aerial image of periodic patterns. The theory and operating principles of this technique are well docu-

Figure 1. (Left) A high-density map of mask-induced CD variations using IntenCD technol-ogy with colors indicating regions of similar relative CD values. (Right) The data is highly correlated to individual wafer CD values.[2]

35

34

33

32

31

30

29

28

27 28 29 30 31 32 33 34 35

Inte

nCD

(nm

)

Wafer CD (nm)

R2 = 0.964


mented and enable the creation of high-defi-nition, high-precision mask-based wafer CD uniformity maps with full mask coverage in about one hour.[2, 3]

CDU Mapping of the Litho Cell Mask-based wafer f ingerprint monitoring and dynamic feed-forward correction can be added to lithography workf lows with minimal overhead. In fact, the signif i-cantly higher throughput and high def i-nition of the new technology, compared with conventional metrology tools, actu-ally improves mask availability by moni-toring mask condition and optimizing mask clean scheduling (Figure 2).

The mask-based CDU contribution can be divided into two elements: static and dynamic. Static CDU is captured at a g iven t ime, par t icularly as the init ia l mask state measured in the mask shop during f inal mask qual i f icat ion, or at pre/post-cleaning steps. Dynamic CDU evolves during cumulative mask expo-sures in the scanner and while the mask is in storage.

The tradit ional method of generating CDU information is to create a CD-SEM map consisting of discrete measurement locations that sample the mask at a low fre-quency. However, this map captures only a fraction of the available CDU informa-tion and may not accurately represent the CD uniformity prof ile. High-def inition IntenCD maps provide signif icantly more

detail, showing smooth contours and high spatial resolution (Figure 3).

Measuring Static CDU The intrafield CDU is generally considered a static parameter induced by the mask itself and is not commonly viewed as a candidate for extensive monitoring. However, for the 4Xnm node and below, intrafield measure-ments are critical to correctly estimate the static CDU fingerprint. Higher sampling density translates to better CDU assessment, accurately revealing the fingerprint contour and enabling better CDU correction strat-egy.[4] Another advantage of high-definition aerial image-based intrafield maps is that the CDU is measured directly from the in-die

structures. CD-SEM-based methods often require special metrology structures outside of the device area to avoid photoresist shrink-age from the CD-SEM electron beam.

Figure 4 shows that a full coverage map can reveal details that normally would not be captured with a traditional sampling scheme. In this example, the dark frames indicate locations in slit and scan directions that nor-mally would be omitted.

■ Critical Dimension Uniformity Mapping

Figure 2. Inserting high-definition CDU mapping into lithography cell workflows can opti-mize on-wafer yield and maximize mask lifetime.

Figure 4. The full coverage map provided by IntenCD technology reveals field edge effects not seen by traditional metrology sampling methods.

Mask Path Data Path

Scanner

CDUdeterioration

Feed-forwardto scanner Aera2

IntenCD CDUmonitoring

Aera2IntenCD CDUmonitoring

CleaningCDU correctionvia DoseMapper

CDU inspec?

YES

NO

Mask stocker

New Mask

IntenCD sampling:300,000 locations;max 106 locations/hr

CD-SEM sampling:154 locations;~600 locations/hr

Figure 3. IntenCD technology detects 1nm mask-based CD variations over 25µm areas at wafer level, displaying much finer detail than traditional CD-SEM-generated maps.


The high-density map can reveal hot spots such as CD drop issues that are some-times found in the periphery of the die.[5]

Therefore, static high-density mask-based CDU capturing allows enhanced mask-based assessment for CDU compensation, increased mask coverage and greater mea-surement precision for in-die structures.

Tracking Dynamic CDU Variations The mask-based CDU fingerprint changes in a non-linear manner during its lifetime. This is due to repeated exposure to deep UV radiation, haze, pellicle degradation and cleaning effects (Figure 5).[6, 8] Since

the limited throughput of the tradition-al metrology tools allow only sporadic wafer intrafield monitoring, when a wafer CDU excursion is identified, yield is often impacted. The mask must be sent for clean-ing and pellicle replacement at the mask shop, increasing cycle time and negatively affecting productivity. Cleaning a mask too often also causes premature feature damage and reduces mask lifetime, raising the per-wafer mask cost.[7]

High-density mask-based CDU map-ping decreases mask requalif ication cycle time from a few days (extensive metrology

followed by mask shop cleaning) to several hours (in-fab CDU monitoring and correc-tion) with minimal production impact.

Scanner Dose ModulationCurrently, CDU variations are corrected using test wafers and feedback control. This can be a lengthy process due to the limited throughput of the metrology tools and the need to expose and develop the test wafers before metrology. In addition, the lower sampling rates commonly in use may not ref lect true CDU distribution and may limit potential improvements.[5]

To protect against yield loss when mask error contributions increase significantly, the combined interfield and intrafield fin-gerprint modulations should be monitored to optimize corrections in slit and scan directions. In order to take advantage of their correction potential, the latest gen-eration APC systems accept a direct feed of a high-definition mask-based fingerprint as well as wafer interfield fingerprint feed-back. This not only protects against yield loss but further enhances yield compared with traditional feedback mechanisms.

When the process window cannot be corrected any further, mask cleaning is required. Cleaning the mask only when needed allows for longer cleaning intervals

and extends mask lifetime. An example of mask degradation can be seen in Figure 6. The notice-able CDU fingerprint change is a consequence of approximately 1,500 wafer exposures, or 16kJ dose accumulation.

This fingerprint drift can be cor-rected by the APC system to bring it back within the control limits. How well the correction is made depends on the quality of the CDU map fed to the scanner.

A CDU correct ion compar i-son made between traditional CD-SEM-based feedback and


Figure 5. Dynamic CDU monitoring tracks mask degradation to prevent yield excursions.[7]

E0 E0 + 16 kJ from scanner

Mask with pellicle

Exposure:Photo-induced effects

change mask transmissionduring wafer production

Pellicle:Changes in pellicle

transmission cause non-uniformchanges in mask CDU

Clean:Cleaning causes

non-uniform changesin mask CDU

Mask without pellicle

Pre-clean Post-clean

SPC within control limits SPC out of control limits

18 x 104

161412108642052 54

Mea

sure

men

t Num

ber

nm56 58 60 62 64 66 68 70

20 x 104

18161412108642052 54

Mea

sure

men

t Num

ber

nm56 58 60 62 64 66 68 70

Figure 6. Cumulative exposures of more than 1,500 wafers degraded this mask until it was beyond the established SPC control limits (red box).


IntenCD-based feed-forward is shown in Figure 7. The high-def inition IntenCD map correction using a feed-forward approach improved the intra-f ield CDU by 30% versus the traditional approach.

ConclusionThe productivity and yield-related examples outlined in this paper demonstrate the various applications of the IntenCD high-definition mask-based wafer CDU mapping. IntenCD

technology improved wafer CDU control over traditional metrology methods, saving scanner time by eliminating the need for test wafers and significantly reducing the overall wafer metrology burden. The CDU finger-print, categorized as static CDU and dynamic CDU, can now be accurately captured and monitored. Applying both CDU elements in the fab extends cleaning intervals and mask lifetime, increases mask availability and raises overall lithography cell efficiency. ■

References[1] ITRS 2007/08 Lithography updates.

[2] Michael Ben-Yishai et al., “An IntenCD map of a reticle as a feed-forward input to DoseMapper,” Proc. 7028-122, PMJ, 2008.

[3] Amir Sagiv et al., “IntenCD: Mask critical dimension variation mapping,” Proc. 7028-49, PMJ, 2008.

[4] Bart Rijpers et al, “Impact of sampling on uncer-tainty: Semiconductor dimensional metrology appli-cations,” Proc. 6922-31, SPIE, 2008.

[5] Heebom Kim et al., “IntenCD: an application for CD uniformity mapping of photomask and process con-trol at maskshops,” Proc.7028-55, PMJ, 2008.

[6] Oleg Kishkovich et al.,“Contrarian approach to and ultimate solution for 193nm reticle haze,” Proc. 6518-144, SPIE, 2007.

[7] Jin Ho Ryu et al., “Report on latent contamination factors inducing lithographic variation,” Proc. 7122-40, PMJ, 2008.

[8] Ilan Englard et al., “Aerial imaging mask inspection system for advanced technology nodes,” Semicon Japan, 2008.


Shmoolik Mangan is an R&D and technology manager with the Mask Inspection division in Applied’s Process Diagnostics and Control (PDC) group. He received his Ph.D. from the Weizmann Institute of Science and his M.Sc. from the Technion Institute of Technology, Israel.

Yaron Cohen is an IntenCD and metrology proj-ect manager with Applied’s Mask Inspection division. He received his second degree in physics from Bar-Ilan University, Israel.

Yair Elblinger is the main developer on the IntenCD project with Applied’s Mask Inspection division. He received his second degree in mathematics from the Israeli Technion.

Shay Attal is an application development engineer responsible for IntenCD product development with Applied’s Mask Inspection division. He received his B.Sc. degrees in chemical engineering and chemistry, from the nanotechnology program of the BGU University, Beer Sheeva.

Neil Berns is a global product manager with Applied’s Mask Inspection division. He holds an engineering degree in electronics from the Jerusalem College of Technology.

Lior Shoval is an algorithm group manager with Applied’s Mask Inspection division. He received his B.Sc. in electronic engineering from Tel Aviv University, Israel.

Michael Ben-Yishai is an image processing group manager with Applied’s Mask Inspection division. He received his M.Sc. in electrical engi-neering from Tel Aviv University, Israel.

Ilan Englard is a product marketing manager for Applied’s Mask Inspection division. He holds an electrical engineering degree from the Tel Aviv Institute of Technology, Israel.

Authors


© SPIE. Republished with permission from Proceedings Vol.7272, Metrology, Inspection, and Process Control for Microlithography XXIII.

Applied Aera2™ Mask Inspection

Inspection System Used in Study

• Aerial imaging-based inspection that can be used in a wafer production environment

• Features IntenCD technology that maps wafer CDU

• Predicts defect printability

CDU 3σ = 1.6nm

CDU 3σ = 1.1nm

Figure 7. Compared to (left) using traditional wafer CD measurements, (right) scanner cor-rection with IntenCD showed 30% improvement in intrafield on-wafer CDU.


New Low k Barrier Film Reduces RC Delay

Low k

New materials will be needed to reduce RC delay in sub-45nm interconnects. One way to achieve this is to lower the dielectric constant of the Cu barrier film below 4.0 by additional carbon dop-ing while maintaining comparable barrier prop-erties and etch selectivity to the current 45nm dielectric barrier material. However, advanced interface management is required to achieve good breakdown and electromigration (EM) perfor-mance. An enhanced nitride interface (ENI) concept was developed to maximize interfacial mechanical and electrical strength without nega-tively affecting Cu electrical performance.

Keywords: BLOk II, Cu Barrier Dielectric, Enhanced Nitride Interface, TDDB, EM, k-value Reduction, Film Interface Control

Since device speed is significantly impacted by the capacitance of the insulating materi-als between Cu interconnect layers, finding lower dielectric constant films is essential for sub-45nm scaling. A porous low k (≈2.5) film has been successfully integrated into the device structure, but additional reduction in the bulk dielectric is no longer viable because it degrades etch selectivity and Cu diffusion.[1]

A new initiation scheme for forming a con-trollable interface layer has been developed that optimizes the interface mechanical and electrical properties without any negative impact on Cu electrical properties.

The baseline barrier low k for 65nm pro-duction is an amorphous SiCN dielectric

material with k≈5.1. By modifying the deposition base chemistry to add a carbon precursor, we can reduce the dielectric constant of the f ilm from 5.1 to 4.0 and lower overall capacitance by more than 5%. In addition, a C-rich f ilm enhances polymer formation during the etch pro-cess to maintain etch selectivity. This is an important benefit because the barrier low k layer is used as a stop layer during damascene etch. No degradation in EM or other dielectric properties from this new chemistry was observed.[2]

Carbon-rich low k barrier films have been qualified for 45nm manufacturing. When porous bulk low k dielectrics are used, the barrier becomes critical to maintaining electrical properties and avoiding inter-connect reliability issues such as time-dependent dielectric breakdown (TDDB) and EM.[3,4]

Reducing interface impurities has been identified as the key for good adhesion and high breakdown performance. In situ CuO removal with an NH3 plasma has been used since the 90nm device node, but it is proven to be insufficient for devices with smaller features. Minimizing the C content is another way to improve the electrical per-formance. Various interface enhancement layers, such as CuSiN or CoWP, have been evaluated but they are very sensitive to Cu surface conditions and difficult to implement in a manufacturing environment.

Experiments and ResultsEarly attempts to decrease the barrier film dielectric constants were carried out by adjusting the plasma density during depo-sition without changing the corresponding process chemistry. Figure 1 shows that the k value is reduced at the expense of f ilm density. As a result, the film becomes more

1.7

1.5

1.6

1.43.5 3.7 3.9 4.1 4.3 4.5

Dielectric Constant

Film

Den

sity

(g/c

c)

Additional C-dopingPlasma Density Reduction

1.7

1.5

1.6

1.4300 400 500 600 700 800

Blanket Etch Rate (Å/min)

Film

Den

sity

(g/c

c)

Additional C-dopingPlasma Density Reduction

Figure 1. Effect of plasma density reduction and C-doping on (left) Cu barrier film density and dielectric constant, and (right) Cu barrier film density and blanket etch rate. Carbon doping can reduce dielectric constant and etch rate without degrading film density.


porous and the dry etch rate of the blanket film increases, potentially leading to com-plete removal of the barrier layer during via and trench etch, thus exposing the Cu.

In contrast, our approach of adjusting the process chemistry by additional C-doping reduces the k value and the dry etch rate while maintaining the integrity of barrier film density. This is very desirable since the barrier thickness does not have to be increased when the k value reduces below 4.0.

Oxidation ResistanceTo successfully integrate a carbon-rich barrier f ilm, f ilm stability and oxidation resistance are required to protect the Cu surface during subsequent integration steps. While the additional carbon may render the low k film more hydrophobic, it may also make the film more susceptible to oxygen attack. A thermodynamic simulation was conducted to understand various C bond-ing types and their effect on oxidation resis-tance. Two types of oxidation paths were explored, including an oxygen insertion mechanism and a peroxide mechanism:

O2 + A-B → A-O-B + O (oxygen insertion) O-O | | O2 + A-B → A-B →A-O + B-O (peroxide formation)

where A and B are exemplary cases.

Figure 2 shows ab initio modeling of the thermal barr ier ΔE for different bonding structures in SiCN f ilms.[2] While most of the conventional bonds, such as Si-N, N-H, Si-C, are thermally stable, C=C bonds present in the f ilm can easily react with water or oxygen causing the film to be more susceptible to oxidation. In this case, the C=C double bonds unfold and bridge with the O-O bonds through the peroxide mechanism. Si-H content is another con-cern. The process chemistry and deposition method must be optimized to minimize these bonds.

To verify the optimized process obtained, an aggressive test was carried out by anneal-ing the barrier low k f ilm capped with electroplated Cu in an ambient condition

of 310°C for 24 hours. The O, C and Cu profiles were obtained using XPS analysis. To preserve the surface information, a SiN capping layer was added prior to XPS analy-sis (Figure 3).

A very low oxygen level was detected, espe-cially at the barrier low k/Cu interface. The f ilm also contained high levels of carbon due to the process chemistry, as expected. A moisture cooker test was conducted using an 85/85 test method (85% moisture at 85°C for 17 hours) to determine the f ilm stability. No distinguishable increase in the k value was observed. The 85/85 test was also used to verify the film hermeticity, a measure of moisture penetration through the

■ Low k Barrier Film

Film Type65nm SiCNBaseline

BLOk II

Dielectric ConstantLeakage at 1MV/cm (A/m2)

5.1 ± 0.12E-10

3.8 ± 0.16E-11

Breakdown (MV/cm) > 4.5 > 4.5

Compressive Film Stress (MPa) 250 ± 50 200 ± 50

Hardness (GPa) 10.9 ± 0.5 5.3 ± 0.5

Young’s Modulus (GPa) 82 ± 3 38 ± 3

Cu Diffusion Length (nm)Cu Oxidation Test (Ambient Anneal)

< 152% -O at Cu/barrier interface

< 152% -O at Cu/barrier interface

Table 1. SiCN film properties.

Atom

ic C

once

ntra

tion

(%)

100 200 300 400 500 600 700 800 9000 1000

Sputter Depth (Å)

250ÅSiN

500ÅBLOk II

O Profile

Cu

100

90

80

70

60

50

40

30

20

10

0

O1sC1s

Si2pF1s

N1sCu2p3

Figure 3. XPS profile after oxidation test shows low O content at the Cu/barrier interface, comparable to the 65nm SiCN baseline.

4.0

3.0

2.0

1.0

0

-1.0

-2.0

-3.0C=C Si-H

(NH2)Si-H(CH3)

Si-C C-H C-C Si-N N-H

Oxidation Favorable –Film Unstable

Oxidation Not Favorable –Film is Stable

∆E (e

V)

Figure 2. Thermodynamic calculations of bond oxidation resistance. 0.5eV corresponds to approximately 250°C, at which point significant film oxidation may occur.


film. Several key film properties, compar-ing the lower k barrier film with that of the 65nm SiCN baseline, are listed in Table 1.

Mechanically, both SiCN films have much higher hardness and Young’s modulus values than those of typical IMD bulk SiCO materi-als (1.5–2.0GPa and 15GPa respectively), and therefore can strengthen the overall dielectric stacks. In order to compensate for the tensile stress associated with the low k IMD films, the barrier dielectric can be tuned to achieve compressive stress. Except for the difference in dielectric constants, these two films pos-sess very similar electrical and Cu barrier properties.

Interface ManagementThe Cu surface condition prior to barrier deposition is an important factor for good

reliability. Since Cu tends to oxidize when exposed to air, it is a common practice to add an NH3 plasma treatment step to remove the CuO with the following reaction:

CuO s NH Cu s H O NORF( ) ( )+ → + +3 2 2

In addition, this NH3 plasma can also clean surface organic residues from the preceding CMP process. Our experiments have shown a clear correlation between EM activation energy and pre-treatment conditions, which impact the SiCN adhesion to Cu (Figure 4). The optimization of Cu surface pre-treatment is obtained through plasma density adjust-ment and dilution of N2. A high NH3/N2

ratio and high plasma density improve Cu surface cleaning efficiency.

Treatment time is another factor in low k damage since most IMD bulk low k materials are composed of C-doped oxides. Hydrogen ions generated from the CuO removal step

can remove C from the IMD and increase its k value. This becomes more critical as the industry adopts porous SiCO film for sub-45nm node. Therefore, an additional interface enhancement approach is required to mitigate the negative impact.

Through XPS surface analysis, we found that the surface condition, especially the C and O content, has a large impact on adhesion strength. Figure 5 shows that condition III exhibits the highest adhesion strength, where-as condition II and I are progressively worse, indicating that lower C and O levels improve the adhesion strength. By inspecting the bar-rier low k (BLOk II) XPS profile in Figure 3, it is clear that the C presence at the interface from the deposition chemistry needs to be minimized. Adding a SiN interface layer in between, termed enhanced nitride interface (ENI), reduces C/O impurities at the inter-face significantly (Figure 6).

Reliability and Electrical PerformanceIn addition to adhesion improvement, ENI also improves leakage and breakdown per-formance. ENI has been shown to improve step coverage and help form a passivation layer to compensate for the surface topog-raphy, especially at the corner area where the Cu and metal barrier (Ta/TaN), IMD and SiCN materials converge (Figure 6).

The test vehicle for this study had a metal 1 CD pitch of 0.22μm, metal 2 pitch of 0.25μm and via of 0.125μm. Lithography


1.2

1.0

0.8

0.6

0.50 0.2 0.4 0.6 0.8 1.0 1.2

Normalized Interface Adhesion Energy (J/m2)

Activ

atio

n En

ergy

(eV)

800 600 400 200 1001,000

Binding Energy (eV)

Cond. I

Cond. II

F

C

N

N

Si

Si

Si

SiC

O

F

Cond. III

Figure 5. (Left) Cu surface analysis after NH3 pre-treatment and (right) its relationship with adhesion strength to SiCN. Cu surface condition dominates the adhesion strength.

1.2

1

0.8

0.6

0.4

0.2

0Cond. I Cond. II Cond. III

Norm

aliz

ed C

u/ba

rrie

r Adh

esio

n

Wafer Load on to Heater

CuO Removal

Enhanced Nitride Interface (30Å)

Bulk SiCN Deposition (320Å)

SiCN k≈3.8

Cu

ENI

ILD

20nm

Figure 6. (Left) BLOk II deposition sequence. (Right) The red circle indicates the weak corner where 4 different materials (SiCO, Ta/TaN, Cu and dielectric barrier) meet. The ENI covers the topographical surface prior to SiCN deposition to improve reliability.

Figure 4. Cu EM activation energy perfor-mance as a function of Cu/barrier interface adhesion strength. In situ CuO removal improves adhesion between barrier and copper which is key for EM reliability.


was performed using 193nm resist. The inter-layer and the intra-layer dielectric was a SiCO f ilm with k≈3.0. Line-to-line I-V breakdown and TDDB tests were conducted at 105°C. Electromigration tests were carried out on packaged samples at 300ºC and a current density of 1.5mA/cm2 using single via structures. The failure criterion was a 10% increase in resistance. Both TDDB and EM results exhibited sig-nificant improvements with the SiN inter-face layer (Figure 7).

Through the ENI optimization, greater than 100% EM improvement has been demonstrated using a 2-level metal dama-scene structure. In addition, we have also verif ied that ENI has no impact on Cu line resistivity since ENI is deposited onto the clean, pre-treated Cu surface.

ConclusionsThe new barrier low k f ilm (BLOk II) is an improved Cu barrier for sub-45nm devices, with a reduced k va lue and

no degradation of barr ier proper-ties when compared with the cur-rent 65nm SiCN baseline. The f ilm structure was optimized to mini-mize unstable bonding and achieve good oxidation resistance. An ENI process was adopted to improve the interface adhesion strength and leak-age performance. Improvements in TDDB and EM performance were demonstrated through 2-level metal integration tests. ■

References[1] S.G. Lee et al., Jpn. J. Appl. Phys., 40, 2663, 2001.

[2] H. Xu et al., Advanced Metallization Conference

Proceedings, p. 512, San Diego, CA, 2007.

[3] M. W. Lane et al., J. App. Phys., 93, 1417, 2003.

[4] A.S. Lee et al., Mat. Res. Soc. Symp. Proc., 812,

F5.10.1, 2004.


Li-Qun Xia is the director of technology with Applied’s Blanket Dielectric Films division where he is focusing on dielectric materi-als and process development. He holds a Ph.D. in chemical engineering from Cornell University.

Vladimir Zubkov is a member of technical staff with Applied’s Silicon Systems group, exploring PECVD and CVD potential for new materials fabrication. He received his Ph.D. in polymer physics and his doctorate in sci-ence in polymer chemistry from the Institute of Macromoleculars Compounds, Academy of Science, Leningrad, Russia.

Weifeng Ye is a process engineer with Applied’s Blanket Dielectric Films division, focusing on dielectric systems and modules. He received his Ph.D. from the University of Michigan, Ann Arbor.

Maggie Shek is a process technology manager

with Applied’s Thin Films group where she is focusing on low k dielectric barrier and new film development. She holds a B.S. degree in chemical engineering from UC Berkeley.

Zhenjiang (David) Cui is a member of the tech-nical staff with Applied’s Maydan Technology Center (MTC) BEOL integration group. He per-forms back-end-of-film integration, character-ization and electrical analysis. He has a Ph.D. from the University of Illinois.

Mehul Naik is a distinguished member of the technical staff at Applied’s MTC. He man-ages BEOL integration focusing on Cu-low k integration, Cu for memory devices and advanced contacts. He earned a Ph.D. in chemi-cal engineering from Rensselaer Polytechnic Institute.

Authors


Reproduced with permission from ECS—the Electrochemical Society from ECS Transactions, 18 (1) pp. 593–599, 2009.

Applied Producer® BLOk® II

Process System Used In Study

• 20% lower capacitance for

improved interconnect perfor-

mance

• Excellent Cu diffusion barrier

properties

• Enables multi-level integration

with tensile bulk low k materials

1016

1014

1012

1010

108

106

104

102

100

0 1 2 3 4 5 6

E-field (MV/cm)

SiCN w/ ENI

SiCNT 63 T

bd (s

)

99%

90%

50%

10%

1%0.1%

0.1 1

SiCN Baseline

ENI + SiCN

10 100 1000Pr

obab

ility

Time (hrs)

Figure 7. Electrical tests for SiCN barrier: (left) TDDB using single level Cu test structure, and (right) EM improvement using ENI on 2-level Cu damascene structure. ENI improves TDDB due to minimized interface impurities and doubles EM resistance.

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