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The challenges of double patterning
Harry J. Levinson
July 16, 2008
Sokudo Semicon West2 16 July 2008
“Double, double, toil and trouble...”*
*MacBeth, Act 4, Scene 1
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g-line → i-line → KrF → ArF
436 nm → 365 nm → 248 nm → 193 nm
Mercury arc lamps Excimer lasers
→ EUV
→ 13.5 nm
Why are we doing this?
“Who did strike out the light?”MacBeth, Act 3, scene 3
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= +
Pitches are limited by physics – minimum linewidths are not!
Why are we doing this?
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The challenges ahead
• With single patterning, parameters scale ~0.7× node-to-node.
• Overlay
• CD control
• LER
• Usually, we have an increase in resolution to assist with the transition.
• Wavelength.
• NA.
• With double patterning.
• Process control must scale faster than 0.7×.
• Exposing (and perhaps etching) twice per layer doubles cost.
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Overlay
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Overlay requirements: metal layer
Exposure 1 Exposure 2 Exposure 1
• To first order, lines will have the same CD variability as single exposures.
• For the space:
L1 L2S
22
222
21
2
44
22
OLL
OLLL
S
OLLL
S
σσ
σσσσ
+=
++=
Δ+Δ
+Δ
=Δ
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22
2 OLL
S σσσ +=
“But yet I'll make assurance double sure,And take a bond of fate...”*
*MacBeth, Act 4, Scene 1
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• In ITRS for 2012:
• ITRS ½ pitch is 36 nm, so σS = 5.4 nm @ 15% CD control requirement.
• Overlay requirement is 7.1 nm for single exposures.
22
2 OLL
S σσσ +=
“But yet I'll make assurance double sure,And take a bond of fate...”*
*MacBeth, Act 4, Scene 1
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22
2 OLL
S σσσ +=
• In ITRS for 2012:
• ITRS ½ pitch is 36 nm, so σS = 5.4 nm @ 15% CD control requirement.
• Overlay requirement is 7.1 nm for single exposures.
“But yet I'll make assurance double sure,And take a bond of fate...”*
3
3.5
4
4.5
5
5.5
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Linewidth control (nm)
Overlay (
nm
)
*MacBeth, Act 4, Scene 1
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laserprojection optics
wafer stage
reticle stage
Overlay control
1 mK temperature change over 1 meter = 1 nm error
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Spacer processes
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Frequency doubling with spacers
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Resolution
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Dark field versus bright field patterning
Bright field
Dark field
4 × 45 nm = 180 nm < 193 nm
Positive resist
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• High resolution negative resists will relieve the resolution burden.
• Challenges:
• Immersion compatibility.
• Aqueous developers.
Resist types
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Cost
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• The basic problem with double patterning is cost.
• It doubles the number of critical layers.
• 10 critical layers → 20 critical layers.
Cost issue
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One FilmOne Etch
CEL‘Memoryless Resist’
‘New Concepts’
Increasing Process Complexity
Increasing Resist Materials Complexity
Two FilmsOne Etch
Resist Stabilization-Pattern Freezing
-Dual Solvents
Two FilmsTwo Etches
Conventional Resist Process
‘Double Exposure’ ‘Double Imaging’ ‘Double Patterning’
Difficulties
Figure courtesy of Dr. Tom Wallow
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“Eye of newt, and toe of frog, Wool of bat, and tongue of dog, Adder's fork, and blind-worm's sting, Lizard's leg, and owlet's wing,—”*
Can appropriate materials be devised?
*MacBeth, Act 4, Scene 1
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One FilmOne Etch
CEL‘Memoryless Resist’
‘New Concepts’
Increasing Process Complexity
Increasing Resist Materials Complexity
Two FilmsOne Etch
Resist Stabilization-Pattern Freezing
-Dual Solvents
Two FilmsTwo Etches
Conventional Resist Process
‘Double Exposure’ ‘Double Imaging’ ‘Double Patterning’
Difficulties
Figure courtesy of Dr. Tom Wallow
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• What if we can eliminate an etch step?
Cost reduction
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Properties
• Properties of films.
• Solvent of second resist does not dissolve underlayer resist.
• Second exposure does not cause underlayer resist to dissolve in developer.
• High resolution, low LER, immersion compatibility,...
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Early AMD resist-on-resist work
Experimental conditions:
KTI 747 negative resist, 0.5 μm; exposure tool: Perkin Elmer 341
Kodak 820 positive resist, 1.5 μm; exposure tool: GCA 6300, g-line, 0.3 NA
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More recent AMD resist-on-resist work
Radiation hardened Chemically treated
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Summary
• There are many challenges!
• There are many opportunities for creative solutions!
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Trademark Attribution
AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners.
©2006 Advanced Micro Devices, Inc. All rights reserved.