Interactions of Double Patterning Technology with wafer ... Interactions of Double Patterning Technology

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1 2006 Synopsys, Inc. (Name)

Interactions of Double Patterning Technology with wafer processing,

OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins

Synopsys

Vincent Wiaux, Staf Verhaegen

IMEC Leuven Belgium

Predictable Success

IMEC, Leuven, Belgium

If it moves, chop it in half, then simulate it

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins

Synopsys

Vincent Wiaux, Staf Verhaegen

IMEC, Leuven, Belgium

Predictable Success

IMEC, Leuven, Belgium

2 2006 Synopsys, Inc. (Name)

Double Patterning additive1st trench imaging

Etch stop.

LowKBARCHM

Resist

Hard Mask etch

2nd trench imaging

Hard Mask etchResist/BARC strip

Hard Mask etch

2006 Synopsys, Inc. (3)

Predictable Success

transfer to dielectric

Hard Mask etchResist/BARC strip

See V. Wiaux 6924-08, next session

Outline

DPT Lithography & Process Window DPT Mask SynthesisDPT Mask Synthesis DPT Physical Design Conclusions

2006 Synopsys, Inc. (4)

Predictable Success

3 2006 Synopsys, Inc. (Name)

Lithography considerations @22nm Need 30-35nm etched CD ~70nm min final pitch

Need highly controlled 140nm pitch single exposure lithoPW budget: 5% EL, 100nm DOF

RET?No space for retargeting or AFsNeed litho sizing + etch downsize

Patterning strategy:Poly: ~45nm litho CD (~32nm gen)

2006 Synopsys, Inc. (5)

Predictable Success

Cont: ~55nm litho CD (~32nm gen)M1: new resist or ~60nm litho CD

All layers require 15nm+ etch shrinkStandard for Poly, new for Cont & M1

Min allowed space vs. # DPT conflicts

2006 Synopsys, Inc. (6)

Predictable Success

Upsizing reduces single exposure litho space.Creates more DPT interactions & conflicts.

0nm upsize 5nm upsize 10nm upsize 15nm upsize

4 2006 Synopsys, Inc. (Name)

DPT litho/etch topographyY

[um

]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

1: n16_01_PolySi_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

2: n16_02_HM_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

3: n16_03_ARC_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

4: n16_04_resist1.tdr 0

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

5: n16_06_trim1.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

6: n16_07_ARC1.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

7: n16_08_HM.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

8: n16_09_strip.tdr 0

m]

-0.4

-0.3

9: n16_10_lpcvd.tdr 0

m]

-0.4

-0.3

10: n16_11_reflow.tdr 0

m]

-0.4

-0.3

11: n16_12_resist2.tdr 0

m]

-0.4

-0.3

12: n16_13_trim2.tdr 0

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

2006 Synopsys, Inc. (7)

Predictable Success

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

13: n16_14_ARC2.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

14: n16_15_Poly.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

15: n16_16.tdr 0

Planar vs. Non-planar results

2006 Synopsys, Inc. (8)

Predictable Success

Litho2 no Etch1 patternCD bottom 55nm

Litho2 over Etch1 patternCD bottom 57nm+

5 2006 Synopsys, Inc. (Name)

DPT Mask Synthesis

2006 Synopsys, Inc. (9)

Predictable Success

DPT Decomposition/OPC/Verify Functions:

decomposition (split & color), RET, OPC and error identification.

High yieldg ySplit creates OPC/RET friendly layoutsOPC creates yield friendly wafer patterns

through overlay, focus, & dose variationsVery high accuracy/predictive OPC modelsSymmetry, density uniformity

Fast turnaround

2006 Synopsys, Inc. (10)

Predictable Success

Fast turnaroundLimits complexity/iterations in decomposition algorithms

Must successfully convert all DPT compliant designs

6 2006 Synopsys, Inc. (Name)

Logic contact split exampleGreen lines show

network of features to be decomposed

Red lines show coloring violations where redesign is necessary.

1D arrays, 2by2

2006 Synopsys, Inc. (11)

Predictable Success

1D arrays, 2by2 arrays, on grid contact are DPT friendly.

Smart Coloring for Violations

Line-end control critical

Overlap quality

Decomposition must ensure

2006 Synopsys, Inc. (12)

Predictable Success

Decomposition must ensure OPC can meet very tight accuracy tolerances- line-end control now critical

7 2006 Synopsys, Inc. (Name)

Yield & process window issues

Pinch, sharp corner, overlay sensitive

2006 Synopsys, Inc. (13)

Predictable Success

Std. round corner current density22nm node Cu feature, max J ~1.2

2006 Synopsys, Inc. (14)

Predictable Success

8 2006 Synopsys, Inc. (Name)

DPT square corner current density22nm node Cu feature,

max J ~2.3

J is ~2X higher withJ is 2X higher with sharp corners.

Blacks electromigration Eq.: Mean time to failure (MTTF) can decrease by 3-4X!

2006 Synopsys, Inc. (15)

Predictable Success

y

Local stress at sharp corner could further accelerate failure.

DRC

Decomposition algorithm differencesBasic approach More complex algorithm

DRC violation

Small poorly printed polygon

2006 Synopsys, Inc. (16)

Predictable Success

Asymmetric with printing issuesHigh # of cuts, risky overlaps

Symmetric, fewer cuts, easier to OPC -> better yield

See C. Cork 6925-62, thurs. PM

9 2006 Synopsys, Inc. (Name)

Need for model based decomposition- Sometimes need model to predict and avoid errors

Looks fine after split but h S lit

MRC limits OPC at LE

has error on wafer

Looks

Split Option 1

DPT-aware OPC

2006 Synopsys, Inc. (17)

Predictable Success

bad after split but is good on wafer

Split Option 2

DPT physical design flow

2006 Synopsys, Inc. (18)

Predictable Success

10 2006 Synopsys, Inc. (Name)

Double Patterning in Design FlowDesign Task Goals

Std cell creation & characterization

Minimize cell widthMaximize timing/leakage performanceg g pNo design rule or DPT violations

Custom layout Minimize areaNo design rule or DPT violations

Place & route Maximize routabilityNo design rule or DPT violations

2006 Synopsys, Inc. (19)

Predictable Success

No design rule or DPT violations

Tapeout signoff (DRC) No design rule or DPT violations in final design

DPT standard cell generation flow

GDS Layout

Std ll t lStd cell tool GDS Import

TuneLayout

Std cell Setup

LayoutRules

ErrorReports

FixRule 1

FixRule 2

FixRule N

DPTDecomp

Tool

External analysis

2006 Synopsys, Inc. (20)

Predictable Success

Corrected Layout

DesignRules

11 2006 Synopsys, Inc. (Name)

DPT Correction Flow Example: aoi22x1 with 2 METAL1 conflicts

Source GDS

GDS analyzed

for

2 Conflicts on METAL1 found

Pass 1Conflictscorrected

d ll

Corrected GDS1 New Conflict Corrected GDS

Pass 2Conflictscorrected

conflicts and cell optimizedand cell

optimized

2006 Synopsys, Inc. (21)

Predictable Success

POLY & METAL1DPT AnalysisResults

DPT standard cell library migration Took a traditional standard cell library and converted to a

DPT clean libraryMade reasonable min-space assumptions for DPT

70 unique standard cells Compared cell area before and after conversion Results: Area shrunk ~1% after conversion (!?) 2 possible reasons

2006 Synopsys, Inc. (22)

Pr

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