Sambuddha Bhattacharya

Subramanian Rajagopalan

Shabbir H. Batterywala

Fixing Double Patterning Violations With Look-Ahead

ASD-DAC’14

Outline

Introduction DPT Fixing As Legalization Co-Resolution of DPT and DRC Constraint Feasibility Check Preventing New DPT Violations Experimental Results Conclusion

Introduction

Lithography at 20nm and below necessitate double patterning (DP) or splitting of a mask into two sub-mask patterns

A graph is free of DPT conflicts if it is bi-colorable

The main idea of this paper is that model the non-DPT edges in the input layout, address the issue of new DPT conflicts

Legalization based approach to fix DPT violations

Key contributions A look-ahead method that predicts new DPT

edges A tightly coupled interaction between a

constraint feasibility checker and DPT conflict verifier

Fix existing violations without introducing new ones

DPT Fixing As Legalization

A legalization engine reads in an input layout and fractures its mask layer geometry into rectangles

All applicable design rules are modeled as linear difference constraints

Generally, the constraint set obtained from a realistic layout is often infeasible due to conflicts between complex rules and design intents

An infeasibility in the corresponding linear program can be detected as positive cycle in the constraint graph(Gc)

Modeling DPT Constraints

DPT conflicts express themselves as odd cycles of spacing between shapes

Note that the DPT constraints are naturally disjunctive

If constraint set is infeasible, then replace the representative constraint of a disjunctive set with an alternative and repeat the feasibility check

Methodology Overview

Co-Resolution of DPT and DRC

There is a strong relationship between GD and GC

GC should be made feasible and GD should be freed of odd cycles

Detecting DPT Conflicts in BCC

The total number of odd cycles in a graph can be exponential

We identify the odd-cycles in a cycle basis from GD

Constraint Feasibility Check

Each edge in the constraint graph GC models corresponding constraints of the form xi − xj ≥ wij

Generally, a pair of rectangles can have multiple constraints between them

Inconsistencies in the constraints express themselves as positively weighted cycles in GC

Positive cycles are detected by invoking a single source longest path algorithm

Assume that the DPT constraint were absent

If wDRC > then the edge weight gets reduced to

Resolving positive cycles in this way have two properties If a constraint is not satisfiable, the input layout

value is retained The input layout positions represent a feasible

solution

Once the infeasibilities are resolved in GC the graph is augmented with the DPT constraints

If an edge was already relaxed to current layout value, the corresponding DPT difference constraint is deactivated and swapped with the next constraint

If none of the disjunctions for a DPT conflict are satisfiable, then the corresponding DPT conflict can not be resolved

Preventing New DPT Violations

As DPT conflict cycles are broken by increasing spacing, this can result in reduction of spacing in the neighborhood

Simulate the behavior of the LP solver to predict new DPT violations

Layout-aware Bellman-Ford Algorithm (LABF)

Forward LABF generates the upper bound Reverse LABF generates the lower bound The ranges generated by LABF includes all

points in the solution space where minimum layout perturbation

Experimental Results

Using designs in 40nm and 20nm technology with appropriate representative DPT rules and DRC rules

2.8GHz, 4 core linux machine with 8 GB RAM

Conclusion

Presented a DPT fixing approach based on wire spreading

The framework of legalization ensures that DRC violations are modeled and fixed simultaneously

Feasible constraint selection, new DPT edge prediction and DPT conflict cycle verification