*Electrical Behaviour of CMOS & BiCMOS Family Logic DevicesFaculty: Anoop Mathew, HoD ECECourse: ES 10 105 A /VL 11 105 A - Electronic System design

IntroductionCMOS devices are best known for low power consumption. This discussion addresses:- types of power consumption in a CMOS logic circuit.- focusing on calculation of power-dissipation capacitance - the determination of total power consumption in a CMOS device.

Power-Consumption ComponentsPower calculations determine power-supply sizing, current requirements, cooling/heat-sink requirements, and criteria for device selection. Two components determine the power consumption in a CMOS circuit:1. Static power consumption2. Dynamic power consumption

Static Power Consumption

CMOS devices have very low static power consumption.When switching at a high frequency, dynamic power consumption can contribute significantly to overall power consumption. There is a small amount of static power consumption due to reverse-bias leakage between diffused regions and the substrate - results in parasitic diodes.

Static power consumption, PS = (leakage current) x (supply voltage)

Dynamic Power Consumption

Dynamic Power Consumption = Transient power consumption (PT)+ Capacitive-load power consumption (PL).

Transient Power ConsumptionTransient power consumption is due to the current that flows only when the transistors of the devices are switching from one logic state to another.Currents are - current required to charge the internal nodes (switching current) and - the through current (current that flows from VCC to GND

Transient power consumptionTransient power consumption = PT = Cpd_x Vcc 2 x fI x NSWPT = transient power consumptionVCC = supply voltagefI = input signal frequencyNSW = number of bits switchingCpd = dynamic power-dissipation capacitance

Capacitive-Load Power Consumption

PL = CL x V2 CC x fO x NSWWhere:PL = capacitive-load power consumptionVCC = supply voltagefO = output signal frequencyCL = external (load) capacitanceNSW = total number of outputs switchingIn the case of different loads and different output frequencies at all outputs, capacitive-load power consumption PL = (CLn x fOn) x Vcc2Where: fOn = all different output frequencies at each output (Hz)VCC = supply voltage (V)CLn = all different load capacitances at each output, numbered 1 through n.

Power-Dissipation Capacitance (Cpd) in CMOS CircuitsCpd is an important parameter in determining dynamic power consumption in CMOS circuits. It includes both internal parasitic capacitance and through currents present.

Comparison of Supply Current versus Frequency

Cpd and dynamic power consumption can be measured through supply-current-versus-frequency plots. Supply current is critical because it indicates the amount of power consumed by the device. Less power consumed means less heat is generated and the problems of dissipating the heat are reduced.

Power EconomyThe dc power consumption can be reduced to leakage by using only CMOS logic gates, as opposed to bipolar and BiCMOS. The leakage current is proportional to the area of diffusion, so the use of minimum-size devices is an advantage. Dynamic power consumption can be limited by reducing supply voltage, switched capacitance, and frequency at which the logic is clocked.

**Thank YouQueries ???Mail to: anoopmathew@ieee.org