Analog CMOS/CMOS/MemristorMemristor Hybrid Circuitsasdn.net/ngc2011/presentations/strukov.pdf · Analog CMOS/CMOS/MemristorMemristor Hybrid Circuits Dmitri Strukov UC Santa Barbara

Analog CMOS/Analog CMOS/MemristorMemristorHybrid CircuitsHybrid Circuits

Dmitri Strukov

UC Santa Barbara

Nano and Giga Challengesin Electronics, Photonics and Renewable Energy

Moscow, Russia

September 2011

Presentation OutlinePresentation Outline

UCSB Presentation OutlinePresentation Outline

• Intro: Analog computation

• Memristive devices

• Hybrid circuits• Hybrid circuits

• Analog hybrids

• Digital hybrids

• Summary

2D. B. Strukov, NGCMoscow, September 2011

Widrow’sWidrow’s MemistorMemistor and and AdaLiNeAdaLiNeUCSB

AdaLiNe concept … … and hardware implementation

TION

TRODUCT

INT

Bernard MarcianBernardWidrow

MarcianHoff


B. Widrow and M.E. Hoff, Jr., IRE WESCON Convention Record, 4:96 1960

The Last Computing The Last Computing Frontier (I) Frontier (I) UCSB

1 human brain 1,000 Blue Gene /L supercomputers

TION

1 kg 105 kgBlue Gene /L

TRODUCT

g100 W

1011 neurons

g1 MW

105 processors1 Blue Gene /L:

INT

1014 synapses100 Hz

1014 transistors1 GHz

recognized a face in 0.1 s still looking after 1 month... (when it gwas programmed as a neural network)

D. B. Strukov, NGCMoscow, September 2011

The Last Computing The Last Computing Frontier (II) Frontier (II) UCSB

Biological neural network Mathematical abstraction

x1w1TI

ON

x2 y

w1

w2TRODUCT

x3

2

w3

INT

‐ Software simulations too slowL k f ffi i t h d

1015 synapses1012 neurons


‐ Lack of efficient hardware 1 to 10000 connectivity

Analog vs. DigitalAnalog vs. DigitalUCSB

Proposed Hybrid Computation Circuits Resource vs. Precision

TION

TRODUCT

INT


R. Sarpeshkar, Neural Computation, 10 1601, 1998

Resistive Switching Resistive Switching “Memristive” Devices“Memristive” Devices

UCSB Memristive Devices Memristive Devices

insulating“OFF” stateI

state

Bipolar switching

DEV

ICES

V

ON

0

state OFF

VRISTIVE D

conducting“ON” state

V

state ON

VOFF

VON

MEM

electrolyte metal oxide

redox at interface

modulationof defect profile

primarymechanism: interface of defect profilemechanism:

oxygen vacancy = shallow donor7D. B. Strukov, NGCMoscow, September 2011

Drift Diffusion MechanismDrift Diffusion MechanismUCSB

Bulk model theory… … and exp

4

2

w

x)/N

DO

10‐1

ON OFF (v = +120v0)

yCurrent vs. sin voltage

0

‐2

2

Curren

t, J/J 0

DEV

ICES

NA

Dop

antN

D(x

10‐2

10‐3 Voltage v/v0

Curren

t J/J

0

‐41000‐100 ‐50 50

H.Yang et al. Nature Mat. 8 585 2009

RISTIVE D

0.2

al ‐φ

/(E G/e)

n+|n|p|n+

n+| n |n+Voltage, v/v0

MEM

Potenti

0Length0 1

n+|n|p|n+Interface model theory

Bulk Model assumption: ‐ 1D Stationary (el) + transient (ions) drift diffusion

Metal Electrode

mixed ionic/electronic compensated n‐semiconductor

MetalElectrode

‐ Constant mobility ‐ Ohmic electron + blocking ion interface

D.B. Strukov et al., Small, Feb. 18, 2009 D.B. Strukov et al., Nature, 2008


J.R. Jameson et al, APL 91, 112101, 2007M. Noman et al APA, 877, 2011

Retention vs. Retention vs. Speed vs. EnduranceSpeed vs. Endurance(linear ionic mobility) (linear ionic mobility)

UCSB

10-2

τstore/τwrite ~ vμi/D = v/v0

B0 120

v /v0

10-6

10-4

0

J 0V

0

DEV

ICES

4 40012 120040 4000

10-6 10-5 10-4 10-3 10-2 10-110-10

10-8s

A C

RISTIVE D

10 10 10 10 10 10tt0

MEM

t DO 10‐1

A

BCD

opant

ND(x)/N

L th /L 10

10‐3


Length x/L 10

Strukov et al. APA 2011

UCSB

Retention vs. Retention vs. Speed vs. EnduranceSpeed vs. Endurance(nonlinear ionic mobility) (nonlinear ionic mobility)

700

800102 103 104 105 106 107 108

E, Vcm10-4 10-2 100 102 104 106 108

7

8

E, Vcm

1 nm / min

E+

++

‐‐‐

+++

‐‐‐

+++

‐‐‐

+++

‐‐‐

++ ‐

‐ ++ ‐

‐

400

500

600

700

T,K

4

5

6

7

U

+

‐+

++

‐‐‐

+++

‐‐‐

+++

‐‐‐

+++

‐‐‐

+‐‐

++

‐‐

+

DEV

ICES

300

400

3

4

700

800

7

8

0.20.3

UA, eV1 nm / year1 nm / ms

1 nm / ns

UA

a

RISTIVE D

400

500

600T,

K

4

5

60.40.50.60.70.80.91.01.1

~qEaf

~kBT

MEM

102 103 104 105 106 107 108300

E, Vcm10-4 10-2 100 102 104 106 108

3

E, Vcm

1.2

Ion mobility is exponential with electric field and temperatureIon mobility is exponential with electric field and temperature

Strukov & Williams, ApplPhys A 94 515 (2009)

τSTORE/ τWRITE∞ Exp[E/E0] Exp[UA/kB (1/TSTORE-1/TWRITE)]10D. B. Strukov, NGC

Moscow, September 2011

SelfSelf‐‐HHeating (I)eating (I)lli

UCSB

nano metallic v

RC

RON

fit experimental data using equivalent circuit

4202468 1100 K1000

K

900 K

curren

t, m

A

-extract

onintermediateoff

gap ON state

dONz

r0

w

OFF state

wOFF

TiO dC

dOUT

perform 3D coupled

map temperature on I-V

2.0 1.0 0.0 1.04

voltage, V- -

- geometry from fitting

DEV

ICES

• Strong evidence of heating!

• Conducting filament

• Heating provides nonvolatility

wONTiO2(ρI,κI)

dC

electrode (ρE,κE)

metallicchannel(ρC,κC)

Lcoupled electro-thermal simulations

D.Strukov et al. MRS (2009)

RISTIVE D

290K140K3K

15

10

600ur

e (K

)Domain fitted on dataExtrapolation

g p y

MEM

10

5

0

I (mA)

ONOFF

INTERMEDIATE

ON

SHORT

OFF

500

400

ocal

Tem

pera

tu

J.Borghetti , D. Strukov et al.JAP (2009)

‐5‐1.0 ‐0.5 0.0 0.5 1.0

V (V)

SHORT

300

Lo

3020100I (mA) 11D. B. Strukov, NGC


Self‐Heating (II)STXM

(a)Bottom

UCSB

E= 445 eVBottomElectrode

TopElectrode

800

780

(b)(a)Top

ElectrodeTop ElectrodeCenterBottom Electrode

Temperature contour for heat source near:TopElectrode Membrane

xy z

(b)AmorphousTiO2

500 nm

10

760

740

BottomElectrode200 µm

DEV

ICES

AnataseTiO2Reduced TiO2-X

10

8

6

4

2Abso

rptio

n(a

.u.)

500 nm 50 nm50 nm

720

700 Kxy

xy

RISTIVE D

0470465460455

X-ray energy (eV)(c)

Top ElectrodeCenterBottom Electrode

Temperature contour forheat source near:

Top Electrode Top Electrode

(d)(c)50 nm

MEM

x y

Bottom Electrode Bottom Electrode

Silicon Nitride Silicon Nitride

z z

‐ Heating200 nm

JP Strachan , D. Strukov et al. Nanotechnology (2011)

Heating ‐ Heating spot location


UCSB

Yield and VariationsYield and VariationsDEV

ICES

RISTIVE D

MEM

13Slide courtesy of K.K. Likharev


Resistive Resistive Switching “Switching “MMemristoremristor” ” Device Device UCSB

insulating

++ Wide range of material systems (many CMOS compatible) and physical phenomena

‐‐ but simple functionality

200

insulating“OFF” state

100

0

100

rrent ( uA

) 50 nm hp

PtTiO V

+

DEV

ICES

electrolyte metal oxidechalcogenide

conducting“ON” state

J Yang Iet al Natue Nano (2008)

<50 ns‐200

‐100

Cu

‐2 ‐1 0 1 2Voltage ( V )

Pt

TiO2TiOx

V

‐

RISTIVE D

++ High density due to … monolithical 3D integration

J. Yang Iet al. Natue Nano, (2008)

lateral scaling and .. hybridsMEM

M.-J.Lee IEDM 85 (2008)(2008)

M.Johnson IEEE J Solid State Circuits 38 1920 (2003)

HPL, 200514D. B. Strukov, NGC


Hybrid Circuits: Main IdeaHybrid Circuits: Main IdeaUCSB

• End of lateral CMOS scaling 3D integration• Problems for conventional 3D stacking

• Solution: monolithical 3D hybrid circuits

CUITS

Hybrid (CMOS + memristor) circuits

Tightly integrated digitalBRID CIRC

Digital memory

Digital logic + memory

Tightly integrated digital memory/logic

Analog and mixed signal

HYB

Digital logic + memory

Programmable logic

programmable logic

Artificial neural nets


Crossbar Crossbar ArchitectureArchitectureXbar to preserve density

UCSB

i

top(nano)wire

level

‐ Xbar to preserve density ‐ Passive (no transistors) but nonlinear I‐ V ‐ Common way (from periphery)

i

vvw‐vw

vr

bottom (nano)wire

similar two‐terminaldevices at each crosspoint

level

CUITS

ReadRead WriteWrite

vwbottom (nano)wire level

BRID CIRC

V

VVr/2

= V

VVw/2

=HYB

A

V V =Vr/2 V V =Vw/2CMOS for d di VV =Vr =Vw

Vr/2 Vw/2decoding and sensing


Area Distributed Area Distributed Interface (CMOL)Interface (CMOL)UCSB

2FVIA α2FXBAR

sin = FXBAR/FVIA

cos = r FXBAR/FVIA

where r is integer

(2FVIA)2

2FXBAR vias breaks wires

where r is integer

CUITS

on segments

CMOS cellV

BRID CIRC

HYB

CMOS Main features:• Double decoding scheme

V

Original idea: Likharev (2005)Strukov & Likharev, Nanotechnol. 16 137 (2005)3D CMOL: Strukov et al. PNAS 2009

• Double decoding scheme• Tilted and segmented crossbar

17V

V


Hybrid Analog Circuits: Main IdeaHybrid Analog Circuits: Main IdeaUCSB

add‐on

Massively parallel matrix multiply

TS

CMOSstack

yWx W

D CIRCU

IT

x

G H

YRBID

x1

w

x1gj1

weight memristor

ANALO

G

x3

x2 yjwj1

wj2

wj3 x

x2gj2

gj3

‐+

jii

i gxj3 x3

CMOS

i

CMOS cell 18D. B. Strukov, NGCMoscow, September 2011

Analog Mode Operation (I) Analog Mode Operation (I) UCSB Measurement setup

TS

1.0

0.5

0.0

Vin

t (V)

(c)

40

Incremental reset Incremental setD

CIRCU

IT 40

20

0

I (µA

)

3210-1

Typical I‐V

1E 5

1E-4

1E-3 Single sweep

rren

t (A

)

100

Reset: Rinitial= ROFF

Set: Rinitial= RON

G H

YRBID

Normalized device resistance at ‐0.2V

1E-7

1E-6

1E-5

Cur

Vread = ‐ 0.2V

Pt

Pt

TiO2‐x

S

AV

1

10

R/R

initi

al

ANALO

G

-1.5 -1.0 -0.5 0.0 0.5 1.01E-7

Voltage (V)

1E-81E-71E-61E-5-1.2

0.01

0.1

(s)1E-51E-4

1E-30.01

0.11

1.2-0.8

-0.40.0

0.40.8

Pulse W

idth (

s

Pulse Voltage (V) 19D. B. Strukov, NGCMoscow, September 2011

M. Pickett, D.B. Strukov et al., JAP (2009)F Alibart and D. Strukov , 2011

UCSB

reset set

Analog Mode Operation (II) Analog Mode Operation (II)

1E-4

1V 0.95V 0.9V0.85V

00m

V (A

)

0.8V

1E-4

-0.9V-1.0V

1 1V@ -2

00m

V

-0.5V to -0.8V

TS

reset set

1E-5Cur

rent

@-2

0

0.5V to 0.75V1E-5

-1.1V

-1.2V

-1.3V

Cur

rent

@

D CIRCU

IT

0 20 40 60

Time (s)

0 5 10 15 20

Time (s)

G H

YRBID

R exp(V)reset transition dynamics

ANALO

G

100000

Model ExponentialEquation y = y0 + A*exp(R0*x)

Reduced Chi-Sqr

1.87853E8

Adj. R-Square 0.9725Value Standard Error

resistance y0 1000 0resistance A 112 61025 16 21722

100000Vp=-1.5V

R exp(V) R W

10000 1ms 1ms 1ms 1ms1ms

resi

stan

ce (

)

resistance A 112.61025 16.21722resistance R0 -5.3215 0.1022

10000

Res

ista

nce

(

1/3

Vp=-0.5V


0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6

1000

1ms exp. fit

Voltage (V)1E-7 1E-6 1E-5

1000

Cumulative pulse time (s)

p

Adaptive Write Scheme Adaptive Write Scheme UCSB

120

140

120A

A) Increase Weight

Decrease Weight

Stand-by (Read only) 30

31

32

-200

mV

(A

)

TS

80

100

200m

V (

A y ( y)

47.5 50.0 52.5 55.0 57.528

29

Cur

rent

@

Time (s)

voltage

0read

settime

D CIRCU

IT

40

60 60A

30A

urre

nt @

-2

121

122

0mV

(A

)

e (s)reset

G H

YRBID

0 25 50 75 100 125 1500

207A

Cu

15A

115 0 117 5 120 0 122 5 125 0118

119

120

Cur

rent

@ -2

00

ANALO

G

Time (s)115.0 117.5 120.0 122.5 125.0

Time (s)

‐ Tolerant to variations in devicesUp to 1% analog accuracy (more write time better accuracy)


‐ Up to 1% analog accuracy (more write time better accuracy)

22‐‐Input Multiply Input Multiply and Add and Add Demo Demo UCSB

0.20

0.25

TS

0.10

0.15

0.20

gggg

Out

put (

V)

1k

D CIRCU

IT

0.20.00

0.05

(V)

rogr

amm

ing

rogr

amm

ing

rogr

amm

ing

rogr

amm

ing

Input1 Input2

Output

CMOS opamp

G H

YRBID

0 1

0.20.00.1

1 (V

)

Inpu

t2 p rpp rpr

ANALO

G

0 50 1000.0

0.1

Inpu

t1

Time (s)


UCSB Electronic Synapses:Electronic Synapses: STDPSTDP

TSD CIRCU

IT

Bi l i l d l i

G H

YRBID Biological… …and electronic synapses

ANALO

G

S.H. Jo et al. Nano Letters, 10 1297 2010D. Kuzum Nano Letters 2011 online pubD. B. Strukov, Nature 476 404 2011


General Purpose CMOL FPGAsGeneral Purpose CMOL FPGAs‐Main idea: lift all configuration overhead

UCSB

typical FPGA …

metallization

… and with lifted config. bits

metallization& config bits

g

‐ HPL’s FPNITS

config. bits & logic logic

& config. bits

Bll

‐ HPLs FPNI‐ All logic functions in CMOS‐ Connectivity with memristors

D CIRCU

IT

‐ Programming for xpoint memristors similar to CMOL digital memories‐ Uniform fabric with CMOS inverter cells ‐ Diode logic with memristors + CMOS inverter for restoration and inversion

AB

cell‐ Generic CMOL FPGA

L HYR

BID

‐ Crossbar wires for routings

BA+B

cell AAB FD

IGITAL

BA+B

nanodevices

A

R

B

24

A

CMOS inverterA+B

RON

RpassCwire D. B. Strukov, NGCMoscow, September 2011

Hybrid CMOS / Hybrid CMOS / MemristorMemristor FPGA: First DemoFPGA: First Demo( ) (d)(a)

UCSB

(c) (d) (a)

i ti

n anowire layer 2

(titanium) NOT gateTS

nanowire layer 1

m emristive layer

AND gate

g

D CIRCU

IT

CMOS layer

(platinum)

NOT gate NAND gate

OR gate

L HYR

BID

(b )

AND gate

NOT gate

NAND gate

NOR gate DIGITAL

OR gate

D flip flop

Q. Xia et al. Nano Letters, 2009

gate

NOR gate

D flip flop


Pattern Matching ProblemPattern Matching ProblemKiller applications:General problem

UCSB

Killer applications:– Network intrusion detection of

computer viruses– DNA sequencing– Network packet routing

General problem

00101011101111101011100input output

Match?001010011010TS Network packet routing

– Associative memory (cache, database searching)

FPGA implementationTCAM implementation

011010

D CIRCU

IT

LB

LB

LB

LB

LB

LB output input

TCAM implementation

(T)CAM

L HYR

BID

0 0 1 1

‐ Circuit for pattern matching of “0011” and “1101”

LB

LB

LB

streamstream Processor(s)output stream

inputstream

DIGITAL

D Q D Q D Q D Qdata

in

data

out

0011

0 0 1 1

1

pattern

detected

1

26

match

1101match

0

1


CMOS technology cannot provide adequate performance!

CMOLCMOL FPGA for Pattern FPGA for Pattern MMatchingatchingUCSB

Mprepre

5

DQ

Q’

CMOS flip‐flop cell

nanodevice

Key features of new circuit:

‐ Diode‐logic TCAM cells (high density)

‐ CMOL FPGA architecture (lowTS

ONOFF OFFON OFFOFF ONOFF

eval1 2 3 4Q Q Q Q Q Q Q Q

D QQ’

CMOL FPGA architecture (low overhead for configuration, high integration bandwidth with crossbars)

Hybrid: TCAM + FGPAD CIRCU

IT

select/preeval

DQ Q

’ DQ Q

’ DQ Q

’ DQ Q

’ 12 4

crossbar

Hybrid: TCAM + FGPA

store patterns L

HYR

BID

DQQ’

select/pre

select/pre

12

5

wirepin crossbar

DIGITAL

3data/pre

select/pre

select/predata/pre

4

5

~4 orders better (in processing power) as

27Strukov et al., Nanotech’11Alibart et al. Proc. AHS’11

~4 orders better (in processing power) as compared to pure CMOS implementation


SummarySummaryUCSB

• Memristive Devices– dense, stackable, analog, nonvolatile and potential fastintrinsic tradeoffs (write/retention/endurance)– intrinsic tradeoffs (write/retention/endurance)

– yield and variation is still a problem but …• still immature field with increasing industry involvement

• Analog Hybrid Circuits– analog circuits: just the top of the iceberg?

C C/ C i fi bl fil• MAC, ADC/DAC, tuning, configurable filters, FPAA, ANN etc.• different requirement for devices

• Digital H brid Circ its• Digital Hybrid Circuits– 3D crossbar digital memories – programmable digital circuits: New life for diode logic?


AcknowledgementsAcknowledgementsi i / ll b i / li i k

UCSB

Discussion/collaboration/preliminary work: HPL: J. Borghetti, A. Bratkovski, M. Pickett, G. Snider, D. Stewart (now at Ottawa

Nat Lab, J.P. Strachan, R.S. Williams, J. Yang, Q. Xia (now at UMass)UCSB K T Ch F Ch T Sh d S St L Th jUCSB: K.‐T. Cheng , F. Chong, T. Sherwood, S. Stemmer, L. TheogarajanSBU: K. LikharevUCB: A. Mishchenko, R. BraytonPortland State U: D Hammerstrom J Carruthers C Teuscher

UCSB G M b

Portland State U: D. Hammerstrom, J. Carruthers, C. TeuscherMicroXact: V. KocherginORNL: S. Kalinin

UCSB Group Members:Fabien Alibart, PhD, ECELigang Gao, PhD, ECEAshok Ramu PhD ECEAshok Ramu, PhD, ECEBrian Hoskins, MaterialsElham Zalmanidoost, ECEAdvait Madhavan, ECEGina Adams, ECEXinjie Guo, ECE


FY 2011 MURI Program FY 2011 MURI Program

MURI Topic 15: Investigation of 3‐D Hybrid Integration of CMOS/Nanoelectronic Circuits

University of California, Santa BarbaraStony Brook University State University of New YorkStony Brook University, State University of New YorkUniversity of MichiganUniversity of Massachusetts, Amherst

30

THANK YOU!THANK YOU!comments/questions/suggestions:

[email protected]

31

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Analog CMOS/CMOS/MemristorMemristor Hybrid Circuitsasdn.net/ngc2011/presentations/strukov.pdf · Analog CMOS/CMOS/MemristorMemristor Hybrid Circuits Dmitri Strukov UC Santa Barbara