SPICE MODEL of TPCP8002 (Standard+BDS Model) in SPICE PARK

All Rights Reserved Copyright (c) Bee Technologies Inc. 2006

Device Modeling Report

Bee Technologies Inc.

COMPONENTS: Power MOSFET (Model Parameters) PART NUMBER: TPCP8002 MANUFACTURER: TOSHIBA Body Diode (Model Parameters) / ESD Protection Diode


Circuit Configuration


MOSFET MODEL

PSpice model parameter

Model description

LEVEL

L Channel Length

W Channel Width

KP Transconductance

RS Source Ohmic Resistance

RD Ohmic Drain Resistance

VTO Zero-bias Threshold Voltage

RDS Drain-Source Shunt Resistance

TOX Gate Oxide Thickness

CGSO Zero-bias Gate-Source Capacitance

CGDO Zero-bias Gate-Drain Capacitance

CBD Zero-bias Bulk-Drain Junction Capacitance

MJ Bulk Junction Grading Coefficient

PB Bulk Junction Potential

FC Bulk Junction Forward-bias Capacitance Coefficient

RG Gate Ohmic Resistance

IS Bulk Junction Saturation Current

N Bulk Junction Emission Coefficient

RB Bulk Series Resistance

PHI Surface Inversion Potential

GAMMA Body-effect Parameter

DELTA Width effect on Threshold Voltage

ETA Static Feedback on Threshold Voltage

THETA Mobility Modulation

KAPPA Saturation Field Factor

VMAX Maximum Drift Velocity of Carriers

XJ Metallurgical Junction Depth

UO Surface Mobility


10

15

20

25

30

35

40

45

50

1 2 3 4 5 6 7 8 9 10

ID - Drain Current - A

gfs

Measurement

Simulation

Transconductance Characteristic

Circuit Simulation Result

Comparison table

Id(A) gfs

Error(%) Measurement Simulation

0.1 5.000 5.000 0.000

0.2 6.500 6.667 2.569

0.5 10.000 10.000 0.000

1 16.500 16.667 1.012

2 22.500 22.500 0.000

5 35.500 35.714 0.603

10 45.000 45.455 1.011


V20Vdc

V1

10Vdc

V3

0Vdc

0

U26

TPCP8002

V_V2

0V 0.4V 0.8V 1.2V 1.6V 2.0V 2.4V

I(V3)

0A

4A

8A

12A

16A

20A

Vgs-Id Characteristic

Circuit Simulation result

Evaluation circuit


0.10

2.10

4.10

6.10

8.10

0.0 0.4 0.8 1.2 1.6 2.0 2.4

VGS - Gate to Source Voltage - V

ID -

Dra

in C

urr

en

t -

A

Measurement

Simulation

Comparison Graph Circuit Simulation Result

Simulation Result

ID(A) VGS(V)

Error (%) Measurement Simulation

0.1 1.280 1.278 -0.156

0.2 1.300 1.296 -0.308

0.5 1.300 1.331 2.385

1 1.350 1.371 1.556

2 1.400 1.428 2.000

5 1.500 1.54 2.667

10 1.600 1.669 4.313


VDS

0Vdc

VGS

4.5Vdc

0

V3

0Vdc

U26

TPCP8002

V_VDS

0V 50mV 100mV

I(V3)

0A

1.0A

2.0A

3.0A

4.0A

5.0A

6.0A

Rds(on) Characteristic


Evaluation circuit

Simulation Result

ID=4.5A, VGS=4.5V Measurement Simulation Error (%)

RDS (on) 0.007 0.007 0


U26

TPCP8002

V2

0Vdc

I29.1Adc

0

I1

TD = 0

TF = 10nPW = 600uPER = 1000u

I1 = 0

I2 = 1m

TR = 10n-

+W1

ION = 0uAIOFF = 100uAW

V116Vdc

D1

Dbreak

Time*1mS

0 20n 40n 60n

V(W1:3)

0V

2V

4V

6V

8V

10V

Gate Charge Characteristic


Evaluation circuit

Simulation Result

VDD=16V,ID=9.1A ,VGS=5V

Measurement Simulation Error (%)

Qgs(nC) 8.000 8.026 0.325

Qgd(nC) 12.000 11.974 -0.217

Qg 48.000 35.921 -25.165


Capacitance Characteristic

Simulation Result

VDS(V) Cbd(pF)

Error(%) Measurement Simulation

0.1 300.000 298.000 -0.667

0.2 235.000 235.000 0.000

0.5 140.000 141.000 0.714

1 75.000 75.000 0.000

2 40.000 39.000 -2.500

5 15.000 14.000 -6.667

10 10.000 9.800 -2.000

Simulation

Measurement


L2

50nH

L1

30nH

U26

TPCP8002R2

4.7

V110Vdc

V2TD = 1u

TF = 10nPW = 10uPER = 200u

V1 = 0

TR = 10n

V2 = 10

0

RL

2.22

R1

4.7

Time

0.95us 1.00us 1.05us 1.10us 1.15us 1.20us 1.25us

V(L1:2)*2 V(L2:1)

0V

2V

4V

6V

8V

10V

12V

Switching Time Characteristic


Evaluation circuit

Simulation Result

ID=3.6 A, VDD=15V VGS=0/10V

Measurement Simulation Error(%)

Ton(ns) 24.000 24.089 0.371

VGS

ID


U26

TPCP8002

Vdsense

0Vdc

Vstep

10Vdc

0

Vv ariable

10Vdc

V_Vvariable

0V 0.4V 0.8V 1.2V 1.6V 2.0V

I(Vdsense)

0A

4A

8A

12A

16A

20A

Output Characteristic


Evaluation circuit

VGS=1.4 V

1.5

1.8

1.7

1.6


V1

0VdcU26

TPCP8002

0

R1

0.01m

V_V1

0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V

I(R1)

100mA

1.0A

10A

100A

BODY DIODE SPICE MODEL Forward Current Characteristic


Evaluation Circuit


0.10

1.00

10.00

0 0.2 0.4 0.6 0.8 1 1.2

Source-Drain voltage VSD(V)

Dra

in r

evers

e c

urr

en

t ID

R(A

)

Measurement

Simulation

Comparison Graph Circuit Simulation Result

Simulation Result

IDR(A) VSD(V)

%Error Measurement Simulation

0.1 0.540 0.539 -0.185

0.2 0.560 0.561 0.179

0.5 0.600 0.594 -1.000

1 0.620 0.626 0.968

2 0.660 0.664 0.606

5 0.740 0.732 -1.081

10 0.800 0.802 0.250


0

U24

TPCP8002

R1

50

V1

TD = 55n

TF = 25nsPW = 1usPER = 100us

V1 = -9.4v

TR = 10ns

V2 = 10.6v

Time

0.7us 0.8us 0.9us 1.0us 1.1us 1.2us 1.3us 1.4us 1.5us 1.6us

I(R1)

-400mA

-300mA

-200mA

-100mA

-0mA

100mA

200mA

300mA

400mA

Reverse Recovery Characteristic Circuit Simulation Result

Evaluation Circuit

Compare Measurement vs. Simulation

Measurement Simulation Error (%)

Trr(ns) 123.500 123.778 0.225


Reverse Recovery Characteristic Reference

Trj=21.500ns) Trb=102.000(ns) Conditions:Ifwd=lrev=0.2(A),Rl=50

Relation between trj and trb

Example


0

V1

0Vdc

U24

TPCP8002R1

0.01mR2

100MEG

V_V1

0V 5V 10V 15V 20V 25V 30V 35V 40V 45V 50V

I(R1)

0A

1mA

2mA

3mA

4mA

5mA

6mA

7mA

8mA

9mA

10mA

ESD PROTECTION DIODE SPICE MODEL

Zener Voltage Characteristic


Evaluation Circuit


Zener Voltage Characteristic Reference

Technology

SPICE MODEL of TPCP8002 (Standard+BDS Model) in SPICE PARK