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The World Leader in High Performance Signal Processing Solutions
EverywhereEverywhere
“SPICE Compatible Models for Circuit Simulation of ESD
Events”Jean-Jacques (J-J) Hajjar, Srivatsan Parthasarathy
& Paul Zhou
IEEE Electron Device Society ColloquiumUniversity of Central Florida, Orlando, FL
March 20, 2012
EverywhereEverywhere
MOTIVATION
2
Key Drivers: the 3 “S” Simulation: Predicting robustness of a particular
design to ESD prior to manufacture.
Synergy: Synthesize the physical concepts thatdescribes the ESD event into a self-containedsolution.
Simplicity: Automate and integrate simulationflow in a standard circuit simulationenvironment.
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OUTLINE
3
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks
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OUTLINE
4
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks
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What is ESD?
5
Definition: Electro-Static DischargeRelevance: - Damages IC
- Key “product quality” metricCustomer Return Pareto:
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What is ESD?
6
Designing for ESD Robustness: Common Practice
Design cycle:
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What is ESD?
7
Designing for ESD Robustness: The benefit ofSimulation
Design cycle:
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OUTLINE
8
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks
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Modeling Objectives & Approach
9
A. Verification– Pass or Fail Robustness test– Interaction with Core (or Protected) Circuitry
B. Optimization– Redundant or insufficient protection?
C. Design Cycle Reduction– First pass success
D. Simplicity– Adopted by end-user
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V1
V2
R R
Q1 Q2
Q3
R1R1
R3
R5 R6R4
Q4 Q5
Q6
VOUT
Modeling Objectives & Approach
10
Quantify Charge dissipation and Failure
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Modeling Objectives & Approach
11
Device Model Development Characteristics: ASIIC
● Accurate● Simple● Incremental
– Leverage standard device models.
● Integrated– Compatible with circuit design environment.
● Comprehensive– Protection as well as protected devices modeled.
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Modeling Objectives & Approach
12
ESD Characteristics
A. Electrical:– Large currents & large voltages
– Short duration: 1-200 ns.
B. Physical Failure:– Junction damage
– Dielectric/Gate-oxide damage
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Modeling Objectives & Approach
13
ESD Characteristics
C. Limited applied stimulus:
– Two common models: HBM & CDM
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DCSTRESS
Modeling Objectives & Approach
14
What to model?
● Focus on region beyond normal operation.● Determine failure point.
DEVICEFAILURE
NORMALOPERATION
(VMAX, IMAX)
VOLTAGE →
VI
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DEVICEFAILURE
(VMAX, IMAX)
NORMALOPERATION
AVALANCHECURRENT
VOLTAGE →
VI
ESDSTRESS
Modeling Objectives & Approach
15
What to model?
● Focus on region beyond normal operation.● Determine failure point.
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Modeling Objectives & Approach
16
Measuring DUT Transient CharacteristicsCharacteristics obtained using a TLP (transmission line pulse)measurement technique.
CU
RR
ENT→
I AVER
AG
E→
_i
_v
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OUTLINE
17
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks
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Model Development
18
What to model?
SiGe Complementary Bipolar ProcessProprietary high performance fully dielectrically isolatedcomplementary bipolar process with SiGe NPN.
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V1
V2
R R
Q1 Q2
Q3
R1R1
R3
R5 R6R4
Q4 Q5
Q6
VOUT
Model Development
19
Incentive for Device Model Development
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Model Development
20
What Devices to Model?
A. Core Devices: Bipolar transistors: PNP & NPN
Diodes
Passive Devices
B. Protection Devices: ESD Diodes
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Model Development
21
Physical Mechanisms to Model
● Junction Breakdown
● Avalanche Current
● Velocity Saturation
● Kirk Effect
● Resistivity Modulation
● Failure
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Model Development
22
Non-Physical Diode-Switch Model
● Verilog-A Implementation:– Variable “turn-on” Voltage: Von
– Variable series Resistance: R
0 1 2 3
Current (A)
Voltage (V)
R
Von
0.5
1.0
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Model Development
23
ESD Diode Model
Standard operation Operation during ESD event
-1 -0.5 0 0.5 1
Current (A)
Voltage (V)
`0.05
0.1
0.05
-4 -3 -2 -1 0 1Voltage (V)
Current (A)
0.5
1.0
0.5
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Model Development
24
ESD Diode Model
● Sub-circuit consisting of Ideal and Standard diodes.
STANDARD DIODENON-PHYSICALDIODE-SWITCH
on V
I
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Model Development
25
Bipolar Breakdown Models• BVEBO: Emitter-Base junction breakdown with Collector floating.• BVCBO: Collector-Base junction breakdown with Emitter floating.• BVCEO: Collector-Emitter breakdown with Base floating.
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Model Development
26
Leverage and Integrate with Standard SPICE Model
● Start with MEXTRAM model● Add necessary elements to
model high-current/voltage transient.
Ci
Bi
Ei
C
E
B
MEXTRAM
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Model Development
27
NPN Emitter-Base Breakdown Model
D1
R1
VEBO
● NPN BVEBO is modeled using:– Ideal diode: D1– Series resistance: R1– DC source: VEBO=BVEBO
● Diode turns on at VEBO
Device Failure (VM,IM)
NPN AE=0.35 5.2 m
BVEB0
SIMULATIONDATA
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Model Development
28
PNP Emitter-Base BreakdownTLP I-V Characteristics
POLYSILICON E
BCEXT-BASE
r
VOLTAGE (V)
BVEB0
0
50
100
150
200
0 4 8 12
PNP AE=4 1 10 m
Device Failure (VM,IM)
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Model Development
29
PNP Emitter-Base Breakdown Model● A parallel breakdown is
observed at V>BVEBO● This breakdown is modeled
using:– Ideal diode: D2– Series resistance: R2– DC source: VEBO1=BVEBO1
r
PARALLEL(R2)
BVEB0
PNP AE=4 1 10 m
PRIMARY(R1)
Device Failure (VM,IM)
SIMULATIONDATA
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Model Development
30
NPN Collector-Base Breakdown Model● BVCBO is modeled using:
– Ideal diode: D2– Series resistance: R2 – DC source: VCBO=BVCBO
● Diode turns at VCBO
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Model Development
31
PNP Collector-Base BreakdownPulsed I-V Characteristics
CU
RR
ENT
(mA
)
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Model Development
32
PNP Collector-Base Breakdown Model● A Parallel breakdown path is
observed due to the reach-through between extrinsic-base/collector.
● Current flows laterally instead of vertically.
D4
R4
D3
R3
VCBOVCBO1
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Model Development
33
Collector-Emitter Breakdown
● Impact ionization in the base collector depletion region. ● Electron-hole pairs swept into the base and collector respectively. ● Results in forward-biasing the base-emitter base junction.● Current flow from emitter to collector sustains the avalanching in the
depletion region
N P N
E B C
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Model Development
34
Collector-Emitter Breakdown Model● The collector-emitter breakdown characterized by several physical
mechanisms. ● Primary breakdown is due to avalanche.● Carrier velocity saturation and conductivity modulation are also
observed.
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Model Development
35
Using MEXTRAM to Model Collector-Emitter Breakdown:
● Weak avalanche is modelled in MEXTRAM.
● The resulting current will turn-on the Emitter-Base diode.
● This is sufficient to initiate and sustain the breakdown.
● The collector resistance will be optimized to model the conductivity modulation.
● Velocity saturation is also modelled in MEXTRAM.
S
RCV
C B E
CBCO CBEO
RCC
RBCRBV
RE
INQBE IB
ISUBQBCIBC
QSUB
E1
B1B2
C1
C2
IAVL
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Model Development
36
Collector-Emitter Breakdown ModelNPN PNP
0
20
40
60
80
VOLTAGE (V)0 4 8 12
Device Failure (VM,IM)
BVCEO
NPN AE=1 10 m
CU
RR
ENT
(mA
)
SIMULATIONDATA
PNP AE=1 10 m
0 10 20
r
VOLTAGE (V)
CU
RR
ENT
(mA
)BVCEO
0
20
40
60
80
Device Failure (VM,IM)
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Model Development
37
Bipolar Model for ESD Event Simulations
D1
R1
Ci
Bi
Ei
MEXTRAM
D2
R2
CBO Model
EBO Model
VEBO
VCBO
C
EB
D1
R1
Ci
Bi
Ei
D2
R2
D4
R4
D3
R3
VEBO
VCBOVCBO1
VEBO1
C
EB
MEXTRAM
CBO Model
EBO Model
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DEVICEFAILURE
(VMAX, IMAX)
NORMALOPERATION
AVALANCHECURRENT
VOLTAGE →
VI
Model Development
38
Failure Metric● Difficult to Model● Empirical formulation– Current density– Energy dissipation
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Model Development
39
Failure Metric● Difficult to Model● Empirical formulation– Current density– Energy dissipation
0 4 8 120
100
200
300
EMITTER AREA ( m2)
MAXIMUM CURRENT (mA) — 100 NS. PULSE
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OUTLINE
40
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Example
5) Concluding Remarks
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Circuit Simulation Example
41
Full-Chip ESD Simulation● High frequency RF quadrature modulator● Required to pass 2,000V HBM ● ESD simulation mimics actual HBM testing
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Circuit Simulation Example
42
Full-Chip ESD SimulationThe design failed 1,000V HBM when stressed between supply VCC and the I/O pin (VOUT).
FAILED NPN (Q9: AE=0.35 5.2 m)
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Circuit Simulation Example
43
● The simulation identified NPN Q9 to go into BVCEO and conduct current before the ESD protection turns on.
TLP CHARACTERISTICS OF INDIVIDUALNPN TRANSISTOR Q9
VOLTAGE TRANSIENT DURINGHBM STRESS
VOLT
AG
E (V
)C
UR
REN
T (m
A)
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Circuit Simulation Example
44
● Current and Voltage transient of NPN transistor Q9 during HBM stress with failure region highlighted.
VOLT
AG
E (V
)C
UR
REN
T (m
A)
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Circuit Simulation Example
45
● XIVA (eXternally-Induced Voltage Alteration) micrograph● The failure location identified was the output NPN transistor flagged by the
ESD simulator.
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Circuit Simulation Example
46
● Fix consists of adding resistor in series with transistor Q9● Resulting current through transistor Q9 decreases to below failure level.
CURRENT TRANSIENT DURING HBM STRESS ACROSS TRANSISTOR Q9
R R
Q1 Q2
Q3
R1
R3
Q4
VOUT
Q9R
0
20
40
60
0 0.2 0.4 0.6 0.8 1C
UR
REN
T (m
A)
TIME (10-6 sec.)
FAILURE
ORIGINAL DESIGN
REVISED DESIGN
Q9: NPN AE=0.35 5.2 m
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OUTLINE
47
1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Example
5) Concluding Remarks
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SUMMARY
48
● An enhanced compact bipolar breakdown model was developed for a SiGe bipolar process.
● The model was built around the industry-standard MEXTRAM compact bipolar model, enabling SPICE-like circuit simulation.
● The model developed is integrated as part of the standard SPICE-type circuit simulation environment.
● Simulation accuracy was confirmed using circuit simulation example and the relevant Failure Analysis techniques.
● Predictive ESD simulation methodology used successfully on over four dozen designs, over four bipolar process technologies and on various design complexities.
The World Leader in High Performance Signal Processing Solutions
EverywhereEverywhere
“SPICE Compatible Models for Circuit Simulation of ESD
Events”Jean-Jacques (J-J) Hajjar, Srivatsan Parthasarathy
& Paul Zhou
IEEE Electron Device Society ColloquiumUniversity of Central Florida, Orlando, FL
March 20, 2012