3DD 1e 31 Luglio Apertura

Politecnico di MilanoPolitecnico di Milano

Dynamic Reconfigurability inEmbedded System Design

- Prima Edizione della 3-Giorni DRESD -

31/07 - 1-2/08, 200631/07 - 1-2/08, 2006Hotel Villa GinaHotel Villa Gina

GoglioGoglio

1° 3-Giorni DRESD1° 3-Giorni DRESD

OutlineOutline

Something about DRESDDRESD philosophyDRESD teamWhere we are workingSome results

Projects and ThesisConferencesPartnerships

DRESD project: the beginningCaronte

FlowArchitecture

DRESD and Linux: the software architectureICAP kernel moduleThe IP-Core Manager

DRESD project: what we are doingSyCERSSome theoretical aspectsThe complete approach

The Acheronte flowYaRAHow to extend YARA and the Acheronte flow


OutlineOutline




FlowArchitecture





DRESD PhilosophyDRESD Philosophy

Do or do not! There’s no try!Do or do not! There’s no try! Master Yoda

I need to believe that something I need to believe that something

extraordinary is possible!extraordinary is possible!Alicia Nash


DRESD TeamDRESD Team

People30 Undergraduate students12 Graduate students2 PhD3 Researchers4 Professors

MeetingRegular meeting every two weeksDRESD Weekend, August


Where we are working: Where we are working: ReconfigurationReconfiguration

fix

TotalEmbedded


DRESD in the WORLDDRESD in the WORLD

EuropePaderborn University and HNI

USA:UICNorthwestern


Progetti di RLA 03/04Progetti di RLA 03/04Campione di 30 StudentiCampione di 30 Studenti

55% 45%

Solo Progetto Tesisti

29%

23%

3%

45%

Solo Progetto Luglio Ottobre Marzo



53% 47%


3%29%

21%47%

Solo Progetto Luglio Ottobre Marzo



Progetti di RLA 05/06: 33 Studenti

9%

55%


6%

35%

5%

45%

Solo Progetto Luglio Settembre Marzo


Some results: Some results: ConferencesConferences

Papers: 10

Journal: 1

Conferences Organization:Chair: 1PC: 4Reviewer: 6 + 1 TVLSI


Some results: Some results: PartnershipsPartnerships

Industries:Italian-European:

Siemens Mobile, Contacts: Ferrara GiovannaATMEL, Contact: Ben Altieri, Piergiovanni Bazzana, Pier Stanislao, Chiara NencioniST – Microelectronics, Contact: Davide PandiniDA Sistemi, Contact: Chiara Coppola, Andrea Zucchetti

American:Xilinx Inc., Contact: Jeff Weintraub, Monica MaccanImpulseC, Contacts: David Buechner, David Pellerin

Italian Universities:Collegio Sant’Anna, Contact: prof. Marco Di NataleUniversità degli studi di Milano, Contacts: prof. Roberto Cordone

European Universities:ALaRI, contacts: prof.ssa Mariagiovanna Sami, prof. Umberto BondiPaderborn e Heinz Nixdoerf Institute, contact: prof. Mario PormanUniversitaet Karlsruhe, Contact: prof. Juergen Becker

Noth American Universities:UIC, contacts: prof. John Lillis, prof. Florin Balasa, prof. Shantanu Dutt, Lynn ThomasNorthwestern, contacts: prof. Seda Ogrenci Memik, Pam Mitchell, Rene HallIndiana University Purdue University Indianapolis, Contact: John Lee


DRESD and HNIDRESD and HNI

Partitioning and SchedulingStatic Scheduling for Reconfigurable ArchitecturePlacement and SchedulingLinux on Raptor2000Dynamic Driver Generation for Custom IPsDistributed reconfigurable scenarios

Cluster Based and Network Based


DRESD and UICDRESD and UIC

Memory

JHDL


AC2SWA - Adaptive Computing to SW acceleration:

AC4C - Adaptive Computing for Codesign:

DRESD and NorthwesternDRESD and Northwestern


OutlineOutline




FlowArchitecture





CaronteCaronte

WhoMarco D. SantambrogioDonatella SciutoFabrizio Ferrandi

ObjectivesPropose a novel embedded partial reconfigurable architecture (RSoC)Define a complete methodology to port a generic application on the proposed architecture


DRESD: The Caronte FlowDRESD: The Caronte Flow


HW-SSP SequencingHW-SSP Sequencing


DRESD: The Caronte DRESD: The Caronte ArchitectureArchitecture


DRESD and LinuxDRESD and Linux

WhoAlberto DonatoVincenzo FrascinoPaolo MartinoVincezo RanaMarco SantambrogioGuido Serra

ObjectivesProvide software support for dynamic partial reconfiguration on Systems-on-Chip running the LINUX operating system.Issues:

Partial reconfiguration process management from the OSAddition and removal of hardware reconfigurable componentsAutomatic loading and unloading of specific drivers for the IP-Cores upon components configuration/deconfigurationEasier programming interface for specific drivers


Software ArchitectureSoftware Architecture

Composed of two main elements:Driver to support partial reconfigurationManager for the IP-Cores devices

The software architecture provides:

Access to ICAP component from userspaceInterface between IP-Cores low-level drivers and kernelAccess to reconfigurable devices from userspace processes


The ICAP Kernel ModuleThe ICAP Kernel Module

Implements a device driver, adds kernel support for the Xilinx ICAP component.

Access from userspace via standard device node mechanism (i.e. /dev/icap)Masks hardware detailsReconfiguration data provided in the form of partial bitstream files


The IP-Core ManagerThe IP-Core Manager

A LINUX kernel module which implements a unified infrastructure for the management of the IP-Cores.IP-Cores Plug-and-Play

Runtime loading of specific IP-Cores driversManagement of operations common to all driversAccess to reconfigurable components from userspaceStandardize and simplify writing of specific drivers


The IP-Core Manager: The IP-Core Manager: HierarchyHierarchy

The IP-Core Manager acts as a layer between the operating system kernel and the low-level device drivers.

The low-level drivers contain:system calls implementationdevices initialization and shutdown functions

The drivers also contain a stub:provides standard kernel module interfaceprovides module initialization and shutdown functions


Caronte: Standalone Vs LinuxCaronte: Standalone Vs Linux

Table 2 - Original Caronte vs. Caronte with Linux on the XC2VP7 FPGA

Resource

Orignal Caronte Caronte LinuxTotal Available

Elem. Perc.(%)

Elem. Perc.(%)

Slice Flip Flops 1843 18 2369 24 9856

4-input LUTs 1727 17 2173 22 9856

Occupied Slices 1818 36 2262 45 4928

Bonded IOBs 107 27 168 42 396

Block RAM 32 72 32 72 44

DCMs 2 50 2 50 4


Distributed scenariosDistributed scenarios


OutlineOutline




FlowArchitecture





SyCERSSyCERS

WhoFrancesco BruschiCarlo AmicucciFabrizio FerrandiChiara SandionigiMarco SantambrogioDonatella SciutoStefano Viazzi

ObjectivesDefine a novel model to describe reconfigurable systems

Based on know HDL (no new languages)To be used in the early first stage of the project; to consider the reconfiguration at the system level

Propose a complete framework for the simulation and the design of reconfigurable systems

Providing system specification that can be simulatedAllowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time Taking into account the software side of the final system


TLM e SystemCTLM e SystemC

Separare la definizione delle funzionalità del sistema dalla definizione dei dettagli di comunicazioneAttraverso la definizione di un Canale di comunicazione

DEF.: un canale implementa una serie di interfacce che sono esposte ai componenti funzionali connessi attraverso di esso.DEF.: un’interfaccia espone i metodi che possono essere invocati dal componente funzionale per comunicare.

SystemC, dalla versione 2.0, permette di utilizzare la TLM per mezzo dei costrutti:

write()read()

write()read()

module Amodule A

pA->write(v)pA->write(v)

module Bmodule B

v=pB->read()v=pB->read()

channel

pA pB

sc_interface

sc_port


The SyCERS methodologyThe SyCERS methodology

SpecificationModel

SpecificationModel

ComponentAssembly

Model

ComponentAssembly

Model

BusFunctional

Model

BusFunctional

Model

Define the system functionalityNo information regarding the final implementation

Solution space explorationProvides the functionalities implementation detailsNo information regarding the communication

Computed solution validation via the simulation


A reconfigurable component A reconfigurable component using SystemCusing SystemC

It’s not possible to instantiate an sc_module during the simulation phaseIt’s possible to modify the SC_THREAD and the SC_METHOD via:

function pointersc_mutex

ConfigurationCombined with the reconfiguration time

ElaborationProvided with the elaboration time

*g()

Reconfigurable Component(sc_module)

Configuration(function pointer)

mutex


Reconfigurable component Reconfigurable component behaviourbehaviour


Caronte ModelsCaronte Models

Control Code(SystemC)

Control Code(SystemC)

CompilerGCC

CompilerGCC

ConfigurationsBlackBox(SystemC)

ConfigurationConfiguration

Control Process

Control Process

Schedulerand Controller

Schedulerand Controller

MemoryModel

MemoryModel

ModelloMemoria

BlackBoxes

ModelCoreConnect

ModelCoreConnect

PowerPCISS

PowerPCISS

Open SystemC PowerPC core models

Cross Compiler GCC

Cross Compiler GCC

Control Code(C/C++)

Control Code(C/C++)


Theoretical AspectsTheoretical Aspects

WhoGianpaolo AgostaFrancesco BruschiRoberto CordoneFabrizio FerrandiChiara FornoniMatteo GianiFrancesco RedaelliMassimo RedaelliMarco SantambrogioPaola Spoletini

ObjectivesPartitioningSchedulingHLS MetricsFloorplanning


Reconfigurable Hardware: Reconfigurable Hardware: why?why?

Time

Area

Aw

Shw

Sw

Ao

Sho So

Feasible Solution Space

Shde

Ade

Problem:Ad < Ade


Reconfigurable Hardware: Reconfigurable Hardware: why?why?

Time

Area

Aw

Shw

Sw

Ao

Sho So

Feasible Solution Space

Shde

AdeAd Avd

Shvd

Svd


Partitioning problemPartitioning problem


The Acheronte FlowThe Acheronte Flow

WhoElisa MalviciniAlessio MontoneAntonio PiazziMarco Santambrogio

ObjectivesExtend the Caronte flow to support different FPGAs Define a complete automated version of the FlowExtend the Caronte flow to support different architectural solution, e.g YARA, Raptor2000


Acheronte: il flusso per la creazione di YaRAAcheronte: il flusso per la creazione di YaRA

.:: Obiettivi

.:: Caronte

.:: YaRA> Parte fissa> Moduli riconf.> Infrastruttura di comunicaz.

.:: Acheronte

.:: Test

.:: Conclusioni

.:: Sviluppi futuri

.::Domande


YaRAYaRA

WhoFabio CancarèAlessio MontoneAntonio PiazziMarco Santambrogio

ObjectivesExtend the Caronte architecture to support the linear placement solutionSolve the communication constraints of the previous architecturePresent an architecture that can be easily portend on different board, e.g Raptor2000


YaRA: the embedded 1D YaRA: the embedded 1D approachapproach

IP-CoreF1

IP-CoreF2

IP-Core

F3

Fix side:PPCICAP

FPGA


YaRA: parte fissaYaRA: parte fissa


YaRA: FPGA LayersYaRA: FPGA Layers

Clock

Modulo Riconf.

Macro HW

PPC-405

BRAM e Moltiplicatori 18x18

Parte Fissa

.:: Obiettivi

.:: Caronte

.:: YaRA> Parte fissa> Moduli riconf.> Infrastruttura di comunicaz.

.:: Acheronte

.:: Test

.:: Conclusioni

.:: Sviluppi futuri

.::Domande

CLB x

CLB y

Layer


Caronte Vs YaRACaronte Vs YaRA

Caronte YaRARiconfigurabilità Parziale e Dinamica

Riconfigurabilità Interna

N° di moduli 2 Anche diverse decine

Continuazione della comunicazione durante la riconfigurazione

Intercambiabilità dei moduli

Utilizzo tecnologie standard


How to extend YaRA and AcheronteHow to extend YaRA and Acheronte

The “YaRA” side:D-ICAPD-WBMBiRFIP-Core Generator ToolEDK System Creator

The “Acheronte” side:RCPCGADGBAnMaTRecOnDemand


D-ICAP: DRESD - ICAPD-ICAP: DRESD - ICAP

WhoChiara SandionigiMarco SantambrogioRiccardo SomagliaPaolo Tornese

ObjectivesDefine the DRESD – ICAP core, characterized by:

Support DMA communicationHW-IPCM integration


D-WBM: DRESD - Wishbone D-WBM: DRESD - Wishbone BUSMacroBUSMacro

WhoDanieleValentinaFabio CancarèMarco Santambrogio

ObjectivesCreate the communication infrastructure for a given instance of the YARA architectureAutomatic XDL description manipulation to define the correct MacroHW for the bus infrastructure


BiRF: Bitstream Relocation BiRF: Bitstream Relocation FilterFilter

WhoSimone CorbettaMassimo MorandiMarco NovatiMarco Santambrogio

ObjectivesAutomatic replacement of a reconfiguration bitstreamHW implementation of such a filter to speed-up its execution


WhoMatteo MurgidaAlessandro PanellaVincenzo RanaMarco SantambrogioDonatella Sciuto

ObjectivesCreate an EDK compatible IPCore given the VHDL description of the coreSupport the PLB, OPB and the Wishbone BUS infrastructureFully support the YARA architecture

IP-Core Generator ToolIP-Core Generator Tool


EDK System CreatorEDK System Creator

WhoRoberto PalazzoMarco Santambrogio

ObjectivesGiven a known EDK system architecture and a generic IPCore description

Automatic binding of the two inputs into a downloadable and executable bitstream

Fully support the YARA architecture


RCPCG: Reconfigurable Core Placer RCPCG: Reconfigurable Core Placer Constraints GeneratorConstraints Generator

WhoCristiana BolchiniStefanoGilulia Marco Santambrogio

ObjectivesAssign the placement constraints for a reconfigurable core to be used with the YARA architectureFind the best floorplanning constraints according with different optimization function, e.g. #AssignedCLBs/#UsedCLBs


ADG: Automatic Driver ADG: Automatic Driver GenaratorGenarator

WhoMaurizio SalaVincenzo RanaMarco SantambrogioNicolas Tagliani

ObjectivesComplete the IP-Core Generator tool work with the creation of the correct driver for a given IP-CoreCreate the basic infrastructure for both the standalone and the OS version of the driver


BAnMaT: BAnMaT: Bitstream Analizer Manipulator ToolBitstream Analizer Manipulator Tool

WhoSimone CorbettaMarco Santambrogio

ObjectivesBitstream analyzerEasy API to manage the bistream fileDifference bitstream file checkerReconfiguration bitstream debugger


RecOnDemandRecOnDemand

WhoFabrizio FerrandiAlessandro MeleVincenzo RanaMarco Santambrogio

ObjectivesClient-Server application for remote FPGA control:Serial Mode:

It downloads a bitstream, the client, that can dialogue with a second entity, the server, to request partial or complete reconfiguration

Download Mode:It allows the download of a sequence of bitstreams for a fixed number of time

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3DD 1e 31 Luglio Apertura