MAPLD2005 / Submission 2221Lake
Reliability Analysis of the Aeroflex ViaLink™ FPGA
MAPLD International Conference
September 8, 2005
Session D: Reliability
Ronald Lake
Aeroflex Colorado Springs
www.aeroflex.com/radhardFPGA
MAPLD2005 / Submission 2222Lake
Agenda
Background– Aeroflex begins QML-Q / QML-V Qualification of RadHard Eclipse FPGA
– Original approach followed MIL-PRF-38535 standards
– Approach outlined in previously published papers
– Then the world changed (Industry Tiger Team, Aerospace Corp., NASA GSFC, etc.)
New Approach– November 2004: Aeroflex received “Aerospace Requirements for FPGAs in Space”
– Aeroflex adopts enhanced MIL-PRF-38535 QML Qualification with Aerospace Corporation guidelines
Un-programmed burn-in Operating life test (HTOL / LTOL)
Current Status– Aeroflex completes QML-Q / QML-V qualification: August 2005
– Standard Microcircuit Drawing (SMD) #:5962R04229
– Aeroflex announces QML results: September 2005 (MAPLD)
– Aeroflex ships first Rad-Assured QML materials: September 2005
MAPLD2005 / Submission 2223Lake
QML Qualification Compliance Matrix
Aeroflex vs. Aerospace Corp. Guidance
Condition Aeroflex AerospaceGroup A MIL-PRF-38535 MIL-PRF-38535Group B MIL-PRF-38535 MIL-PRF-38535Group C MIL-PRF-38535 MIL-PRF-38535Group D MIL-PRF-38535 MIL-PRF-38535
Dynamic Burn-InCore=3.4V, I/O=4.6V,
125C, 16HrsCore=2.75V, I/O=3.6V,
125C, 240Hrs
LTOLCore=2.75V, I/O=3.6V, -55C, Read Pts: 96, 500,
1000Hrs
Core=2.75V, I/O=3.6V, -55C, Read Pts: 500, 1000,
2000, 3000, 4000, 5000, 6000 Hrs
HTOLCore=3.2V, I/O=4.1V,
125C, Read Pts: 96, 500, 1000Hrs
Core=2.75V, I/O=3.6V, 125C, Read Pts: 500,
1000, 2000, 3000, 4000, 5000, 6000 Hrs
MAPLD2005 / Submission 2224Lake
Aerospace Evaluation Structural Evaluation
– Using focused ion beam techniques
– Output – 3 dimension model (colorized)
Follow-on evaluations
– Effect on adjacent ViaLinks
– Lot to Lot variation
– Via Links vs Programming
– Spatial Wafer Evaluation (center to edge)
– Lot to Lot variations
– Failed ViaLink (if possible)
3Q2005ElementalStructural
ProgrammedUn-Programmed
ElementalStructural
Task
4Q20051, 3 and 5 pulse programmed ViaLinks (bi-directional)Uni-Directionally Programmed ViaLinkUnprogrammed ViaLink
CompletionSample Type/Description
MAPLD2005 / Submission 2225Lake
Un-programmed ViaLink Cross Section
Figure removed untilProprietary issues are resolve.This was a late arriving paperand I apologize for this, I wastoo nice and will fix that forMAPLD 2006. -- rk
MAPLD2005 / Submission 2226Lake
Reliability Design for ViaLink Operating Life
Goal: Create worst case design for ViaLink stress
– Adhere to NASA OLD guidelines for reliability test vehicles for fuse based FPGAs
Design
– Use all FPGA logic, memory and I/O resources
– Use all wiring types, with associated ViaLinks
– Force high fan-out structures for flip flops and logic
– Maximize current density through ViaLinks
– Manually fix placement to force use of long wires and worst case ViaLinks
– Use dedicated and global clocks for synchronous logic
– Synchronize reset to insure initialization conditions
– Create long combinatorial and synchronous chains for AC delay measurements
MAPLD2005 / Submission 2227Lake
Life Test Environment for RadHard Eclipse
Goal: Subject RadHard Eclipse to real world environment during life test to stress ViaLinks
Life test conditions
– Do not de-couple or terminate I/O signals
– Allow voltage spikes on inputs
– Allow noise on I/O and within wiring array of ViaLinks
– Evaluate multiple power sequencing conditions
– Use extended times in stress chambers
– Closely monitor power supplies
MAPLD2005 / Submission 2228Lake
Test Environment for Characterization
Goal: Create repeatable and accurate test environment for measurement of RadHard Eclipse ViaLink characteristics
Test Conditions
– Use Teradyne Tiger tester for accurate measurements of quiescent current and propagation delay
– Test all temperature conditions: -55ºC, 25ºC and 125ºC
– Test all voltage conditions: 2.3V core and 3.0V I/O; 2.5V core and 3.3V I/O; 2.7V core and 3.6V I/O
– Use control units to verify test environment does not change between stress read points
– Review all test results prior to next stress, comparing worst case deltas to means
MAPLD2005 / Submission 2229Lake
Un-programmed burn-in
Applied to 100% of un-programmed units passing manufacturing stress Standard step in Aeroflex QML manufacturing flow 240 hrs of 125°C burn-in at maximum operating conditions (Vcc=2.7V, Vccio=3.6V) FPGAs dynamically stimulated during burn-in After burn-in devices tested for quiescent current (Icc, Iccio) and un-programmed electrical test (3 temperature, min/typ/max voltage) Percent defective allowable (PDA) <5%
Lot ID # units # pass % defectiveQL0882 377 367 2.65%RD0910 59 59 0%RD0947 288 287 0.30%
MAPLD2005 / Submission 22210Lake
Operating Life AC Deltas LTOL: 77 test units + 3 control
– No ViaLink failures at 1000 Hrs stress
– <3% change in propagation delay HTOL: 77 test units + 3 control
– No ViaLink failures at 1000 Hrs stress
– <10% change in propagation delay Delay deltas calculated for all voltage &
temperature combinations
Worst Case 251 Bit NAND Chain
100
120
140
160
180
200
0 200 400 600 800 1000Operating Life Stress (Hrs)
Pro
pag
atio
n D
elay
(n
s)
HTOL
LTOL
Reliability Design Feature
Details Clock
Synchronous Scan Chains
560 bit fast data quadrant
Two 360 bit Chains - high fan-out (16), fast data
dedicated
Two 225 bit Chain - high fan-out (16), fast data
global
SRAM 3072x18 quadrant
Register File 64x8 quadrant
Registered I/O Buffers
global
Combinatorial Chains
NAND w/ fanout 16
251 bit NAND w/ placement, 251 bit NAND, autoplace
MAPLD2005 / Submission 22211Lake
Co60 AC Deltas
Delta’s calculated at room temperature for all voltage combinations
<5% change in delay at 100 krad(Si) <15% change in delay at 300 krad(Si) Irradiated at 1 rad(Si)/sec Propagation delays stay within simulation
limits
Worst Case 251 Bit NAND Chain
100
120
140
160
180
200
0 100 200 300
Total Ionizing Dose (krad(Si))
Pro
pag
atio
n D
elay
(n
s))
NAND Delay
Reliability Design Feature
Details Clock
Synchronous Scan Chains
560 bit fast data quadrant
Two 360 bit Chains - high fan-out (16), fast data
dedicated
Two 225 bit Chain - high fan-out (16), fast data
global
SRAM 3072x18 quadrant
Register File 64x8 quadrant
Registered I/O Buffers
global
Combinatorial Chains
NAND w/ fanout 16
251 bit NAND w/ placement, 251 bit NAND, autoplace
MAPLD2005 / Submission 22212Lake
Radiation Testing
ConditionsVDD I/O, VDD
Core, TempSN Ion
Normal LET, MeV-cm²/mg
Angledegrees
Flux
ions/cm2-sLatchup
Fluence (normal)
ions/cm2
Effective Fluence
ions/cm2
Effective LET MeV-cm²/mg
3.6, 2.7, 125C 24 Au 90.3 41 7.8E+04 0 1.3E+7 1.0E+7 1203.6, 2.7, 125C 10 Au 90.3 41 6.9E+04 0 1.3E+8 1.0E+8 1203.6, 2.7, 125C 22 Au 90.3 41 6.0E+04 0 1.3E+7 1.0E+7 1203.6, 2.7, 125C 2 Au 90.3 41 6.3E+04 0 1.3E+7 1.0E+7 120
FPGAComponent
Temp(C)
VddCore, I/O
(V)
Numberof storage
cells
WeibullShape
WeibullWidth
SaturatedX-section
(cm2/bit)
Onset LET
(MeV-cm2)
Error-rate(Errors/bit-
day)RegF 25 2.25/3.00 1,024 1.6 100 2.10E-07 23 4.40E-09ShiftR 25 2.25/3.00 1,120 1.4 85 4.50E-07 15 2.20E-08
ShiftR w/ TMR 25 2.25/3.00 400 2 20 8.00E-08 76 1.90E-10RAM 25 2.25/3.00 55,296 1.95 125 9.60E-08 17.5 6.90E-10
1.0E-10
1.0E-09
1.0E-08
1.0E-07
1.0E-06
0 20 40 60 80 100 120
LET (MeV-cm2/mg)
Cro
ss
Se
cti
on
(c
m2 /b
it)
SN 20
SN 27
SN 7
SN 4
weibull
Single Event Effects
SerialNumber
Temp VDDCore & I/O
Pulse WidthFWHM (ns)
Latch-up(y/n)
Dose Rateat Die(rad/sec)
70 125C 2.75V/3.6V 35 n 6.37E+1169 125C 2.75V/3.6V 35 n 5.58E+1168 125C 2.75V/3.6V 35 n 5.73E+1167 125C 2.75V/3.6V 35 n 5.62E+1165 125C 2.75V/3.6V 35 n 6.09E+1166 125C 2.75V/3.6V 35 n 5.98E+1164 125C 2.75V/3.6V 35 n 5.25E+1163 125C 2.75V/3.6V 35 n 5.84E+1162 125C 2.75V/3.6V 35 n 6.16E+1161 125C 2.75V/3.6V 35 n 5.91E+1171 125C 2.75V/3.6V 35 n 5.82E+11
Lowest AllFail Limit
(rad/sec(Si))
Highest AllPass Limit
(rad/sec(Si))
Specification(rad/sec(Si))
SurvivalProbability
(%)
Number ofSamplesIrradiated
ConfidenceLimit (%)
1.18E+10 8.95E+09 8.7E+09 90.00 11 901.18E+10 8.95E+09 7.7E+09 99.00 11 901.18E+10 8.95E+09 6.9E+09 99.90 11 901.18E+10 8.95E+09 6.2E+09 99.99 11 90
Propagation Delay vs. Total Ionizing Dose
0
10
20
30
40
50
60
0.01 0.10 1.00 10.00MegaRad (Si)
Pro
pag
atio
n D
elay
(n
S)
NAND2 Delay Chain (866 Elements)
44 Stage Input Buffer NAND Tree
Input Buffer to PCI Compliant Output BufferPre-Rad ACs
Aeroflex SEC Test ChipExample Propagation Delay Paths
2.75V @ 25oC
Total Ionizing Dose
Dose Rate
MAPLD2005 / Submission 22213Lake
Timing Characterization
QuickLogic Timing Release Flow
Oscillator Design
(34 types)
Initial Data
Collection
• Pre Release Data
• Aeroflex
Timing Generation
Re-Simulate Oscillator
Designs
• Aeroflex • QuickLogic • Aeroflex
Silicon
Vs Simulation
• Aeroflex
Spde Release
• QuickLogic
Verification Loop Current Status
– Aeroflex speed grade -5 primitive library provides >10% guard band vs. silicon for combinatorial and most synchronous delays
– Margins maintained for material after TID of 300krads (Si)
– Some exceptions exist due to Aeroflex removal of charge pump on FPGA
– Delay library undergoing updates for 4Q2005 release
MAPLD2005 / Submission 22214Lake
Summary
Aeroflex Colorado Springs has embraced the Aerospace Corporation’s guidelines to enhance the QML qualification flow
Burn-in analysis demonstrates <3 % defective after 3 temperature testing (QML lot acceptance PDA<5%)
Worst case conditions used for ViaLink™ operating life test– LTOL delay analysis demonstrates <3 % change in
propagation delay after 1000 Hrs of stress– HTOL delay analysis demonstrates <10% change in
propagation delay after 1000 Hrs of stress TID delay analysis demonstrates <5% change in
propagation delay at 100krad and <12% change at 300krad ViaLink structural and elemental analysis underway with
Aerospace Corporation RadHard Eclipse FPGA qualified as Rad-Assured QML Q/V