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University of Tehran 1
Microprocessor System Design
Omid Fatemi
Memory Interfacing
University of Tehran 2
Outline
• Address decoding
• Chip select
• Memory configurations
University of Tehran 3
Processor Timing Diagram of 8088 (Minimum Mode)for Memory or I/O Read (with 74245)
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R __
IO/M __
____
RD
DEN______
A19 - A0from 74LS373 to memory
S6 - S3A19 - A16
A19 - A0 from 74LS373
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
D7 - D0from memory to 74LS245
D7 - D0 (from memory)
D7 - D0 from74LS245
garbageA7 - A0
A15 - A8
University of Tehran 4
Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OE
LE 74LS373
D7 - D0 Q7 - Q0
OE
LE 74LS3738088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DEN
DT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OE
LE 74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0A7 - A0 B7 - B0
E
DIR 74LS245
A7 - A0
A15 - A8
A19 - A16
RD
WR
University of Tehran 5
Minimum Mode
MEMORY
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMW
When Memory is selected?
University of Tehran 6
Minimum Mode
MEMORY
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMWCS
220 bytes or 1MB
University of Tehran 7
What are the memory locations of a 1MB (220 bytes) Memory?
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0 0011 0100 11111 1101 0000
University of Tehran 8
Interfacing a 1MB Memory to the 8088 Microprocessor
2300000
00001
10000
10001
10002
10003
10004
10005
10006
10007
10008
95
::
45
98
27
39
42
88
07
F4
8A
::
20020
20021
20022
20023
FFFFD
FFFFE
FFFFF
29
12
7D
13
19
25
36
::
::
::
::
A19
A0
:
D7
D0
:
RD
WR
A19
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
CS
University of Tehran 9
Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?
University of Tehran 10
What are the memory locations of a 512KB (219 bytes) Memory?
A18 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
University of Tehran 11
Interfacing a 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMWXXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
2300000
00001 95
::
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
::
::
::
A18
A0
:
D7
D0
:
RD
WR
CS
A19What do we do with A19?
University of Tehran 12
What if you want to read physical address A0023?
A18
A0
:
D7
D0
:
MEMR
MEMWXXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
A000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
2300000
00001 95
::
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
::
::
::
A18
A0
:
D7
D0
:
RD
WR
CS
A19
University of Tehran 13
What if you want to read physical address A0023?
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
A0023 1010 0000 0000 0010 0011
A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”, the memory cannot “see” this.
University of Tehran 14
What if you want to read physical address 20023?
A18 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
20023 0010 0000 0000 0010 0011
For memory it is the same as previous one.
University of Tehran 15
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 16
Interfacing two 512KB Memory to the 8088 Microprocessor
• Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read.
• Solution: Use address line A19 as an “arbiter”. If A19 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
University of Tehran 17
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 18
What are the memory locations of two consecutive 512KB (219 bytes) Memory?
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
University of Tehran 19
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
Interfacing two 512KB Memory to the 8088 Microprocessor
When the P outputs an address between 80000 to FFFFF, this memory is selected
When the P outputs an address between 00000 to 7FFFF, this memory is selected
University of Tehran 20
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 21
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
A18
A0
:
D7
D0
:
RD
WR
A19
University of Tehran 22
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
9700000
00001 D4
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
A3
92
45
33
2C
98
12
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
What if we remove the lower memory?
University of Tehran 23
What if we remove the lower memory?
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CSWhen the P outputs an address between 80000 to FFFFF, this memory is selected
When the P outputs an address between 00000 to 7FFFF, no memory chip is selected !
University of Tehran 24
Full and Partial Decoding
• Full Decoding– When all of the “useful” address lines are connected the
memory/device to perform selection
• Partial Decoding– When some of the “useful” address lines are connected
the memory/device to perform selection
– Using this type of decoding results into roll-over addresses
University of Tehran 25
Full Decoding
A18
A0
:
D7
D0
:
MEMR
MEMW
XXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
A19
2300000
00001 95
:
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
:
:
:
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 26
Full Decoding
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
A19 should be a logic “1” for the memory chip to be enabled
University of Tehran 27
Full Decoding
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
Therefore if the microprocessor outputs an address between 00000 to 7FFFF, whose A19 is a logic “0”, the memory chip will not be selected
University of Tehran 28
Partial Decoding
A18
A0
:
D7
D0
:
MEMR
MEMWXXXX
BP
ES
DS
SS
CX
BX
AX
XXXX
XXXX
XXXX
2000
0000
0023
3F1C
FCA1
SP
DX
XXXX
CS
SI
XXXX
XXXXIP
XXXXDI
2300000
00001 95
::
20020
20021
20022
20023
7FFFD
7FFFE
7FFFF
29
12
7D
13
19
25
36
::
::
::
A18
A0
:
D7
D0
:
RD
WR
CS
A19
University of Tehran 29
Partial Decoding
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not
University of Tehran 30
Partial Decoding
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ACTUAL ADDRESS
University of Tehran 31
Partial Decoding
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ACTUAL ADDRESS
University of Tehran 32
Interfacing two 512K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB#2
A18
A0
:
D7
D0
:
RD
WR
CS
512KB#1
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 33
Interfacing one 512K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 34
Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2)
8088Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 35
Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3)
8088Minimum
Mode
A18
A0
:
D7
D0
:
MEMR
MEMW
A19
512KB
A18
A0
:
D7
D0
:
RD
WR
CS
University of Tehran 36
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
University of Tehran 37
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
University of Tehran 38
Memory chip#__ is mapped to:
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
----- ---- ---- ---- ---- ----
----- ---- ---- ---- ---- ----
University of Tehran 39
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
University of Tehran 40
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
University of Tehran 41
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CSI1I0
O3
O2
O1
O0
University of Tehran 42
Interfacing several 8K Memory Chips to the 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#?
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
University of Tehran 43
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
University of Tehran 44
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
University of Tehran 45
Memory chip#__ is mapped to:
A19 to A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
1000
AAAA
7654
AAAA
3210
----- ---- ---- ---- ---- ----
----- ---- ---- ---- ---- ----
University of Tehran 46
Memory Terms
• Capacity – Kbit, Mbit, Gbit
• Organization– Address lines
– Data lines
• Speed / Timing– Access time
• Write ability– ROM
– RAM
University of Tehran 47
ROM Variations
• Mask Rom
• PROM – OTP
• EPROM – UV_EPROM
• EEPROM
• Flash memory
University of Tehran 48
RAM Variations
• SRAM
• DRAM
• NV-RAM
– SRAM – CMOS
– Internal lithium battery
– Control circuitry to monitor Vcc
University of Tehran 49
Memory Chip
• 8K SRAM
• to be specific:– 8Kx8 bits SRAM
6264
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CS2
I/O0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS1
OE
WE
University of Tehran 50
6264 Block Diagram
University of Tehran 51
6264 Function Table
University of Tehran 52
Memory Chip
• 8K EPROM
• to be specific:– 8Kx8 bits EPROM
2764
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
VPP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
G
P
University of Tehran 53
2764 Block Diagram
Chip enable
Output enable
University of Tehran 54
Operating Modes
University of Tehran 55
Programming 2764
• after each erasure for UV-EPROM):– all bits of the M2764A are in the “1" state.
• The only way to change a “0" to a ”1" is by ultraviolet light erasure.
• Programming mode when:– VPP input is at 12.5V
– E and P are at TTL low.
• The data to the data output pins.
• The levels required for the address and data inputs are TTL.
University of Tehran 56
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
