UNIT 1 of ASIC

7/26/2019 UNIT 1 of ASIC

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APPL ICATION SPECIFIC

INTEGRATED CIRCUITS DESIGN

-Ankita Tijare


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WHATISTHISCOURSEALLABOUT?

The course is about Higher Methodology for ASIC

design and includes various testing techniques,

fault models, algorithms.


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An ASIC is application-specific integrated circuit.

History of integration: smal l-scale integrat ion

(SSI, ~10 gates per chip, 60s), medium scaleintegration (MSI, ~1001000 gates per chip, 70s),

large-scale integration (LSI,~100010,000 gates

per chip, 80s),very large-scale integration (VLSI,

~10,000100,000 gates per chip, 90s),ultra large

scale integration (ULSI, ~1M10M gates per chip)


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History of technology: bipolar technology and

transistortransistor logic (TTL) preceded metal-

oxide-silicon (MOS) technology because it was

difficult to make metal-gate n-channel MOS; the

introduction of complementary MOS greatlyreduced power.

The feature size is the smallest shape you can

make on a chip and is measured in l or lambda


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Origin o f ASICs: the standard parts, initially used

to design microelectronic systems, were gradually

replaced with a combination of glue logic, custom

ICs, dynamic random access memory (DRAM) and

static RAM (SRAM)


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ASIC

An application-specific integrated circuit, ASIC

pronounced a-sick, is an integrated circuit

(IC) customized for a particular use, rather than

intended for general-purpose use.


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ASICSVS. WHAT?

Application Specific Integrated Circuit A chip designed to perform a particular operation as

opposed to General Purpose integrated circuits

An ASIC is generally NOT software programmable

to perform a wide variety of different tasks

An ASIC will often have an embedded CPU to

manage suitable tasks

An ASIC may be implemented as an FPGA

Sometimes considered a separate category


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ASICSVS. WHAT? (CONTD.)

General Purpose Integrated Circuits:

Examples:

Programmable microprocessors (e.g. Intel Pentium

Series, Motorola HC-11) Used in PCs to washing machines

Programmable Digital Signal Processors (e.g. TI

TMS 320 Series)

Used in many multimedia, sensor processing andcommunications applications

Memory (dRAM, SRAM, etc.)


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ASICSVS. STANDARDIC

Standard ICsICs sold as Standard Parts SSI/LSI/ MSI IC such as MUX, Encoder, Memory

Chips, or Microprocessor IC

Application Specific Integrated Circuits (ASIC) A

Chip for Toy Bear, Auto-Mobile Control Chip, DifferentCommunication Chips [ GRoT: ICs not Found in Data

Book]

Concept Started in 1980s.

An IC Customized to a Particular System orApplicationCustom ICs.

Digital Designs Became a Matter of Placing of

Fewer CICs or ASICs plus Some Glue Logic.

Reduced Cost and Improved Reliability.


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TYPESOFASIC:-

Full-Custom ICs/Fixed ASICs and Programmable ASICs

Wafer :A circular piece of pure silicon (10-15 cm in dia, butwafers of 30 cm dia)

Wafer Lot:5 ~ 30 wafers, each containing hundreds of

chips(dies) depending upon size of the die Die: A rectangular piece of silicon that contains one IC

design

Mask Layers: Each IC is manufactured with successive

mask layers(1015 layers)

First half-dozen or so layers define transistors Other half-dozen or so define Interconnect


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FULLCUSTOMASICS

Full Custom ASICs

Every transistor is designed and drawn by Hand

Typically only way to design analog portions of

ASICs Gives the highest performance but the longest

design time

Full set of masks required for fabrication


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Full-Custom ASICs

Include some customized logic cells

Have all their mask layers customized

Full-custom ASIC design makes sense only

When no suitable existing libraries exist or

Existing library cells are not fast enough or

The available pre-designed/pre-tested cells consume too

much power that design can allow or The available logic cells are not compact enough to fit or

ASIC technology is new or/and so special that no cell

library exits.

Offer highest performance and lowest cost (smallest die size)

but at the expense of increased design time, complexity,

higher design cost and higher risk.

Some Examples: High-Voltage Automobile Control Chips,

Ana-Digi Communication Chips, Sensors and Actuators


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SEMI-CUSTOMASICS:

STANDARD-CELLBASEDASICS (CBIC- SEA-BICK)

Use logic blocks from std. cell

libraries, other mega-cells,

full-custom blocks, system-

level macros(SLMs), functional

standard blocks (FSBs), cores

etc.

Get all mask layers customized

- transistors and interconnect

Manufacturing lead time isaround 8 weeks

Less efficient in size and

performance but lower in

design cost


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SEMI-CUSTOMASICSCONTD

STANDARD-CELLBASEDASICS (CBIC-

SEA-BICK) CONTD


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GATE-ARRAY-BASEDASICS:

In a gate-array-based ASIC, the transistors are

predefined on the silicon wafer.

The predefined pattern of transistors is called the

base array.

The smallest element that is replicate to make the

base array is called the base or primitive cell.

The top level interconnect between the transistors

is defined by the designer in custom masks-Masked

Gate Array(MGA).

Design is performed by connecting predesigned

and characterized logic cells from a library.


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Gate Array based ASICs


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GATEARRAYBASEDASICS(CONT)


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Semi-Custom ASICsContd

Programmable ASICs- ContdStructure of a CPLD / FPGA

FPGA

CPLD


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DESIGNFLOW:


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DESIGNFLOW:

Design Entry- Using a hardware descriptionlanguage(HDL) or schematic entry.

Logic synthesis- Produces a netlist-logic cells and theirconnections.

System partitioning- divide a large system into ASIC-sized pieces.

Prelayout simulation- Check to see if the designfunctions correctly.

Floorplanning- Arrange the blocks of the netlist on thechip.

Placement- Decide the locations of the cells in a block.

Routing- make the connections between cells in a block. Extraction- Determine the resistance and capacitance of

the interconnect.

Postlayout simulation- Check to see the design stillworks with the added loads of the interconnect.


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ASICCELLLIBRARIES

A library of cell is used by the designer to design

the logic function for an ASIC.

Option for cell library:

1. Use a design kit from the ASIC vendor Usually requires the use of ASIC vendor approved

tools.

Cells are phantoms- empty boxes that get filled in

by the vendor when you deliver, or hand off thenetlist.

Vendor may provide more of a guarantee that

design will work


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ASICCELLLIBRARIES:

2. Buy an ASIC-vendor library from library vendor

Library vendor is different from fabricator.

Library may be approved by the foundry

Allows the designer to own the masks for the partwhen finished.

3. You can build your own cell library

Difficult and costly.


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ASICCELLDEVELOPMENT:

A complete ASIC library must include the following

for each cell and macro:

A physical layout

A behavioral modelA VHDL or verilog model

A detailed timing model

A test strategy

A circuit schematicA cell icon (symbol)

A wire- load model

A routing model.


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ECONOMICSOFASICS:

On a parts only basis,an FPGA is more expensiveper-gate than MGA,which is in turn more expensivethan a CBIC.

The key is that the fixed cost of the CBIC is higher

than the MGA which is higher than the FPGA-design Cost

-fabrication cost

Total product(or part) cost is a function of fixed cost,

variable cost, and the total number of products(parts sold):

total part cost= fixed part cost+ variable part cost

X volume of parts


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BREAK- EVENANALYSISEXAMPLE:


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ASICFIXEDCOSTS:

Documents

UNIT 1 of ASIC