KaiSemi - FPGA to ASIC, ASIC to ASIC, DSP to ASIC CONVERSIONs

8/9/2019 KaiSemi - FPGA to ASIC, ASIC to ASIC, DSP to ASIC CONVERSIONs

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,P G A t o A S I C ,P G A t o A S I C,S I C t o A S I C ,S I C t o A S I C

S P t o A S I CS P t o A S I CCONVERSIONsCONVERSIONs


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Reduce Production CostReduce Production Cost

Reduce your FPGA chip cost by more than 50%from your product, with no effort from your side"

KaiSemi provides you a Guaranteed ASIC drop-inreplacement with No NREpayment, as Fast as 6-

14 weeks.

KaiSemi is the only vendor who owns in-housesemi-automated tools converting FPGA-to-ASICdirectly from netlist, any size of FPGA.

KaiSemi will convert your FPGA, covering thewhole ASIC workflow from customer decisionuntil 2nd source product shipping, seamless tocustomer work.

-


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KaiSemi is a fablesssemiconductor vendorspecialized in product conversions of:

FPGA-to-ASICASIC-to-ASICDSP-to-ASICMultiChip-to-ASIC

www.kaisemi.comKaiSemi is a part of the Kai-Tek Group of

companies, a well establishedrepresentative, distributor and a R&Dservice provider in the semiconductor

market with a strong financial backing. www.kai-tek.com

The Kai-Tek Group is a member of the ATeGAdvanced Technology Group, a provider

of very strong technical offerings to itscustomers, worldwide, from design-in toroduction service.

About KaiSemiAbout KaiSemi
http://www.kaisemi.com/http://www.kai-tek.com/http://www.kai-tek.com/http://www.kaisemi.com/


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Specialists of Cost-reduction chips

Cost-reduction by FPGA-to-ASIC replacement.

Any size of FPGASeamless automated conversion directly from Netlist

End-Of-Life continuation ASIC-to-ASIC replacement.

Cost-reduction by merging multiple FPGAs/ASICs:

into a single-die replacement, or

into a multi-die single package replacement

Drop-in replacement:

fully compatible pin-to-pin 2nd source

functional replacement with decreased package

Cost-reduction and performance boost by DSP-to-ASIC.

KaiSemi services


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Technical background:

Why replace FPGA by ASIC ?

.ignificant Cost reduction .Significant Power saving -Protection and copy securing of Intellectual

.Property

:Board cost reduction No need for

/ ; -Flash EPROM chip May reduce size in a multi.FPGA case

- .Eliminates power up reconfiguration time

.Significant lower radiated EMI


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KaiSemi is focused onconverting, FPGA or ASIC,directly from the FPGAs Post-P&R-Compiled Netlist.

Kai-Semi has an exclusive set oftools and processes to convertdirectly from FPGA netlist toASIC final chip.

Converting from FPGA netliststage allows us to givequality guarantee with nofunctional risk and very fastcycle time.

KaiSemi exclusive Workflow

RTL fit to ASIC

Full ASICSynthesis

FunctionalSimulation

Timing +FunctionalSimulation

DFT insertions

Layout P&R

Timing + FunctionalSimulation

FAB hand-off

FPGARTL

FPGANetlist

Traditional flowKaiSemi flow

ASIC Netlist

KaiSem

i

in-house

tool s


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KaiSemi business model

1.Functionality Guaranteed No good, no pay.

2.Zero NRE Payment Minimum Risk.

3.Fastest cycle-time as fast as -1 4 weeks.4.Minimum customer intervention Fire and

forget.

5.Any size FPGA Minimum complexity limitation.

1

2

3

5

4

Customer


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KaiSemi exclusive benefits1. Functionality Guaranteed (No Good No Pay!), because:

No RTL touch ! Functional source code is untouched.

Using ONLY the Netlist outcome of the proven working FPGA.

Proven in-house semi-automated developed conversion tool with experiencelimits human errors

2. No NRE Payment (No Risk), because:

Our business model is targeted to ease on the customer. Based on minimumquantity ordering.

3. Fastest cycle-time, because: Shortening ASIC flow cycle by using automated process and by starting, higher,

from netlist stage

Limiting the need for customers cycles of RTL flow, synthesis, verifications and

back-annotations. Having well established coherent work flow with FABs.

4. Minimum customer intervention (Fire & Forget), because: Customer is required to provide 2 main receivables:

1.The FPGA netlist

2. A verification test vectors. From that point on we proceed in posted mode, performing the whole ASIC

process until providing a final working chip.


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KaiSemi Team

The KaiSemi team is built from experts, having 12to 19 years of experience in the relevantactivity of FPGAs & ASIC conversions including

the full flow required for ASIC productization.The team members have an experience of over

500 successful FPGAs & ASIC conversions.


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KaiSemi Additional Expertise

Delivering a fully compatible pin-to-pin packaged device based on the existingFPGA.

Capability to fit compatible IPs, PLLs & I/Os of FPGAs to ASICs.

Capability to provide various types of special cells like PLLs, DLLs, ADPLLs,

Multipliers, Power-On-Reset and broad range of IPs.

KaiSemi has a well established infrastructure with FABs and Processes in awide range of technology processes (0.5u, 0.35u, 0.18u, 0.13u, 0.09u). FAB-Process is carefully defined based on the required frequency and otherdesign constraints, targeting to lower the cost.

Supporting Commercial, Industrial and Military grades.

Supporting Mixed signal and custom Analog cells solutions.

Providing Custom low power design for specific modules.

Supporting High performance libraries and clocking, convering both high speed


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ASIC to ASICASIC to ASICKaiSemi provides EOL (End Of Life) replacements for

ASICs taking care of the entire production process,without customer involvement.

We guarantee a fully compatible drop-in replacementfor use as a reliablereplacement part second source.

We do not charge NRE, we only get paid for the

working parts, so no risk is involved for the customer.

KaiSemi has also the capability to provide ASIC to ASICconversion for improving performance and/or usingimproved replaceable ASIC libraries and IPs.


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Multi Chip MergeKaisemi provides advanced multi chip

solutions, that convert severalFPGA's into one ASIC, thus reducingthe total system cost and powerconsumption immensely.

We could also package your EOL (EndOf Life) ASIC or converted FPGAalong with its external memoriesetc. thus enabling further cost

reduction and a reduced PCBfootprint.

We have the ability to assembleMultiple dies in a single package.


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DSP to ASICDSP to ASIC

KaiSemi offers a migration flowfrom DSP designs to a dedicatedASIC.

This allows our customers to boostDSP performance up to x100from the existing top of the lineexpensive DSP chips.

KaiSemi offers a developmentenvironment flow and service to

import DSP designs into ASICwhile using evaluationverification on an FPGA.

DSP design houses can now boostperformance per cost in their

applications, by moving from atraditional DSP chip to a

Perfblcks/sec

Platform

6,835 TI C5410 160MHz

12,602 Blackfin 300MHz

31,505 Blackfin 750MHz

41,025 FPGA + Impulse C 50MHz

205,125 *KaiSemi ASIC1 250Mhz 0.13um

369,225 *KaiSemi ASIC2 450Mhz 0.09um

Performance comparing example:Performance comparing example:JPEG Encoder Case StudyJPEG Encoder Case Study

CostMMAC/s

MMAC/s Num of Multipliers

Device6.4 4,000 4 TI DSP 1GHz3.3 1,200 4 TI DSP 300MHz0.8 7,000 28 ECP-DSP20

250MHz0.024 119,000 476 *KaiSemi ASIC1

250MHz0.027 214,200 476 *KaiSemi ASIC2450MHz

Performance per Cost comparingPerformance per Cost comparing

* Estimated performance based ASIC frequency speedup

* Estimated performance/cost based ASIC area parallelism

www.latticesemi.com/lit/docs/generalinfo/

www.gmvhdl.com/fpga_for_dsp.htmlLink:Link:

Link:Link:
http://www.latticesemi.com/lit/docs/generalinfo/ecp_whitepaper.pdfhttp://www.gmvhdl.com/fpga_for_dsp.htmlhttp://www.gmvhdl.com/fpga_for_dsp.htmlhttp://www.latticesemi.com/lit/docs/generalinfo/ecp_whitepaper.pdf


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hank Youhank You

Documents

KaiSemi - FPGA to ASIC, ASIC to ASIC, DSP to ASIC CONVERSIONs