Transient analysis of submicron CMOS latchup with a physical criterion

Pergamon Solid-State Electronics Vol. 37, No. 2, pp. 255-273, 1994

Copyright © 1994 Elsevier Science Ltd Printed in Great Britain. All rights reserved

0038-1101/94 $6.00 + 0.00

TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION

MING-Dou KER and CHUNG-Yu W u Integrated Circuits and Systems Laboratory, Institute of Electronics and Department of Electronics

Engineering, National Chiao-Tung University, Room 307, Engineering Building 4th, 1001 Ta-Hsueh Road, Hsin-Chu, Taiwan 300, Republic of China

(Received 3 June 1993; in revised form 6 August 1993)

Abstraet--A new physical criterion and an analytical timing model for transient latchup in a p-n-p-n structure are developed and verified. In the new physical transient latchup criterion, two new parameters called the large-signal transient current gains of the parasitic vertical and lateral BJTs in the p-n-p-n structure are defined. If their product rather than the forward beta-gain product becomes larger than unity right after triggering and remains larger than unity, the latchup occurs. With the piecewise-linearized device currents of the parasitic BJTs and the averaged junction depletion and diffusion capacitances in the p-n-p-n structure, the large-signal transient current gains are derived as functions of time and device parameters. Moreover, the dynamic behaviors and the associated timing of transient latchup can also be fully characterized. Model calculation results using the developed criterion and timing model agree very well with both SPICE simulation and experimental results. Thus the developed criterion and timing model can be applied to transient latchup analysis and prediction in CMOS ICs.

l. INTRODUCTION

As the device dimensions are scaled to the submicron range, iatchup becomes a more serious problem to be solved. Latchup, which creates a low impedance path in the inherent parasitic p - n - p - n structure from the power supply VDD to ground, is one of the major failure mechanisms of bulk CMOS ICs. Thus latchup characterization and prevention are important issues in developing submicron CMOS technology.

Since latchup is mostly triggered in the dynamic mode, transient latchup and its mechanism have attracted much attention recently[I-15]. Some efforts have been contributed to characterize transient latchup[1-9], including using 2-D numerical simulations[10-15]. However, a good criterion for transient latchup is required so that it can be used with the accurate characterization models to judge whether the p - n - p - n structure is triggered into its latchup state. Otherwise, extensive trial-and-error steps are required, which may consume too much computing resource.

A criterion for transient latchup initiated by current pulses has been proposed[8]. In that criterion, a quantitative change of charges stored in the junction capacitances of the p - n - p - n structure was selected to predict the occurrence of latchup. It was found that the change of charges remains unchanged when the p - n - p - n structure is triggered into latchup by different pulse currents. The constant change of charges can only be obtained empirically from the trial-and- error SPICE simulations and used as a criterion to judge the occurrence of latchup triggered by different pulse currents. The reason why the change of charges

at the base nodes of a p - n - p - n structure keeps constant when it is triggered into latchup is still not clear. Thus an explicit formula for the change of charges and the criterion cannot be obtained. This not only complicates the numerical calculation but blocks the physical understanding on the mechanism of transient latchup, although the criterion can accurately predict the required current pulse to trigger latchup.

In our work, the dynamic mechanism of transient latchup is explored and a general physical criterion is developed[16]. As compared to the previous criterion, this new criterion has an explicit formula which is associated with both device parameters and circuit parameters of the p - n - p - n structure. The criterion can also provide a clear understanding of the mechanism of transient latchup. Thus it is called a physical criterion. Based upon the developed criterion, the time and the magnitude of trigger sources required to cause a iatchup in any p - n - p - n structure can be accurately calculated through a timing model without any trial-and-error process. Using the definition in the previous work[8], the change of charges at the base nodes of a p - n - p - n structure can be directly calculated from the new developed criterion and timing model. Our criterion is general because it can be applied to various triggering cases and to analytical and numerical analyses.

In order to enhance the physical understanding of the latchup transition, a rigorously simplified quasi- analytical timing model was developed. It is based upon the physical criterion[16] and the classical two- transistor model of a p - n - p - n structure[I-8] with the

255

256 MING-Dou KER and CHUNG-Yu WU

device parameters extracted from the fabricated p - n - p - n structure in CMOS ICs. With the physical criterion and the exactly extracted device parameters including the current-dependent beta gain, the voltage-dependent junction capacitances, and the transit time (calculated from the measured unity-gain frequency), the developed timing model can provide a reasonably accurate characterization on the transient latchup parameters.

The dynamic behaviors of transient latchup in a p - n - p - n structure are analyzed and the large-signal transient current gains are defined and derived in Section 2. From the theoretical analysis of the current iDD which flows out from the voltage supply VDD source and the verification of SPICE simulated waveforms, a physical criterion for transient latchup which is related to the product of large-signal transient current gains is proposed[16]. With the piecewise-linearized bipolar junction transistor (BJT) currents and the averaged junction capacitances, a timing model of transient latchup is developed in Section 3. Using the timing model and the physical criterion, the relations

between the minimum pulse width and the magnitude of pulse-type trigger currents for transient latchup initiation can be directly calculated. Comparisons of theoretical calculations results with both SPICE simulated and experimental results are given in Sec- tion 4. Good agreement among these results confirms the validity of the proposed latchup criterion and timing model. Finally, a conclusion is given in Section 5.

2. TRANSIENT LATCHUP CRITERION

To simplify the analysis and get a physical insight into the dynamic mechanism, transient latchup is characterized by the traditional two-transistor model [1-8]. Figure l(a) shows the cross-sectional view of a CMOS inverter and its parasitic p - n - p - n latching path in p-well n-substrate CMOS technology. The corresponding lumped two-transistor equivalent circuit is shown in Fig. l(b), where Q 1 is the parasitic lateral p - n - p transistor and Q2 is the parasitic vertical n - p - n transistor. The Q I transistor is

Vin (a) VDD / GND

! I V : o u t ~ ~

-1- CC2 Latching path N-SUBSTRATE

(b)

11(,

VDD

- oo I

RS < > ~ > I - - I

"> I I eel -L VEB 1 I '.: is~ ~ K ' C2 I I - -

Ic2 'r cc l l i Q2L'~ IB2 iB2I C1 ~VB-~E: :Ce2: lw

...I_

I2

Fig. 1. (a) The cross-sectional view of a CMOS inverter and the parasitic resistances and capacitances of a p - n - p - n structure; (b) the lumped equivalent circuit of the p n - p - n structure in (a).

Analysis of CMOS latchup 257

Table 1. The current equations of the BJT used in SPICE[18]

The modified GummeI-Poon model in forward active region

1. Base current:

Is • (e vuE/v 'rNF - - 1) + ISE" (e vaE/Er NE -- I)

+ I S ' (eV~C/VT ~R _ 1) + ISC' (e V~C/VT ~C __ I). P~

2. Collector current:

l c = I s . (eVaE/vx • Nv _ e V ~ / V T Na) q~

- i s " ( e v " ~ ' ~ ~" - ~) - l s c " ( ev"c 'v~ u~ _ 1). P,

3. Emitter current:

where

q~ q~=~--[1 +(1 + 4 - q z ) °'s]

1 q~

1 Vac VaE v ~ V~R

Is (e vBE/vT'NF- 1 ) + Is • (e v~lvv N e - 1) q: = / rE" I ~

VT(thermal voltage)= k • T / q .

composed of p ÷ diffusion as emitter, n-substrate as base, and p-well as its collector. The Q 2 transistor is composed of n-substrate as collector, p-well as base, and n ÷ diffusion in p-well as its emitter. The intercon- nected bases and collectors of the transistors Q 1 and Q2 form a silicon controlled rectifier (SCR) circuit. Rs and R w represent the inherent substrate and well shunt resistances across the base-emitter junctions of the transistors Q 1 and Q2, respectively. Ce 1, Cc 1, Ce2, and Cc2 in Fig. l(a,b) are the bias-dependent junction capacitances. In the equivalent circuit, I~ (I 2) is the external trigger current in the n-substrate (p-well).

Taking the effects of junction depletion and diffusion capacitances into considerations and using the modified Gummel-Poon model of BJTs in SPICE [17,18], the base-emitter voltages VEB 1 (t) and VBE2(t) in Fig. l(b) can be expressed as:

~VEa~ (t)

0t

Iw " ( C c l + Cc2 + Ce2) - I F 2 " ( C c l + Cc2) - - ( l )

A C

0UBE2(/)

Ot

IF2" ( C c l + Cc2 + Ce l) - IF1 " (Cc l + Cc2) (2)

A c

where

A c = (Cc I + C c 2 ) . (Ce 1 + Ce2) + Ce 1 • Ce2

IF1 = Ic2 -- IBI VEal - - ~ - + / ,

IF~ -- I a - - I B2 - - VBE2 + / 2 - R w

(3)

(4)

(5)

The detailed derivation of the above equations is given in Appendix A with a reasonable assumption of "0(Cj- vj)/Ot ~ Cj. (Ovj/dt)", where the Cj and vj represent the capacitance and its voltage bias of each junction in the p - n - p - n structure. IBl, IB2, ICj, and Ic2 in (4) and (5) are the intrinsic base and collector currents of the BJTs Q 1 and Q2, respectively. These currents are exponential functions of the BJT termi- nal voltages as shown in Table 1. The Cel(2) and Cc1(2) in (1)-(3) are the base-emitter and base- collector junction capacitances of Q 1 (2), respectively. All these capacitances are dependent upon their junction voltages as shown in Table 2. Thus, VEal(t) and VBE2(t ) are nonlinear differential equations of time, trigger currents, and device parameters of the BJTs QI and Q2 in the p - n - p - n structure. These equations can only be solved by intricate numerical methods. The time-varying VEB~ (t) and VEa2(t ) a r e the basically dominant factors in the lumped equivalent circuit and can be used to model the latchup transition in Section 3.

To develop the transient latchup criterion, new transient parameters called the time-dependent large- signal transient current gains f l l t r ( t ) a n d fl2tr(t) of the transistors Q 1 and Q2, respectively, are defined from

Table 2. The equations of junction diffusion and depletion capacitances of a BJT used in SPICE[18]

I. The junction diffusion capacitances: C ~ and C ~

O(IBE/qb) C ~ = r F for forward-biased base-emitter junction;

aVBE a(~)

C ~ = zrt" ~ for reverse-biased base-collector junction,

where I B E = I s ' ( e v B E w r u F - I) for VBE>0

IBC = Is " (e v~c/vT Ne - l ) for VBC<0

qb has been listed in Table I.

2. The junction depletion capacitances: Cjb~ and Cj~

CJ¢° for VBE < F C • 40 E, c,~, [,_ v.q-~ O~J

q°° [ Cj~ [1 F C ] ( . . . . )" 1--FC'(I +mE)+mE " VBE1

- - ~EJ for VBE >>. F C " doE;

and

cj~ CJ~° for VBc < F C . (b c , [1 - v~l '~

~cJ

CJ¢° " [ 1 - F c ' ( l + m c ) + c q~c] Cj~: = [1 - F C ] 0 + me] m " V a c

for Vac t> F C . go c .

where

C~ = zero-biased base-emitter junction capacitance;

Cj: 0 = zero-biased base-collector junction capacitance;

mE and m c = 0.5 for abrupt junction;

m E and m c = 1/3 for grading junction;

F C = 0.5 (default);

4~e = base-emitter built-in potential (0.75 V, default);

~c ~ base-collector built-in potential (0.75 V, default).

258 M1NG-DOu KER and CHUNG-Yu WU

the large-signal base and collector currents which include the transient currents of junction capacitances, flltr(/) and fl2,r(t) can be written as:

= icl (t____~) f l l t~( / ) - iBl ( t ) (6)

ic2(t) fl2tr(/) -'~ ~ . (7)

Using the relations of (1)-(5) and (AI)-(A11), flltr(/) and fl2~r(t) can be derived as:

flltr(/)

Ac ' Ic l - - IF l " Ccl • Ce2 - - IF2" Cc l " C e l

Ac • I al + I H • (A c - Cc2" Ce2) - I F 2 " Ce 1 . Cc2

Ac' ~ 2 - ~ 2 " C c 2 " C e l - ~ 1 " C c 2 " C e 2

(8)

Ac' /B2 "-F IF2' (A C -- Cc l • Ce l ) - I F : . Ce 2 " Cc l "

(9) Note that flltr(t) and fl2tr(t) are heavily dependent upon the junction capacitances of Q 1 and Q 2. In the d.c. case, they reduce to the forward beta gains. The product of flltr(t) and fl2tr(t) is an important parameter to judge the transient latchup occurrence as will be described later.

Based upon the definition of flltr(t ) and fl2tr (t) in (6) and (7), respectively, the instantaneous current iDD flowing out from the voltage source VDD right after the current triggering can be derived by taking all the transient currents in the device capacitances into considerations and expressed as:

the latchup case maintains at about 0.8 (0.85)V after the pulse-type current triggering, whereas those in the non-latchup case drop to 0 V. Figure 2(b) shows the product of the forward beta gains during the transient operation. The forward beta gain is defined as the ratio of the collector current over its corresponding base current without including the transient currents in the device capacitances of a p - n - p - n structure. Although the forward beta current-gain product in the non-latchup case is even as high as about 206 after triggering, it still does not cause latchup. On the other hand, the curves in Fig. 2(c) show the product of the large-signal transient current gains, which first raises to be above unity and then maintains at 1.431 in the latchup case. In the non-latchup case, the product drops to be below unity fight after the pulse-type current triggering. This exactly coincides with the theoretical prediction from (10). Note that the transient currents of the junction capacitances make the product of the forward beta current gains very different from that of the large-signal transient current gains. The corresponding iDD waveform is also shown in Fig. 2(d). It is found that iDD maintains at about 9.3 mA in the latchup case but drops to zero in the non-latchup case. All of the device parameters used in the SPICE simulations are listed in Table 3.

From the above analysis, the transient latchup criterion can be described as:

The p - n - p - n structure can be triggered to cause a transient latchup if and only if the product of the large-signal transient current gains (not the forward beta gains) of the para-

iDD flltr" fl2tr' (VBE2/Rw -F /)EBI/Rs) -'~ fl2tr "(UBE2/Rw) "F flltr" (UEBI/Rs)

/3,,~ • fl2t~ - 1 (lO)

Note that this/DD also varies with time because fl,r (t), fl2tr(t), VEBI(t), and VBE2(t) are all functions of time during the latchup transition. But, the VEBI(t) and VBE2(t) will hold about 0.8-0.9 V if both Q 1 and Q2 are turned on in the p - n - p - n structure. Thus VBE2/Rw and VEBI/Rs are of some finite values. If 0 < flltr" fl2tr ~( 1 in (10), iDD has a negative value which means that transient current would flow into VDD. But this condition is impossible from the circuit operation and it implies that the degenerative process occurs and latchup is not sustained. This is the state without latchup. If flltr' fl2tr ~ 1, /DO is positive which means the current flows out from VDD after current triggering and the regeneration process starts to sustain latchup. This is the latchup state.

The above latchup judgment has been verified by many SPICE simulation results. One of the typical SPICE simulated waveforms in both latchup and non-latchup cases are shown in Fig. 2(a--d) for different trigger-current pulse widths and Rs ( R w ) = 800 (5600)0. It is clear from Fig. 2(a) that VEB1 (VBE2) in

sitic n - p - n and p - n - p BJTs becomes larger than unity fight after the triggering and remains larger than unity.

This criterion is general and very useful in either analytical or numerical transient latchup analyses under the triggering of various sources. In this work, the criterion will be applied in the analytical modeling of transient latchup.

3. PHYSICAL TIMING MODEL OF TRANSIENT LATCHUP

The dominant factors in the lumped equivalent circuit of a p - n - p - n structure are the base-emitter voltages v~B l (t) and VBE2(t). This is because both base and collector currents as well as the emitter junction capacitances of the BJTs Q 1 and Q2 are basically functions of their base--emitter voltages. If both VEB ~ (t) and VBE2(/) can be found, not only each branch current or node voltage in the lumped equivalent circuit can be directly calculated by the equations


listed in Tables 1 and 2 and Appendix A, but the large-signal transient current gains flltr(t) and fl2tr(t) can also be found. Then the above proposed criterion can be used to judge whether the latchup is initiated in a p - n - p - n structure. Unfortunately, the base- emitter voltages /)EBI(t) and /)BE2(t) expressed in (I)-(5) are nonlinear differential equations of time. They can only be solved by intricate numerical methods.

To clearly understand the physical mechanism of transient latchup, analytical solutions of VEal (t) and VBEZ(t ) are presented in this work. This can be

achieved by piecewisely linearizing the BJT currents and approximating the bias-dependent junction capacitances by the averaged values within their operating voltage ranges. The piecewise linearization of intrinsic collector and emitter currents of BJTs are derived in Appendix B, whereas the averaged junction capacitances are derived and listed in Table 7. By using the method of piecewise linearization in Appen- dix B, the intrinsic base and collector currents can be expressed as linear functions of their base-emitter voltages when the base-emitter voltages are greater than their corresponding turn-on voltage VEBIo . and

(a)

A

>

G) O)

m

O >

,m

E ILl &

m

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4 0

J~ VEB1 Q

,,.'-;="-i.-...° . . . . . . . . . ' V . . . . " - . . , L up C a s e azcn

/ ' ~ ~, " ' - . / ~ ', -....

/ .E2 ',,. "...,

' x x ~ ", Non-Latchup " " " "

/ - - H ' ~ ~ - - ~ 2 n S . Case ~..~..

/ ........ I1 pulse width = 7 nS. / ~ I1 pulse width = 10 nS.

/ . . . . . . . I1 pulse width = 7 nS. Triggered by I1 = 5 mA, 12 = 0. I I l , I

1 0 2 0 3 0 4 0

TIME (nS)

(b) "~ 30

"O 9 25

O. c ~ 2O o 2. ¢" 15 P I.-

0 10

!I1 5 "0

L .

m o

O ii -5 0

<

300 I1 pulse width = 10 nS. ]

I q .......... I1 pulse width = 7 nS.

Triggered by I1= 5 mA, 12= 0. , ' °

, / ~ ; <---Non-Latchup case

/ ~ ~ 1.168 i

,,,c,u, c.,o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . o

I , i i , u , -50 10 20 30 40 50

TIME (nS)

250

2O0

150

100

50

Fig. 2(a, b). Caption overleaf.

260 MING-DOu KER and CHUNG-Yu Wu

(c)

c-

O t-

O

¢n'o c o

e-

10

8

6

4

2

0

-2

-4

-6

-8

-10 0

" . I

I | I

n I I ' \

i] =lJ , I l l k t I l l

1111 I i i i laid II i I II d I

2O

La tchup case

1.431

0 ,185

Non-La tchup case

Tr iggered by I1 = 5mA, 12 = 0.

'. I1 pu lse w id th = 10 nS.

. . . . I1 pu lse w id th = 7 nS.

I = I

30 40 50

TIME (nS)

(d) 10

E £3 E3

4

0 0

l p _ W . h = O S I .......... I1 pu lse w id th = 7 nS. J / I" . . . . . . '

Triggered by I1 = 5 mA, 12 = 0.

a tchup case

Non-La tchup case

. /

10 20 3O 4O

TIME (nS)

Fig. 2. (a) The typical SPICE simulated VEB I (t) and VBE2(1) waveforms of the p-n-p-n structure with Rs = 800 f4 and Rw = 5.6 kf~ in both latchup and non-latchup cases; (b) the product of the forward beta gains as a function of time in latchup (solid line) and non-latchup (dashed line) cases corresponding to the curves in (a); (c) the product of large-signal transient current gains as a function of time in latchup (solid line) and non-latchup (dashed line) cases as derived from the curves in (a); (d) the iDD waveform as a function of time in latchup (solid line) and non-latchup (dashed line) cases corresponding to those in (a).

VBE2o n. The intrinsic base and collector currents are set to zero when the base--emitter voltages are less than their turn-on voltages.

3.1. The four operating modes o f a p - n - p - n structure

Based upon the ON and O F F operations of the BJTs Q 1 and Q 2, there are four operating modes in

the lumped equivalent circuit of a p - n - p - n structure during latchup transition. The BJTs Q1 and Q2 are initially in their O F F states before the external trigger sources are applied. When the external trigger sources which are the pulse-type current sources I~ and 12 are applied to the structure, the BJTs QI and Q2 first remain off and the junction capacitances are charged

Analysis of CMOS latchup

Table 3. Device parameters of the parasitic BJTs in a p-n-p-n structure used in the theoretical calculations

Qj (p-n-p) Q2 (n-p-n ) Parameter Lateral BJT Vertical BJT

fie 1.104 277.2 fla 0.2 2.0 Is(A ) 2.833E- 16 8.112E- 16 IKF(A) 6.909E - 5 4.867E - 4 IsE(A) 4.250E- 14 1.217E- 13 zr(nS) 20 0.25 zR(nS ) 10 2.0 Ck,0 (pF) 2.0 0.6 C#(pF) 0.6 1.3

by the external trigger sources so that the base- emitter voltages arise as functions of time. When the base--emitter voltage VEa I (t) [or VBE 2 ( t ) ] raises up to be greater than its turn-on voltage, Q l (or Q2) is driven into its ON state and the circuit operation is changed to the next mode. Due to the different turn-on speed of Q 1 and Q2, the circuit has two different operation modes in which Q 1 is first turned on with Q2 off or Q2 is first turned on with Q l off. Finally, with the continuous and enough supply of external trigger sources, both Q I and Q2 can be turned on and the circuit operation is changed to the last mode. In that mode, the above developed new criterion is used to judge the occurrence of latchup, and the required minimum pulse width (time) and magnitude of the pulse-type current source I 1 or I 2 can be easily calculated. If the p - n - p - n structure remains in its latchup state after the external trigger sources die out, the latchup changes from the transient type to the static type. On the other hand, if the p - n - p - n structure gradually turns off from the transient latchup state after the external trigger sources are removed, it was called the recoverable iatchup[21].

In the following subsections, VEa I (t) and VBE 2 ( t ) will be solved in the four operating modes.

3.1.1. Mode 1: (QI and Q2off) . In this mode, the base and collector currents are zero since the BJTs Q 1 and Q2 are in their O F F states. All the bias-dependent junct ion capacitances are estimated by their averaged values within the operating voltage ranges. With the initial condition, VEa l(0 ) = 0 and VBE2(0 ) = 0, the solutions OfVEB l (t) and VBE2(/) in the Laplace form can be solved from (1)-(5) as:

VE.1 (S)

alo" S + (al0. bll + blo" at2)

S • [S 2 + (all + b , ) " S + (all • bll -- a12- b12)]

VBE2 (S) (11)

bl0 ' S + (bl0" all + al0. b12 )

S " [S 2 + (all + bll)" S + (air • bll -- a12" b12)]"

(12)

261

Then their t ime-domain solutions can be expressed as two-pole functions of time as:

VEBl( t )=Alo+All .e- (P"")+A~2.e -tm2O (13)

VaE2(/) = Bl0 + BI1 "e -(p'1.0 + BI 2 . e-(r~2.0. (14)

All the coefficients (a~j, b v, A~j, and Blj) and the poles (Pls) (J = 0 , 1, 2) in the above equations can be derived in terms of substrate and well resistances, junct ion capacitances, and the magnitudes of trigger sources (I I and I 2). The results are listed in Table 4. In this mode, the p - n - p - n structure has two negative real poles and the base--emitter voltages raise up as time increases. The transistor Q 1 (Q 2) will be turned on when its base-emitter voltage raises up to its turn-on voltage VEalo n (VaE2o.) which can be calculated by using (B9) in Appendix B. The required time period tla (tlb) to turn on the transistor Q 1 (Q2) can be solved from (13) and (14) as:

Ajo + All "e-(P"t'a) + A12"e -(p'vt'')= VEBIo n (15)

B l o + B l l . e (p,,qb)+Bz2. e (p,2-t,b)= VBE2on" (16)

Note that the tla and tlb can be easily solved from (15) and (16) without complicated numerical methods or steps.

The turn-on speed of Q 1 and Q2 can be judged by the solved time variables tla and tlb. If t~a < l ib, Q 1 will turn on before Q2 and the circuit operation enters into the mode 2 when time increases to tla. On the contrary, Q2 will first turn on if fia > tlb and it enters into the mode 3 when time increases to hb. The base-emitter voltages in this mode at the time tla or tlb are the initial conditions of the next mode and they can be calculated from (13) and (14) with the solved tin and tlb. The initial conditions of the next mode can be summarized as:

VEBl(tla) = VEBlon (17)

VBE2(lla) = Bl0 + Bl~ "e (p" t,a) + Bi 2 . e-(Pl2-tla) (18)

for the mode 2, and

VEal ( t lb) = A10 + AH • e -(p' ' ' 'b) + Al2" e -(p'2''~b) (19)

VBE2(/lb) = VBE2on (20)

for the mode 3. 3.1.2. Mode 2: (QI on but Q2 off). In this mode,

the base and collector currents of Q2 are still nearly zero, but those of Q 1 are the linearized functions of its base-emitter voltage. The junction capacitances are averaged over their operating voltage ranges. With the initial conditions of base-emitter voltages in this mode given in (17) and (18), the solutions of VEal(t ) and VBE2(I ) in the Laplace form are:

V m ( S ) =

VBE2 (S) =

S 2" VESl(tta ) + S • [b21 • VEal(tla ) + a22. VaE2(tla ) + a20 ] + (a20. b2 l + a22 • b20)

S • [S 2 + (a21 + b21 ) • S + (a21 • b21 - a22. b22)]

S 2" VlIE2(/Ia ) + S • [a21 • vaE2(tla ) + b22. VEa I (tla) + b20 ] + (b20. a21 + b22 . a20)

S • [S 2 + (a21 + b21)" S + (a21 • b21 - a22" b22)]

(21)

(22)

SSE 37/2--D

2 6 2 M I N G - D o u K E R a n d C H U N G - Y u W U

T a b l e 4. T h e coeff ic ients in the f o u r o p e r a t i o n m o d e s o f the equ iva l en t c i rcui t in Fig . I (b)

M o d e 1 :

Pll

a n d

whe re

(all + bN ) _ [ ( a l I _ b N )2 + 4 . a t 2 . bt2] °5

2

(al , + bl ~ ) + [(a, t _ b~ I )2 + 4 . a12. b,2] °5

2 P12

,41o = at0 • bit + bl o - a12 a N , bll - - a12 • b12

ato "PH - (ato" b~ + b]o. a12 ) All

P,I ' (Pi2 - - P i t )

alo "Pl2 - (alo" bH + b ~ o ' at2) AI2 =

P12" (Pll --P12)

blo ' al l + al o • bt2 BlO =

a , ' b t l - a , 2 • bl2

blo " PH -- (blo" atl + alo" bl2) B]I

P ~ " (PL2 - P , )

blo 'P12 - - (blo" aN + alo" b12) /5'12

P , 2 ( P , , - P , 2 )

Cc 1 + C c 2

a12 A c • R w

C c l + C c 2 + Ce2

a~ A c • Rs

( C c l + C c 2 + C e 2 ) . 1~ - ( C c l + C c 2 ) . 12 t/10

Ac C c l + C c 2

bt2 Ac" Rs

C c l + C c 2 + C e l btl

A c . R w

( C c l + Cc2 + C e l ) . 1 2 - ( C c l + C c 2 ) . l I blo

~C

(a21 + b21 ) _ [(a21 _ b21 )2 + 4 - a22" b22] °5

2

(a2t + b2 t ) + [(a21 _ b21 )2 + 4" a22' b22] °5

2

M o d e 2:

1921

P22 =

a n d

A2o =

whe re

a20" b2t + b20" a22

a21 • b21 -- a22 • b22 1

A2~ = {(P2~ )2. VES~ (tta) _ P2~ " [b2t 'VEnt (/la) + a22" VSE2(lta) + a20] + (a20 'b21 + b20 "a22)} P2 t " (/921 -- P22 )

1 A22 = P22" (/722 --P21 ) {('022)2" rEfit ( t ta) -- P22" [b21 " VEto (t la) + a22' VBE2(/la) + a20] + (a20" b2t +b20" a22 )}

b20 • a21 + a20. b22 B2o =

a2l - b2t - 022 - b22 1

B21 = {(/921 )2. VBE2(lla ) --P21 " [a21 " VsE2(tla)+b22 " VESt (tta) + b2o] + (b2o" a~L + a2o" 322)} P21 " (P21 -- P22)

I B22 = P22' (/922 -- P21 ) {(P22)2 ' VSE2(lla) -- P22" [a21 " VBE2 (tla) + b22' VEBI (/la) + b20] + (b20' 021 + a20' b22)I

C c l + Cc2 a22 = A C " R w

1 a21 = ~ . [(Cc 1 + C c 2 + C e 2 ) " (gin + 1 /Rs) + (Cc 1 + C c 2 ) " gct l

1 a2o = ~ " [(Cc 1 + C c 2 + Ce2) " (11 - Islo) - (Cc I + Cc2)" (12 + Ioo) ]

1 b22 = ~ . [( Cc I + C c 2 + Ce 1) ' g c l + ( Cc I + C c 2 ) . (gst + 1/Rs)]

C c l + C c 2 + C e l bzt =

A c ' Rw

b2o = ~_1. [ (Cc l + C c 2 + Ce 1)" (12 + / o o ) - ( Cc I + Cc2)" ( I I - lnl0)] a c

continued

Analysis o f C M O S latchup 263

T a b l e 4--continued

M o d e 3:

1932

a n d

/13o

A31

whe re

(a3~ + b~ ) - [(a~l - b~ )2 + 4" a32" b37] °5

2

(a~t + b3~) + [(a~t - b31) 2 + 4 . a32. b32] 05

2

a3o" bat + b3o" aa2

a31 • b31 - t/32 • b32 1

{(P31) 2" VEal(lib) -- P31" [b31" VEal(lib) q- a32" VaE2(llb) 4- a30 ] + (a~o" b~ + b~o" a~2) } P31 " (P31 --P32)

1 A3~ {(P~e)2' ~e~l ( l~) --P3:" [b31 " ~em (tl~) + a~ " ~r~ (gb) + a3o] + (a~o" b~ + b~o " a32)}

p~ . (p~ -- p~ )

b30 • a31 -b a30 - b32 B30

a31 • b31 - a32 • b32 1

B31 {(P31 )2, VaE2(/Ib ) _ P31" [a31" VlaE2(/Ib) + b32" Vra~ (lib) + b~o] + (b~o" a~ + a~o, b~2) } P31 " (/931 -- P32)

1 B32 {(P32) 2" /~aEZ (lib) --P32" [a3l " va~2(tlb) + b32" VEal (rib) + 6301 + (b3o" a31 + a3o" b~2)}

P32" (/032 - P ~ )

1 a~2 = A~. [(Ccl + Cc2 + Ce2) " gcz + (Ccl + Cc2)'(g~2 + l/Rw)]

C c l + C c 2 + C e 2

a~ A c • Rs

1 aso = ~ " [(Cc 1 + C c 2 + Ce2)" (I t + 1c2o) - (Cc I + Cc2)" (12 - / a 2 o ) ]

Cc I + Cc 2 b32

Ac" Rs

b~ = 1 c • [(Cc 1 + Cc2 + Ce 1)- (ga2 + l /Rw) + (Co I + Cc2)" gc2]

b~o = 1_. [(Cc I + Cc2 + Ce 1) ' (/2 - la:o) - (Co I + Cc2)" (I~ + lczo)] a c

M o d e 4:

P41

P~2

a n d

A~o

A41

,442

where

(a41 q_ b41 ) _ [(a4 t _ b41 )2 + 4 ' a42" b42] °5

2

(a4~ + b4~) + [(a4~ - b J ~ + 4 ' a42' b~2] °~

2

a4o- 541 + b ~ ' a42

a4~ • b4~ -- a42 • b42 1

• {(p,~ )2. vE~ (t2) - p4~ "[b4, ' ven~ (t2) + a42' vBe:(t2) + a ~ ] + ( a ~ - b4~ + b~" a~2)} P4t " (P4~ - P 4 2 )

1 • {(P42) 2" blEBI (/2) -- P42' [b41 ' UEBI (i'2) q- R42" t~BE2(/2) -]I a4o] -~- (a4o" b41-1- b4o" a42)}

P42 (P42 - P4~ ) b40" a,u + aao • b,,2

a4t " b4~ - a,~2 • b42

• {(P,~I )2. VaE:~(t2 ) _ P.~I ' [a41" VB~2 (t2) + b42" v~al (t2) + b~] + (b,~. a4r 4- a ~ . b,~2) } ]741 " (Pal --P~2)

I • {(P4~): ' Vae:(t2) --P42" [a , l" Vae2(t2) + b ,2 ' vea l ( t : ) + b~o] + (b~o'a~ + a~o" b42)}

p ~ : ' (P~: - p~ )

I a42 = Ac " [( Cc 1 + Cc2 + Ce 2) . g¢2 + ( Cc 1 + Cc2)" (gB2 + l /Rw) ]

A--~. [ ( C c l + Cc2 + Ce2) . (gal + l /Rs ) + ( C c l + Cc2) m g C I ~ £/41

= ~ " [(Cc 1 + CC2 + Ce2)" (11 + 1c2o - Islo) - (Cc I + Cc2)" (12 a4o + Ic,o 11120)] i

I b42 = ~ " [(Cc I + Cc2 + Ce 1) ' g c l + (Cc I + Cc2)" (gat + l/Rs)]

b4t = ~c" [(Cc I + Cc 2 + Cel )" (gs2 + 1/Rw) + (Cc] + Cc2) I

1 b4o = ~ - " [( Cc 1 + Cc2 + Ce 1). (12 +Ic t o - la2o ) - (Co I + C c 2 ) , (11 + Ic2o - lalo)]

,a c

264 MING-DOU KER a n d CHUNG-Yu WU

The corresponding time-domain solutions are:

VEto ( t) = A2o + A:j • e -(p2~ ~) + A22. e -tp22 .o (23)

UBE 2 ( t ) = B20 + B21 "e- ~02, t) + B22 . e - e22 o. (24)

The coefficients and the poles in (21) (24) are also listed in Table 4. With the negative real poles -P2~ and -P2 : , these base-emitter voltages also monotonically increase as time increases. The required time period t2u to turn on Q2 can be easily obtained by solving the following equation:

B20 q- B21 . e tp~' ' ~ + B22" e -(p22" t2b) ~ VBE2o n . (25)

When Q2 is turned on after Q 1, the circuit operation enters into the mode 4. The base-emitter voltages in this mode at the time t2b are the initial conditions of the mode 4 and they are:

VEBI(t2b) : Az0 + A21 " e (p2, '~2b) + A22 . e-(P22.t2,) (26)

V~Ez(tzb) = VBE2o,. (27)

3.1.3. M o d e 3 : ( Q 2 on but Q I off) . Similar to the mode 2, the base and collector currents of Q 1 in this mode are still zero, but those of Q2 are the linearized functions of its base-emitter voltage. The veto (t) and VBEE(t) can be similarly solved with their coefficients and poles listed in Table 4. The required time period tz, to turn on Q 1 can be easily obtained. The initial conditions for the mode 4 can be determined similarly as those in the mode 2.

3.1.4. M o d e 4: (Both Q I and Q 2 have been turned on). In this mode, the base and collector currents of Q1 and Q2 are the linearized functions of their base-emitter voltages. The junct ion capacitances are also averaged over their operating voltage ranges. To conveniently express the initial conditions, the nota- tions VEBI(/2) and UBE2(t2) a r e used to generally represent these initial conditions from the modes 2 and 3. Then, the solutions of the base-emitter voltages in the Laplace form are:

structure can be quickly triggered into its latchup state.

3.2. The required m in imum time to init iate latchup

With the above solved VEto(t) and VBE2(t) in each operation mode, all the node voltages and branch currents in the equivalent circuit shown in Fig. l(b) can be calculated and the dynamic behaviors of a p - n - p - n structure as functions of time due to external currents triggering can be fully characterized. Then, the product t i m ( t ) " fl2tr(/) can be obtained and the physical criterion can be used to determine whether the transient latchup occurs in a p - n - p - n structure. Because either Q1 or Q2 is off in the piecewise-linearized operation modes 1-3, the latchup does not occur in these modes. The product of the large-signal transient current gains in the modes 1-3 may have a value due to the transient currents in the device capacitances but it is near zero as shown in Fig. 2(c) before the occurrence of latchup. When the circuit operation enters into the mode 4, the product of large-signal current gains arises from zero as time increases and the p - n - p - n structure becomes latchup when f l l t r ( t ) ' f l 2 t r ( t )= 1. When fll ,r(t)" fl2~r(t) > 1, the p - n - p - n structure has been in its latchup state.

Substituting the piecewisely linearized base and collector currents derived in Appendix B with the solved base-emitter voltages expressed in (30) and (31) into (8) and (9), the time equation of the product of the large-signal current gains can be obtained and the time period in the mode 4 corresponding to f l l t r ( / ) " f l 2 t r ( / ) = 1 can be solved from the relation:

l 0 + l I • e (p4, ,) + 12" e (p,2. ,) + 13. e-Ii p,, +,~)-,1

+ 1 4 . e - 1 2 " ' ~ + / s . e ~2" ' 2 °=0 . (32)

The coefficients lo-15 are derived in terms of device parameters of a p - n - p - n structure and the magni-

VEto (S) =

VBE2(S) =

S 2" veto (t2) + S • [b41 - t)EB 1 (t2) + a42" VBE2(t2) -k- a40 ] q- (a40" b41 q'- a42" b40)

S • [S 2 q- (a41 q- b 4 1 ) ' S -t- (a41 ' b41 - a42" b42)]

S 2" OBE2(t2) q- S • [a41 " VBE2(I2) "+- b42" VEBI ( t2) n t- b4o] + (b40" a41 q- b42" a40)

S • [ S 2 -t- (a41 -]- b41 ) " S -1- (a41 • b41 - a42" b42)]

(28)

(29)

The corresponding time-domain solutions are:

V E m ( t ) = A 4 o + A 4 1 . e (p41.0_I_A42. e (p42-t) (30)

VaE2(t) = B40 + B41 "e -(p4* t) + B42' e -Cp"2 ~). (31)

The coefficients and the poles in (28)-(31) are also listed in Table 4. The pole -P42 is a negative real pole whereas -P4~ is a positive real pole due to the positive-feedback regeneration process in the p - n - p - n structure. It is interesting to note that only this mode of operation has a positive pole which leads to the rapid positive regeneration in both base and collector currents of Q 1 and Q 2, so that the p - n - p - n

tudes of the external trigger current sources. The expression of lo-15 are summarized in Table 5.

From the equations of the time periods in each mode, the minimum required pulse width to initiate transient latchup can be calculated. For example, if only 11 is applied and 12 = 0, the transistor Q 1 is first turned on and then Q2 is turned on later. The corresponding circuit operation mode is from the mode 1, through the mode 2, and then to the mode 4. Therefore, the required minimum pulse width of I~ to initiate latchup can be calculated as:

tmin,ll = tl. + t2u + t3a, (33)

Analysis of CMOS latchup

T a b l e 5. T h e coeff ic ients o f the e q u a t i o n (32)

lo = kl " A4o + k2 " B4o + k3 " A ~ + k4 " B ~ + ks " A4o " B4o

I I = k ] . A41 + k 2 - B4] + 2 • k 3 • A40 ' A41 + 2 • k 4 . B40" B41 "[- k s . (A40" B41 + B40" A41 )

l 2 = k t - A42 + k 2 . B42 + 2 • k3 ' A4o" A42 + 2 . k 4 - B4o" B42 + k5. (A4o" B42 + B4o" A42)

13 = 2 ' k 3 . A41 " A42 + 2" k 4 " B41 " B42 d- k 5 " (A41 " B42 + B41 ' A42 )

14 = k 3. A~t + k 4. B~, + k 5. A41 • B41

whe re

(A c - Cc I . Ce 1). lcto + Cc I . Ce I . ls20 + Cc I . C e 2 . (IBi 0 - Ic20) k~ Rs

(A c - Cc2" C e 2 ) - Ic2 o + C c 2 " Ce2" IBi o + C c 2 ' Cel " (IB20 - lcl0) k2 R w

C c l . C e 2 g c ] . ( A c - C c l . C e l ) + g s i . C c l . C e 2 k3 Rs 2 + Rs

C c 2 . C e l g c 2 " ( A c - C c 2 " C e 2 ) + g a 2 " C c 2 " C e l k4 = ~ + R w

gBI " C c 2 • C e 2 - g c ] " Cc2 • Ce I ga~" Cc I • Ce I - g c 2 " Cc I • Ce2 ks R w ÷ Rs

C c l . C e 2 + C c 2 . CeI + C e l . Ce2

R s . R w

265

where t3a is the time period when the f l l t r ( t ) " f l 2 t r ( t )

product raises up to be equal to unity after the circuit operation enters the mode 4. The t3a can be solved from (32). The time periods tla and t2b have been solved in the modes 1 and 2, respectively. For 12 triggering, similar relation of the minimum pulse width t~,.t2 as (33) to initiate latchup can be found with the circuit operation of mode 1-,mode 3-~mode 4.

Certainly, when both I I and 12 are applied simul- taneously, the required minimum pulse width to induce transient latchup can also be found similarly by using the proposed criterion and analytical timing model. Depending on the turn-on speed of each transistor, the sequence of the operation modes could be 1 ~ 2 ~ 4 or 1-~3-~4.

3.3. The minimum pulse height o f trigger currents to induce latchup

If the applied external currents are not large enough, the p - n - p - n structure can not be turned on even though the trigger time is very long. Thus the structure can never be triggered into the latchup state. The minimum required pulse height of external trigger currents can also be found through the above described timing model.

For I] triggering (12 = 0 ) , Q2 will be turned on after Q 1 does and then the p - n - p - n structure could be triggered to transient latchup. If Q2 can not be turned on due to I~ triggering, the latchup state will not occur. In the mode-2 operation where Q l has been turned on but Q2 remains off, the base-emitter voltage of Q2 monotonically raises up to its final value with two negative poles as described in (24). If the final base-emitter voltage of Q2 in the mode 2 is smaller than its turn-on voltage, latchup never oc-

curs. Thus a necessary condition for transient latchup initiation is that the final base--emitter voltage of Q 2 in the mode 2 due to I l triggering must be greater than its turn-on voltage VBE2o . . The final base-emitter voltage of Q2 is the term B20 in (24) with I~ triggering and I z = 0. Substituting the corresponding coefficients into B20, this necessary condition can be written as:

Iclo' (gBl + 1/Rs) +gcl" (II -- IB]o) B2o = >/ VBE2o n .

(g~ + l / m ) . (l/Rw) (34)

From the above equation, the required minimum magnitude of Ii to initiate transient latchup under 12 = 0 can be written as:

llmin = iS lo + (ga l + 1 / R s ) FVBE2on ] gel " l Rw - Ic lo • (35)

Similarly, the minimum pulse height of 12 in the mode 3 to initiate latchup under lj = 0 can be written a s :

12mi n = IB20 q. (gB2 "b 1 / R w ). VVEBIon - - / C 2 0 ] " (36) gcz [_ Rs /

It can be seen from (35) and (36) that smaller Rs and Rw cause larger I ~ , and I2m~n. This means that a p - n - p - n structure with smaller substrate and well resistances has a higher transient latchup immunity against the substrate or well current triggering.

4. R E S U L T S O F M O D E L C A L C U L A T I O N A N D D I S C U S S I O N

4.1. Comparisons with S P I C E simulation results

By using the developed new criterion and timing model, the required minimum pulse widths to initiate latchup with different pulse heights of trigger current

266 MING-DOu KER and CHUNG-Yu Wu

A

c

J~ " O =m

E E

°~ =E

40

30

20

10

O l i Model-Calculated Result SPICE-Simulated Result

Model-Calculated Result SPICE-Simulated Result

Rs = 8 0 0 ~ , Rw = 5 . 6 k ~ .

.o• t r i g g e r i n g -

"9 r ~ I1 triggering ''o..... "c~'"t> .......... "o" ..... 0" .....

. . . . . . . t , . .~ ""0" "O" E~'O'~ • -. • -~L::.~ 1 l O 100

Trigger Current (mA) Fig. 3. The SPICE simulated and the model calculated results of the required minimum pulse width of

the trigger currents to initiate latchup as functions of the pulse current heights.

11 and 12 are calculated and compared to those obtained from SPICE simulations. The results are shown in Fig. 3 where the adopted device parameters of a p - n - p - n structure are listed in Table 3 with the piecewise-linearized currents in Appendix B and the averaged junction capacitances in Table 7. As can be seen from Fig. 3, good agreement is obtained between analytically calculated and SPICE simulated results. It is also found in Fig. 3 that a smaller trigger current requires a longer trigger time to induce latchup, and it never becomes latchup if the pulse width of a trigger current is smaller than the corresponding minimum values tmin,ll (or tmin,i2 ) in (33).

Figure 4(a) and (b) show the variations of the minimum pulse widths tmin,ll and tm~,,n as functions of the substrate and the well resistances, respectively, for 11 = 5 mA or 12 = 0.5 mA triggering. It is noted that the decrease of the substrate or the well resistances increases the values of the required minimum pulse widths of I~ and 12 to initiate transient latchup so that the iatchup immunity is enhanced. Good agreement is also obtained between analytically calculated and SPICE simulated results.

The effect of well-substrate junction capacitance on transient latchup is shown in Fig. 5. The minimum pulse widths of I~ and 12 are linearly proportional to the zero-biased well-substrate capacitance. This is also consistent with the previous results[8]. This result indicates that the larger well-substrate junction capacitance in a p - n - p - n structure leads to a higher transient latchup immunity against well and substrate currents triggering. The larger well-substrate junction capacitance can be achieved by a larger well region.

Figure 6(a) and (b) show the model calculated and SPICE simulated results of the minimum pulse widths

as functions of the forward transit times ZF~ and zF2 of the BJTs Q 1 and Q 2, respectively, with/1 = 5 mA or 12 =0.5 mA triggering. As seen from the first equation in Table 7, the transit time has an important effect on the averaged base-emitter junction diffusion capacitance which is dominant in the total capacitance of the forward-biased base-emitter junction. A larger transit time which may be caused by a wider base width of the parasitic BJTs in a p - n - p - n structure leads to a larger minimum pulse width and thus a higher latchup immunity, as seen in Fig. 6(a,b).

The minimum pulse width as functions of the maximum forward beta gains, flw and fly2, of Q 1 and Q2 with l l - 5 m A or 12=0.5mA are shown in Fig. 7(a) and (b), respectively. As shown in these figures, the minimum pulse widths of well-triggering current /2 and substrate-triggering current Ii have a stronger dependence on the beta gains of Q 1 and Q2 when the beta gains are smaller. But the dependence becomes less when the beta gains are large enough. Smaller beta gains increase the transient latchup immunity as expected.

From the above figures, it can be concluded that the transient latchup immunity can be effectively improved through the increase of the collector junction capacitances of the parasitic transistors. But the immunity can not be strictly improved if Rs (Rw) and flvl (flF2) are large enough or ZFI (ZF2) is small enough.

By using the proposed transient latchup criterion and the latchup timing model, the minimum magnitudes of I1 and I 2 to induce latchup have been derived in (35) and (36), respectively. The model calculated and SPICE simulated results of Ii,.in and I2min are shown in Fig. 8(a,b) with good agreements. As shown in Fig. 8(a,b), smaller substrate and well resistances


lead to larger Ilrni n and I2min' This means that a p - n - p - n structure with smaller substrate and well resistances has a higher transient latchup immunity as expected. The result of Fig. 8(b) also shows that the minimum magnitude of the well-triggering current I s applied to the base of the parasitic n - p - n BJT Q2 is more sensitive to well resistance (dashed line) than substrate resistance (solid line). This implies that decreasing the well resistance has a more signifi-

cant efficiency on the enhancement of transient iatchup immunity than decreasing the substrate resistance.

All the model calculated results with the different variations on device parameters of a p - n - p - n structure have shown good agreements to those of SPICE simulations in the above figures. These substantiate the validity of the proposed new transient latchup criterion and the timing model.

(a) 20

u) c

• , -- 15 J~ "D

E

.~- 5 c

, ~

0 .1

Model-Calculated Result o SPICE-Simulated Result

.......... Model-Calculated Result

SPICE-Simulated Resul t

12 = 0.5mA triggering

o ¢ ...D. ..... O....O..D. ........................... o. .......... i

I1 = 5mA triggering

Rw = 5.6 K ~ . . . . . J i i . . . . . I . . . . . . .

1 10 1 0 0

Substrate Resistance Rs (K~)

(b) 15

¢/) C

J¢: • ~ 10 "o =m

E 5 E

o ~ =E

~ ° " " ' o o 12--0.5mA tr iggering

"- ...... o . . . . o l ~ oo , . o . . . . . , ooo ,~o .oooo° . . . . . . . . . . . . . o ,

11=5mA tr iggering

Model-Calculated Result

[] SPICE-Simulated Result

.......... Model-Calculated Result

o SPICE-Simulated Result R s = 8 0 0 ~

10 100

Well Resistance Rw (k~)

Fig. 4. The SPICE simulated and the model calculated results of the required minimum pulse widths with It = 5 mA or 12 = 0.5 mA triggering as functions of (a) the substrate resistance Rs with a fixed well

resistance Rw = 5.6 kQ; (b) the well resistance Rw with a fixed substrate resistance Rs = 800 fl.

268 MING-Dou KER and CHUNG-Yu WU

50

A

(I) 40 C ¢-

N 3o

~ 20

E

E e- lO

0 0

Model-Calculated Result .¢ r~ SPiCE-Simulated Result ...........

.......... Model-Calculated Result ......... o SPICE-Simulated Result .... P'°"

- - - - .O=°°* °°

,~.*""

12=0.5mA triggering . . . , . . . . c , ' " " ' ~

Cjel0=0.6pF . . . . ° ' I o - ,

2 4 6 8 10

WelI-Substrate Capacitance Cjc0 (pF) ( Cjcl0=Cjc20=Cjc0 )

Figl 5. The SPICE simulated and the model calculated results of the required minimum pulse widths as a function of the zero-biased well-substrate junction capacitance with I~ = 5 mA or I: = 0.5 mA triggering.

4.2. Comparisons with experimental results

To experimentally investigate the dynamic triggering characteristics of transient latchup and verify the developed criterion and model, a p - n - p - n structure with the anode-to-cathode spacing of 35 p m has been fabricated by using a 0.8/~m twin-well n-substrate bulk CMOS technology and measured. The d.c. triggering voltage (current) of the fabricated p - n - p - n structure is 29.8 V (3.06 mA) and the holding voltage

(current) is 1.2 V (4.54 mA). The device parameters of both parasitic lateral p-n -p and the vertical n-p-n BJTs in this experimental test structure has been extracted and listed in Table 6. Although the parasitic vertical n-p-n BJT Q2 has a fly2 as high as 322, its knee current I~F for high-level injection[17-20] is only 0.226 mA which is much smaller than that of a normal BJT.

Figure 9 shows the model calculated and experimentally measured results of the minimum pulse

(a) 12

A

11 ¢..

e- "O

0 . 9

E

E ' ~ 81

7 .1

Model-Calculated Result D SPiCE-Simulated Result . q f

I .......... Model-Calculated Result ~ . " ~ I o SPICE-Simulated Result o /" /

- - o°*° [ ] O , , . - ' ° [ ] / 7

TF2=0.25nS o ..... / / =

O ° ° , , ' ° ' ° ' ~ * ° ° ~ [ ]

. . . . . . . . , , o , , , , * . . . . . . . ° ° , = . . , , o = o = , , O . . , , . . , ° . . . . . . . . . . . . . . . . , , ~ ) , . ° , , ' ° ' " ° = ' ° f O~ 12=0"5mA triggering J [ ]

11=5mA triggering . . . . . . . i . . . . = = i I I . . . . . . .

1 10 100

Forward Transit Time of BJT Q1 (TF1) (nS) Fig. 6(a). Caption on facing page.


(b) 45

4O

U~ ¢= 35 v t--

"O 3O

~ 25

a . 2O

E

E 15 C

10q

Model-Calculated Result

n SPiCE-Simulated Result

/i °

7 .......... Model -Calcu la ted Result

o SPICE-Simulated Result / /

TF1 = 2 0 n S _ o /

. . ~

12=0.5mA tr igger ing ...

~ _ . ,oo ,o ,oOO, ' °y °°" ='(~°°

..... O' ........ O ' " ~ ~ ,.,o.,.,..,°,.~.°,,"°'°" ~. . j~ , . .~-" - - -LI 11=5mA triggering

, , , , , , I 5 .1 1

Forward Transit Time of BJT Q2 (TF2) (nS) Fig. 6. The SPICE simulated and the model calculated results of the required minimum pulse widths with 1~ = 5 mA or 12 = 0.5 mA triggering, Rs = 800 Q, and Rw = 5.6 kf] as functions of (a) the forward transit time of the BJT Q 1 with a fixed 0.25-nS forward transit time of the BJT Q2; (b) the forward transit time

of the BJT Q2 with a fixed 20-nS forward transit time of the BJT Q 1.

widths as functions of the pulse heights of 12 and 12. It is shown that good agreement is obtained between calculated and measured results. This also verifies the exactness of the proposed new physical transient latchup criterion and the timing model.

5. CONCLUSION

A new general and physical criterion for transient latchup has been developed. It is based upon the product of large-signal transient current gains of the parasitic lateral and vertical BJTs in the p - n - p - n

(a) 16

14

C 12

e.-

10

~ 8

D.

E 6

._E 4 C

2

0 0

Model-Calculated Result [] SPICE-Simulated Result

.......... Model -Calcu la ted Result

~ SPiCE-Simulated Resul~

...... D. ......... .Q. ......... D. ......... ,Q~.. ........................ .9. ...........................

\ 12=0.5mA tr igger ing

0, o I1 =5mA triggering

Rs=0.8K.O, Rw=5 .6K f~ B F 2 = 2 7 7 . 2

I I I I i

2 4 6 8

Forward Beta Gain of BJT Q1 (BF1) Fig. 7(a). Caption overleaf.

270 M[NG-DOu KER and Cre, mG-Yu Wu

(b) 13

O"J 12 t - v

"0 11

~ m I1.

E ~ 9 E e-

o ~

~ a

\ o"

b..

[3 , , o ° ° . ° ° ° °

O

Model-Calculated Result SPICE-Simulated Result Model-Calculated Result SPICE-Simulated Result

12 = 0.5mA triggering "D .......... O It. /

" ' ° ° ' " ° ' " " = ' ~ ' " ' " ° ' " ' * ' ° ' " ' " " . . . . . . , ° o , - o * , O , . . . . . , . . . , . . . . . . . . . . . . . . . . . . . . . . . .

[ • I1 = 5mA triggering

..,.._13 FI ....

7 i

50 350 400

RS=0.SKQ, Rw=5.6K~ BF1=1.104

100 150 200 250 300

Forward Beta Gain of BJT Q2 (BF2)

Fig. 7. The SPICE simulated and the model calculated results of the required minimum pulse widths with Ii = 5 mA or Is = 0,5 mA triggering, Rs = 800 f2, and Rw = 5,6 kQ as functions of (a) the forward beta gain of the BJT Q 1 with a fixed/~F2 = 277.2 forward beta gain of the BJT Q2; (b) the forward beta gain

of the BJT Q2 with a fixed ~Ft = 1.104 forward beta gain of the BJT QI.

structure. The large-signal transient current gain is a new parameter which describes the transient current gain of a BJT, taking all the transient currents of the device capacitances into consideration. As the product o f the large-signal transient current gains is equal to or greater than unity right after triggering,

transient latchup occurs. Using the developed criterion and the derived analytical timing model with properly linearized equations, the required minimum pulse width for transient latchup as functions of the pulse heights of the well-triggering or the substrate- triggering currents can be calculated analytically.

(a) 3

,< E

v

e- o w

E m

2:

I . . . . . Model-Calculated Result [~ I [3 SPICE-Simulated Result \ I .......... Model-Calculated Result \ I o spicE-Simulated Resu!t

q ' ~ . 12 i i variation wit h ",. f ixed Rs=0.SK.Q

2' ".'b" °";....,o..od.. " - - x ......... o o o \ .................... °

0 .1

. . . . . ! . . . . . . . . i . . . . . . . .

1 10 100

Well or Substrate Resistance (KD.) Fig. 8(a). Caption on facing page.

(b) 0.3

A

<t E ¢-

E O4 m

0.2

0.1

[ ]

RS variation with

I 1 = 0

, ° . . . . . . . .

O


0o0 , . . . . . . . i

.1 1

Rw variation with fixed Rs=0.8Kfl '¢

fixed Rw=5.6K~ "o

Model-Calculated Resu l t ~"

SP iCE-S imu la ted Resu l t " ' ' . Model-Calculated Result " a . SPICE-S imu la ted Resu l t ""°'"..,o....O.

10 100

Well or Substrate Resistance (K~) Fig. 8. The SPICE simulated and the model calculated results of the minimum trigger currents (a) llmln,

or (b) 12m~n, to induce latchup as functions of the parasitic resistances Rs or Rw.

Both SPICE simulated and experimental results show good agreements to the model calculated results, which substantiate the validity of the proposed new criterion. It can be shown from the above results that larger forward transient times, larger well-substrate junct ion capacitance, smaller well and substrate re-

sistances, smaller forward beta gains, and significant high-level injection effect of the parasitic BJTs lead to a higher transient latchup immunity in a p - n - p - n

structure against well or substrate currents triggering. The developed physical criterion and timing model

for transient latchup are useful and convenient in

1000 I Model-Calculated Result

n Experiment-Measured Result -'-- .... "'"'" Model-Calculated Result 0') o Experiment-Measured Result 800 q t-- N~ o Substrate Resistance : Rs = 4 2 8 Q

- ~ ~ W e l l R e s i s t a n c e : R w = 7 . 9 1 K Q

600 G) [3 ~ I1 triggering

n E 400

12 triggering

E 200 c~....~ . . . .

• , . o , ,

~ ' " " ~ ' " " ~ ' " ' < ~ . - . - o ..... ~> ..... ~ ..... ~ ..... "6" ..... i5" ..... "6" ..... "(3

=E

0 , i I i I , I

7 9 11 13 15 17 9

Trigger Current (mA) Fig. 9. The comparison of the measured and the model calculated results of the minimum pulse widths to initiate latchup as functions of the trigger currents with the substrate resistance 428 D and the well

resistance 7.91 kfl.

272 MING-DOu KEg and CHUNG-Yu WU

Table 6. Device parameters of the parasitic BJTs in the fabricated test structure

Q l(p-n-p) Q2(n-p-n) Parameter Lateral BJT Vertical BJT

fly 0.623 322 fir 0.104 6.5 Is(A ) 8.48E- 18 4.29E- 15 IKv(A) 7.59E - 3 2.26E - 4 Ise(A) 1.166E - 17 4.04E- 14 lsc(A) 5.134E- 15 6.819E- 13 tF(S) 1.05E - 6 1.745E - 7 ta(S) 4.04E - 6 6.57E - 7 C~0(F) 9 E - 13 9 E - 13 C~(F) 8.82E- 14 4.80E- 14 VA~ 40 8.6 FAR 20 2 N F 1.002 1.405 N E 0.989 2.093 N c 1.084 2.674 N R 1.026 1.041 MJE 0.5 0.5 MJC 0.33 0.33

t rans ien t l a t chup analyses wi th any type o f triggering.

The developed physical cr i ter ion can also be appl ied

to the numer ica l t rans ien t l a tchup analysis as well.

Moreove r , the developed cr i ter ion and mode l can be

Table 7. The piecewise-averaged junction capacitances of the parasitic BJTs in a p-n-p-n structure

1. The averaged diffusion capacitance of a forward-biased base-emitter junction over its operating voltage range from VBE ~ to VBE b is:

C,~ ZF- I s [e ~r~Eb/vT u v - 1 e *''E*/Vw N F- I]. v . ~ - v.r~ qb(vsEb) ~ d

2. The averaged diffusion capacitance of a reverse-biased base-collector junction with its operating voltage range from vac~ to Vac b is:

Ct~ "OR" Is l e . . . . . . . . . . e t'BC . . . . . . ]. UBCb - - /)BCa

3. The averaged depletion capacitance of an abrupt base-emitter junction over its operating voltage range from va~ to vBeb is:

- - 2.~b b-Cro - ( 1 VBeb ~/2

when VBE , < VBE b < ~bb/2,

UBEb -- 2-- /)BE

-t 4.(0.5) 3 / ~ " 1 -~

when vaE ~ < <kb/2 < vB[ b,

g~. = ~ . 1 + ¢b J

when VBE b > UBE a > ~bb/2.

4. The averaged depletion capacitance of a reverse-biased grading base-collector junction over its operating voltage range from Vaca to Vncb is:

when Vac b < Vaca < O.

applied to the au tomat i c l a tchup immun i ty checking,

which are requi red in fu ture C M O S VLSI design with

s u b m i c r o n technologies.

Acknowledgement--This work was supported by United Microelectronics Corporation (UMC), Taiwan, R.O.C., under Contract C80029.

REFERENCES

1. R. R. Troutman and H. P. Zappe, IEEE Trans. Electron Devices ED-30, 170 (1983).

2. R. D. Rung and H. Momose, IEEE Trans. Electron Devices ED-30, 1647 (1983).

3. G. J. Hu, IEEE Trans. Electron Devices ED-31, 62 (1984).

4. K. Y. Fu, IEEE Trans. Electron Devices ED-32, 717 (1985).

5. L. Chang and J. Berg, IEEE Trans. Electron Devices ED-33, 165 (1986).

6. G. Goto, H. Takahashi and T. Nakamura, IEEE Trans. Electron Devices ED-33, 1341 (1986).

7. W. Li and M. E. Nokali, Solid-St. Electron. 30, 1331 (1987).

8. Y.-H. Yang and C.-Y. Wu, IEEE Trans. Electron Devices ED-36, 1336 (1989).

9. R. R. Troutman and H. P. Zappe, IEEE Trans. Electron Devices ED-31, 315 (1984).

10. M. R. Pinto and R. W. Dutton, 1EEE Electron Device Lett. EDL-6, 100 (1985).

11. S. Odanaka, M. Wakabayashi and T. Ohzone, IEEE Trans. Electron Devices ED-32, 1334 (1985).

12. J. Harter, H. Jacobs and H. Skapa, IEEE Trans. Electron Devices ED-32, 1665 (1985).

13. E. C. Sangiorgi, M. R. Pinto, S. E. Swirhun and R. W. Dutton, IEEE Trans. Electron Devices ED-32, 2117 (1985).

14. M. Strzempa-Depre, J. Harter, C. Werner, H. Skapa and R. Kassing, IEEE Trans. Electron Devices ED-34, 1290 (1987).

15. T. Ohzone and H. Iwata, 1EEE Trans. Electron Devices ED-39, 1870 (1992).

16. C.-Y. Wu, M.-D. Ker, C.-Y. Lee, J. Ko and L. Lin, 1990 International Electron Devices and Materials Sym- posium, Taiwan, R.O.C., p. 18 (1990).

17. P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE. McGraw-Hill, New York (1988).

18. HSP1CE User's Manual. Meta-Software, Inc. (1990). 19. I. E. Getreu, Modeling the Bipolar Transistor. Tek-

tronix, Oregon (1976). 20. G. Krieger, IEEE Trans. Electron Devices ED-34, 1525

(1987). 21. C.-Y. Wu, Y.-H. Yang, C. Chang and C.-C. Chang,

IEEE Trans. Electron Devices ED-32, 1642 (1985).

A P P E N D I X A

Through the circuit connection in Fig. l(b), the relations among the large-signal branch currents and node voltages

are: t'EB I ( l ) ic2(t) + l l(t ) - i B l ( t ) - - = 0 (A1)

Rs

t'Be2(t) icl(t) + /2( t ) -- inz(t) -- R ~ = 0 (A2)

OCB I ( l ) = VBC2(/) = - - [ [ / D o - - VEBI(t) - - VBE2(/)]. ( A 3 )

The VDo power supply used in CMOS ICs is generally of 5 V. Taking the transient currents of junction depletion and diffusion capacitances into considerations and using the


modified Gummel-Poon model of BJT[17-19], the large- signal base and collector currents of BJTs Ql and Q2 in Fig. l(b) can be written as:

O(Cel "VEBI) O(Ccl 'Vcm ) i m (t) = I m + ~3t + Ot (A4)

8 (Cc I " VcB~ ) ic~ (t) = I o Ot (A5)

c3(Ce2. UBE2) O(Ce2. VBC2) ia2(t) = 1B2 + + (A6)

0t 0t

0(Cc2 " VBc2) ic2(t) = lc2 - Ot (A7)

where

Ce 1 : Cjbcl + Ctb¢l (A8)

Cc I = Cjb~t + C ~ (A9)

Ce2 = Cj~ 2 + C~b~2 (AI0)

Cc2 = Cib~2 + C~2. (AI I)

In above equations, the /Bl(2) and lo(2) are the voltage- dependent intrinsic base and collector currents of Q 1(2). The Cj~tz) and Cjb~<2) are the base-emitter and base- collector junction depletion capacitances of Q 1(2), whereas the C , ~ a ) and C~(2) are the base-emitter and base- collector diffusion capacitances of Q I(2). The equations of the intrinsic base and collector currents as well as the junction depletion and diffusion capacitances of a BJT device have been summarized in Tables 1 and 2, respectively[18].

The O(Cj.vj)/Ot terms in (A4)-(A7) can be further approximated as Cj. (Ovj/Ot) because the value of the OCflOt term is much smaller and can be negligible at each operating voltage range, where the Cj and vj represent the junction capacitance and its voltage bias in each junction of a p - n - p - n structure. Substituting (A4)-(A7) into (A1) and (A2), and using the voltage relations in (A3), the dynamic behaviors of the base-emitter voltages VEB~ (t) and VnE2(t) can be exactly obtained as expressed in (1)-(5).

A P P E N D I X B

Choosing two proper values of the base--emitter voltages for each of the BJTs Q 1 and Q2, their base and collector currents can be approximated by using the piecewise linear models as:

l o = Io0 + go " VEto (BI)

Ie, = IBl0 +gm " VEBI (B2)

for QI, when VEal I> VEBIo,;

and Ic2 = Ic20 + gc2" VBE2 (B3)

IB2 = 11120 + gB2' UBE2 (B4)

for Q2, when VBE 2 t> VSE2o n. If the base-emitter voltage is less than its corresponding

turn-on voltage VEelo n (VBE2on), the base and collector currents of QI (Q2) are set to zeros to simplify model calculation.

In (BI) and (B2), the large-signal transconductances of the collector and the base currents with respect to the base-emitter voltage of Q 1 BJT are defined as:

Alct Ict (VEmb, VCB,b) -- Ic, (VEB,~, VCB,~) gct = - - - (B5)

A r m VEBtb- VE~I~ Aim IBI(VEslb, VCBIb)--Isl(VEBla, VCBla)

gB~ ------ - - (B6) AVEBI VEB~b- VEB~a

and the zero-biased initial currents are

Iclo=lcl(VEBib, Vcslb)--gcl ' VEslb (B7)

[BIO=-IBI(VEBlb, VcBib)-- gll I " VEBIb. (B8)

With the above linearized relations, the approximated turn-on voltages of the BJT Q 1 can be obtained as:

VEB,on=__I_.(Icto lm0~. (B9) 2 ~,go + gBl.]

The two base-emitter voltages, VEBta and VEB~b, used in the above linearized equations for Q I are estimated at the fixed voltages of 0.68 and 0.78 V, respectively. The corresponding base--collector voltages can be found by (A3). Similar technique is also applied with the base-emitter voltages VB~(0.65 V) and VBr2b(0.75 V) of Q2 to determine the piecewise-linearized parameters of gc2, gB2, Ic20, IB20, and VaE2o . in (B3) and (B4).

Documents

Transient analysis of submicron CMOS latchup with a physical criterion