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CMOS Latchup Simulation
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CMOS Latchup Simulati on
Introduction
Triggering of parasitic pnpn structure acrossCMOS well
boundary
Evaluation of different well dopings and depthsEvaluation of
different epi thicknessesOptimize p+/n+ spacing
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Process Simulation Requirements
Accurate process and device simulation of large structuresEasy
way to adjust p+/n+ spacingConsistent mesh with different p+/n+
spacingInterface whole structure to device simulator
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Device Simulation Requirements
Ability to handle large structuresAbility to trigger latchup in
DC and transient modeTracing of complex I-V curvesAppropriate
physical models for pnpn devices
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CMOS Latchup Simul ation
Case Study
Use MaskViews layout interface to construct a pn well
boundarywith mesh spacing tied to mask edge locations
Use ATHENA process simulation to simulate structureATLAS
simulation of latchup by:
positive DC ramp on Vddnegative DC ramp on Vsstransient pulse on
Vss
Post processing analysis
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CMOS Latchup Simul ation
Layout of P+/N+ Well Boundary
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Mask Edges and Grid for 2D Cross Section
of Layout
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Final Process Structure with Junctions
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Final Process Structure with Doping and
Depletion Regions
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Device Simulation Model Requirements
CMOS latchup is a bipolar phenomenaRequires bipolar model set
including accurate recombinationmodelsRequires band gap narrowing
for accurate prediction of parasitic
device gain
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CMOS Latchup Simulati on
Transient Device Simulation Setup
1/ bias Vdd and Nwell to 5V2/ apply -1V pulse to Vss for several
nanoseconds3/ return Vss to zero continue simulation for 1us4/
Analyze current-time plot to analyze trigger point
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CMOS Latchup Simul ation
Current vs. Time During Transient latchup
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Comparison of 1ns and 3ns Duration Pulses
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CMOS Latchup Simul ation
Flowlines in Structure During Vss Pulse
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CMOS Latchup Simulati on
Flowlines in Latched Structure
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CMOS Latchup Simulati on
DC Latchup Simulation Setup
1/ bias Vdd and Nwell to 5V
2a/ apply positive bias ramp to Vdd, trace curveuntil
Idd=1mA/um
2b/ apply negative bias ramp to Vss, trace curveuntil
Iss=1mA/um
3/ analyze curve to measure trigger voltage andholding
current
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CMOS Latchup Simulati on
Positive DC bias on Vdd
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CMOS Latchup Simulati on
Parasitic Vertical pnp Bipolar Characteristic
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CMOS Latchup Simul ation
Negative DC Bias on Vss
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CMOS Latchup Simulati on
Parasitic Lateral npn Bipolar Characteristic
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CMOS Latchup Simul ation
P+/N+ Spacing
To evaluate the effect of p+/n+ spacing the simulations need to
berepeated with different structures
Changes to the p+/n+ spacing can be done in MaskViews. A
newcutline for each spacing is required.
Mesh spacing follows mask edges to ensure consistent
simulationgrid
No changes to ATHENA or ATLAS input files required
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CMOS Latchup Simul ation
Overlay of two Structures with Different p+/n+
Spacings
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CMOS Latchup Simulati on
Comparison of Positive DC Latchup Characteristics
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CMOS Latchup Simulati on
Conclusion
ATHENA and ATLAS are able to simulate CMOS latchup
For DC latchup the CURVETRACE feature an excellent tool
forextracting complex I-V characteristics
In transient mode ATLAS can evaluate the length of pulse
requiredfor latchup
Different p+/n+ spacings can be evaluated by using MaskViewsMore
complex p+/n+ layouts can be evaluated using ATLAS/
Device3D
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