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InDeep Submicron CMOS Tech Dsm
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Slide 1Loke et al.Avago Technologies
Introduction to Deep Submicron CMOS Device Technology
& Its Impact on Circuit DesignAlvin Loke, Tin Tin Wee, Mike Gilsdorf,
Tom Cynkar & Jim PfiesterImaging Solutions Division, Fort Collins, Colorado
IEEE Solid-State Circuits Society SeminarVancouver ChapterFebruary 23, 2006
Slide 2Loke et al.Avago Technologies
Outline• Part 1
• CMOS Technology Trends• MOSFET Basics• Lithography• Deep Submicron FET Fabrication Sequence• Enabling Device & Equipment Technologies
• Part 2• FET Non-idealities & Second-Order Effects• Impact of Technology Advances on Circuit Design• Process Variations in Manufacturing• Conclusions
Slide 3Loke et al.Avago Technologies
Evolution of IC Technology
0.25µm CMOS(Motorola, 1996)
Al (0.5%Cu)Al (0.5%Cu)
oxide (SiO2 )oxide (SiO2 )
M5M5
M4M4
M3M3
M22
M1M1
I can see Waldo, but where’s the transistor?
1st Fabricated IC(Texas Instruments, 1958)
90nm CMOS(TSMC, 2002)
M5M5M4M4M3M3M2M2
M1M1
M9M9
M8M8M7M7M6M6
CuCu
LowLow--KK
Is the transistor getting less important?
Slide 4Loke et al.Avago Technologies
Source: Thompson et al., Intel (2002)
CMOS Scaling is Alive & WellTransistors Are Picking Up The Slack
• Where are we now?• 130nm & 90nm in volume manufacturing (8-inch wafers)• 65nm early production in progress (12-inch wafers)
• Key trends:• Gate CD* scaling is more aggressive than interconnect scaling• Scaling driven by exclusively by digital circuit needs
Source: Wu et al., TSMC (2002)
90nm Technology
59nm59nm
* CD = critical dimension
Slide 5Loke et al.Avago Technologies
Why Aggressive FET Scaling?
• The road to higher digital performance• Cload↓ reduce parasitics (largely dominated by wires & gate load)• ∆V ↓ reduce VDD or logic swing, need for core & I/O FET’s• IFET ↑ all about moving charge quickly
• Major hiccup along the way• Interconnect scaling much more difficult than
anticipated, especially Cu/low-K reliability
tdelay ≈ Cload ∆VIFET
Idsat ≈ ½ µCox (W/L) (VGS – VT)2
• How to beef up IFET?• Tweak with µ, Cox, L & VT
• Technology scaling not necessarily compatible with analog design
Stress-Induced Voiding
Got redundant vias?
Slide 6Loke et al.Avago Technologies
Why Should Designers Care So Much About Technology Details?
• Technology dictates performance limitations• Simulating layout-extracted parasitics now even more critical• Statistical design considerations necessary for circuit functionality• Technology-related surprises keep showing up as we keep scaling
• Implementation of accurate models is ALWAYS late• Live with new technology-related effects & issues before they are
included in simulations• New model implementations not necessarily accurate or reliable• Meanwhile, learn to either mitigate or exploit these effects
• Keeping your foundry partner honest is key to silicon success
• Job security ☺
Slide 7Loke et al.Avago Technologies
MOS Fundamentals• VT = FET ON voltage, i.e., gate voltage required to form inversion layer
connecting source & drain by shorting out back-to-back pn-junctions with substrate
VT = VFB + 2φb +Qdep
Cox
φb = lnNA
ni
kBTq
p-substrate
––
––
–– –
– –––
+ + + + + + + + + + + + + + + +
– – – – –
Qdepdepletioncharge
n– inversion layer
poly gate
n+
sourcen+
drain
siliconsurface + + + + + + + + + + + + + + +
– – – – –– – – – –– – – – –
flatband (offset) voltage due to oxide charge & work function difference oxide capacitance
per unit area = εox / tox
bulk potential
depletion charge per unit area = qNAxdep ∝ NA (xdep ∝1/ NA)
Remember ∇ • E = ρ / ε ?
Slide 8Loke et al.Avago Technologies
Electron Energy Band DiagramFormation of Inversion Layer
VT = gate voltage required to reverse doping of silicon surface, i.e., move φs by 2φb
onset of inversion(surface is undoped)
φb
φs
M O S
φs = 0
onset of strong inversion(VT condition)
φsφs
φb
φsVT
M O S
φs = -φb
inversionlayer
VT = VFB + 2φb +Qdep
Coxoffset bulk
dropoxide drop
EC
EV
Ei
flatband(no field in silicon)
φbφs
EF
EF
siliconsurface
M O S
φs = φb
φb = lnNA
ni
kBTq
Slide 9Loke et al.Avago Technologies
All the Action is at the Surface
VGS > VTVDS > 0 (net source-to-drain current flow)Carriers easily overcome source barrierSurface is strongly inverted
VGS ≈ VTVDS = 0 (no net current flow)Source barrier is loweredSurface is inverted
VGS = 0VDS = 0 (no net current flow)Large source barrier(back-to-back diodes)
electronelectroncurrentcurrent
Source: Sze (1981)
Slide 10Loke et al.Avago Technologies
Life’s Never So Perfect
Ideal
IDS
VDS
Reality
We’ll plunge into a lot of neat second-order effects.
But first, we need to understand what physical structure we’re dealing with, and how it has evolved with scaling …
IDS
VDS
VGS
VGS
Ideal MOSFET = voltage-controlled current source (saturation)
Slide 11Loke et al.Avago Technologies
Warp Speed Ahead Short-Channel Effect (SCE)
• Prominent in older CMOS technologies• How to minimize SCE?
• Minimize volume of charge depleted by source/drain junctions• Higher substrate doping for thinner junction depletion regions (xdep ∝1/ N )
• Higher VT & junction capacitance not consistent with scaling• Shallower source/drain junctions
• Higher source/drain resistance smaller drive currents• Tighter gate coupling to surface potential
• Thinner gate oxide of surface potential direct tunneling leakage• Higher K gate dielectrics
• Other SCE problems: large electric fields carrier vsat & µ degradation
VT
Drawn Channel Length, L
VT rolloff at shorter L since less charge must be depleted to achieve
surface inversion
junctiondepletion
region
poly gate
n+ n+
p-substrate
poly gate
n+ n+
p-substrate
depleted bygate charge
Slide 12Loke et al.Avago Technologies
Lithography TrendsWhat 1µm Barrier???
• Refractive projection (4×) optics• More aggressive CD’s shorter λ• Higher NA lenses $$$• Larger field sizes (increased integration) $$$• Now over 25% of total wafer cost
Resolution =k1 λ
NA
k1 = ƒ (resist quality, resolution tricks)
Source: ICKnowledge.com (2003)
365nm
436nm
365nm
436nm
Slide 13Loke et al.Avago Technologies
Step-and-Scan Projection LithographyBeyond 0.35µm Technology
• Slide both reticle & wafer across narrow slit of light
• Aberration-free high-NA optics only required along 1-D but now requires high-precision constant-velocity stages
• Still much cheaper than high-NA optics optimized in 2-D
• 6” x 6” physical reticle size (4× reduction)• 25 x 33mm or 26 x 32mm field size
shorter edge limited by slit width• Relatively weak intensity of deep-UV
source required development of very sensitive chemically-amplified resists for throughput
Source: Nikon
Deep-UV Slit SourceExcimer Laser
KrF (248nm) or ArF (193nm)
Slide 14Loke et al.Avago Technologies
Key Resolution Enhancement Tricks• Sharp features are lost because diffraction attenuates & distorts higher
spatial frequencies (mask behaving as low-pass optical filter)• Compensate for diffraction effects when printing feature sizes << exposure λ
manage sub-λ constructive & destructive interference• Software complexity during mask fabrication but this is foundry’s problem
Optical Proximity Correction (OPC)• Add scattering features to sharpen corners• Used extensively for poly gate definition
Phase Shift Masking (PSM)• Modulate optical path through mask• Used extensively for contacts & vias• Complicated for irregular patterns
Non-Optimized Optimized
Mask
ResistPattern
Source: Socha, ASML (2004) Source: Plummer, Stanford (2004)
MaskAmplitudeOf Mask
Intensityat Wafer
Amplitudeat Wafer
180°phaseshift
Slide 15Loke et al.Avago Technologies
Deep Submicron FET Fabrication Sequence
Well Implantation
2 n-well p-well
Gate Oxidation &Poly Definition
3
gate oxide
Source/Drain Extension& Halo Implantation
4halos
Spacer Formation &Source/Drain Implantation
5
Salicidation
6
silicide
pFET nFET
Shallow Trench Isolation
1 STIoxidep-Si substrate
Slide 16Loke et al.Avago Technologies
Basics of LOCOS Isolation – 0.35µm & Earlier
• Industry played lots of tricks to reduce width of bird’s beak & make field oxide coplanar with active areas
• Required detailed understanding of visco-elastic properties of oxide during thermal oxidation
• LOCOS ran out of gas beyond 0.25µm
2
Grow thermal field oxide
1
Deposit & pattern thin Si3N4oxidation mask
Strip Si3N4 oxidation mask
3
bird’s beak
Depth of Focus ∝ Resolution / NA
Slide 17Loke et al.Avago Technologies
Shallow Trench Isolation (STI) – 0.25 µm & Beyond
1
2
3
4
5
Advantages over LOCOS technologies
• Reduced active-to-active spacing (no bird’s beak)
• Planar surface for gate lithography
Deposit & pattern thin Si3N4 etch mask & polish stop
Etch silicon around active area –profile critical to minimize stress
Grow liner SiO2, then deposit conformal SiO2 – void-free deposition is critical
CMP excess SiO2
Strip Si3N4 polish stop
etched away in subsequent oxide cleans
Slide 18Loke et al.Avago Technologies
STI Etch Profile Control
Reactive ion plasma etching (RIE)• Etching ions vertically bombard
surface to be removed• Very directional• High sputtering component causes
resist to re-deposit inside trench• Tune etch gas chemistry to keep or
remove redeposited resist for desired etch profile (micromasking) Source: Plummer, Stanford (2004)
Slide 19Loke et al.Avago Technologies
STI HDP-CVD Oxide GapfillHigh-Density Plasma Chemical-Vapor Deposition• Fills aggressive aspect ratios • Rapid cycling between successive deposition & etch• Re-sputtering nature results in very compressive oxide films
Source: Plummer, Stanford (2004)
Conformal CVD HDP CVD
keyhole
Slide 20Loke et al.Avago Technologies
Let’s Think a Little Bit More About CMP
• Ideal world for CMP: want perfectperiodicity of patterns throughout wafer
• Need to throw in dummy features to minimize pattern density variations
optimize planarity• Polishing pad will flex
oxide CMP
dishing
wafer carrier in situ pad conditioner
(critical)
polishing table
polishingpad
wafer(facing down)
slurry
opticalendpointdetection
CMP technology pioneered by IBM• Leveraged expertise from lens polishing
Slide 21Loke et al.Avago Technologies
Always Think Dummies in Any CMP Process• Dummification is key to minimize topography in any CMP process
• Add dummy patterns to open spaces to minimize layout density variations→ Added design complexity to check layout density & insert dummy patterns
• Also critical to step dummy dies along wafer circumference
Slide 22Loke et al.Avago Technologies
Well Implants – Lots of Transistor Variants• core vs. I/O FET’s, core low-/nom-/high-VT variants, native vs. implanted
Coren-well
Coren-well
Corep-well
I/On-well
Coren-well
Corep-well
I/On-well
I/Op-well
Corenative
I/Onative
Coren-well
Corep-well
free lunch!!!
Slide 23Loke et al.Avago Technologies
Well Engineering
Retrograded well dopant profile(implants before poly deposition)
p-well
Depth
SubstrateDoping
Deeper subsurface implant• Extra dopants to prevent subsurface
punchthrough under halos• Prevent parasitic channel formation on
active sidewall beneath source/drain• Faster diffusers (B, As/P)
Shallow & steep surface channel implant • VT control• Slow diffusers critical (Ga, Sb)
Very deep high-dose implant• Latchup prevention• Noise immunity• Faster diffusers (B, As/P)
STIoxide
STIoxide
Implant order matters to prevent ion channeling, especially for the shallow implant
substratebackground
Slide 24Loke et al.Avago Technologies
Gate Oxidation• Need two gate oxide tox’s – thin for core FET’s & thick for I/O FET’s
1 2 3
• Oxide is grown, not deposited• Need high-quality Si-SiO2 interface with low Qf & Dit
• Gate oxide is really made of silicon oxynitride (SiOxNy)• N content prevents boron penetration from p+ poly to channel in pFET’s• Improves GOI (gate oxide integrity) reliability• Side benefit – increased εox
• Foundries now offer triple gate oxide (TGO) processes with two I/O FET varieties
Grow 1st oxide Strip oxide for core FET’s Grow 2nd oxide
I/O FETgate oxide
Core FETgate oxideSi substrate
gateoxide
Slide 25Loke et al.Avago Technologies
Aside on Equipment Technology Evolution
Source: Maex, IMEC (2002)
• Gate oxide no longer furnace grown
• Multi-chamber cluster tools now ubiquitous
• Pre-oxidation clean, gate oxidation & poly/ARL deposition performed in separate chambers without breaking vacuum
• Better thickness & film compositional control (native SiO2 grows instantly when exposed to air)
• Fast – minutes-seconds per wafer vs. hours per wafer batch
• Economically feasible with trend towards larger wafer sizes
TopView
Slide 26Loke et al.Avago Technologies
Poly Gate Definition
Si substrate
• Process control is everything – resist & poly etch chamber conditioning is critical (lesson to remember: don’t clean residues in tea cups or woks)
• Way to get smaller CD’s to trim more (requires tighter control)• Dummification also necessary for poly mask (ILD0 CMP)
poly-Si
1 2 3
anti-reflection layer (ARL)
gateoxide
resistresist
Pattern resist Trim resist (oxygen ash)
Etch gate stack
polygate
• Gate CD way smaller than lithography capability
Slide 27Loke et al.Avago Technologies
Source/Drain & Channel Engineering
Resulting structure has:• Smaller SCE• Shallow junction where needed most• Low junction capacitanceNot to be confused with LDD’s in I/O FET’s• Same process with spacers but Iightly
doped drain (LDD) is used for minimizing peak E fields that cause hot carriers & breakdown
• Extensions need to be heavily doped to minimize series resistance
Different halo & extension/LDD implants for each FET variant
poly gate
self-aligned source/drain extension implant(n-type)
self-aligned high-tilt halo/pocket implant(p-type)
p-well
p-well
poly gate
dielectric spacer formation
p-well
poly gate
self-aligned source/drain implant (n-type)
p-well
poly gate1
2
3
4
halos
Slide 28Loke et al.Avago Technologies
Control of Minimum Channel Length• Foundries get paid for wafers that hit nFET & pFET Idsat targets in Lmin devices
which depend strongly on channel CD • Adjust resist trim ash time to compensate for poly photo variations
• Adjust halo dose to compensate for poly etch variations (modulate position of pnjunction where counterdoping occurs)
• Designers can help by orienting poly gates along direction of least variation
shorter ash time
longer ash time
poly
higherhalo dose
lowerhalo dose
well
Slide 29Loke et al.Avago Technologies
Rapid Thermal Processing (RTP)WasabiWasabi vs. Curry
• Initially developed for short anneals• Impossible to control short thermal cycles in furnaces• Want minimum diffusion for shallow & abrupt junctions
• Process steps:• Annealing repair implant damage• Oxidation gate oxide• Nitridation spacers, ARL• Poly deposition gate
• RTP in single-wafer multi-chamber cluster tools
RTPTe
mpe
ratu
re
Time
Furnace
Tem
pera
ture
Time
substantialramp times
Slide 30Loke et al.Avago Technologies
Self-Aligned Silicidation (Salicidation)• Need to reduce poly & diffusion Rs, otherwise get severe IFET degradation due to
voltage drops from contacts to intrinsic FET (source degeneration)
• Selectivity degraded at RTA2, i.e., metal over SiO2 & Si3N4 will form silicide• Technology progression: TiSix CoSix NiSix
• Scaling requires smaller silicide grain size to minimize Rs variations
1
Deposit sicilide metal (Ti, Co, Ni)
RTA1 (low temperature)Selective formation of metal silicidefrom direct metal reaction with Si
welldiffusion
2
Strip unreacted metal
3
RTA2 (high temperature)Transforms silicide into low-ρphase by consuming more Si
4
poly
STI
Slide 31Loke et al.Avago Technologies
Making Cheap Resistors• Only one extra mask can buy you unsalicided poly & diffusion resistors• Salicide block etch
SiO2 deposition prior to salicide module
field oxide diffusionpoly
1
protection oxide
2Salicide block etch
3
Salicide module
salicide
Slide 32Loke et al.Avago Technologies
Outline• Part 1
• CMOS Technology Trends• MOSFET Basics• Lithography• Deep Submicron FET Fabrication Sequence• Enabling Device & Equipment Technologies
• Part 2• FET Non-idealities & Second-Order Effects• Impact of Technology Advances on Circuit Design• Process Variations in Manufacturing• Conclusions
Slide 33Loke et al.Avago Technologies
SPICE FET Binning• Wondered why so many SPICE transistor bins, e.g, core nFETs?
• A single model cannot suffice what can possibly vary with L & W?
16111621
27121722
38131823
49141924510152025
0.10 0.24 0.5 10 201.2Drawn Channel Length (µm)
0.120.24
0.5
1
10
900D
raw
n C
hann
el W
idth
(µm
)
Slide 34Loke et al.Avago Technologies
VT Variations Across FET L & W in 90nm• VT’s for 90nm core nFET @ 85°C
• VT↑ as L ↓• VT↓ as W ↓• WHY?
0.10
0.16
0.25
0.40
0.63
1.00
1.58
2.51
3.98
6.31
10.0
00.
15 0.38 0.95 2.38 5.97
15.0
0
0.120.140.160.180.200.220.240.260.280.300.320.340.36
VT (V)
L (µm)
W (µm)
0.34-0.36
0.32-0.34
0.30-0.32
0.28-0.30
0.26-0.28
0.24-0.26
0.22-0.24
0.20-0.22
0.18-0.20
0.16-0.18
0.14-0.16
0.12-0.14
0.15/0.1µm
15/0.1µm
15/10µm
0.15/10µm
shortnarrow
shortwide
• Think how much gate charge is needed to raise surface potentialneeded for surface inversion
Slide 35Loke et al.Avago Technologies
Revisiting Short-Channel Effect (SCE)
VT
Drawn Channel Length, L
VT rolloff at shorter Lsince less charge
must be depleted to achieve surface
inversion junctiondepletion
region
poly gate
n+ n+
p-substrate
poly gate
n+ n+
p-substrate
depleted bygate charge
• But VT ↑ as L ↓ is observed… why?
Slide 36Loke et al.Avago Technologies
Reverse Short-Channel Effect (RSCE)
• Mechanism – Transient Enhanced Diffusion (TED)• Halo implant damage creates crystalline defects that accelerate
dopant diffusion in subsequent anneals where damage is repaired • Dopants migrate to source-to-substrate junction & raise source-to-
channel barrier height• VT increases
• Target Lmin near VT peak for good process margin, i.e., minimize VTsensitivity to poly-CD variations
VT
Drawn Channel Length, L
as L decreases, VT rises before conventional SCE kicks in
conventional SCEp-well
poly gate
halo
dopantdiffusiontowards junction
Slide 37Loke et al.Avago Technologies
Narrow-Channel Effect (NCE)
• Prominent with LOCOS isolation• Does not exist in STI
VT
Drawn Channel Width, W
VT increases for narrower W since more gate charge is required to deplete edge of
active area under gate
poly gate
p-substrate
Thicker oxide under gate edge• Tougher to deplete• More gate charge needed for
inversion
poly gate
fieldoxide
bird’s beak
• Sure enough, VT ↓ as W ↓ is observed in 90nm time for another excuse
Slide 38Loke et al.Avago Technologies
Reverse Narrow Channel Effect (RNCE)
• Prominent in STI technologies• Concentration of electric field
lines terminating at corner• Trench recess results from
faster oxide etch rate at STI edge during pre-oxidation HF wet-cleans
VT
Drawn Channel Width, W
VT decreases for narrower Wdue to trench recessing &
corner outdoping
• Edge device turns on before center device I-V kink in very narrow devices
trenchrecess
corner outdoping
Source: Burenkov & Lorenz, Fraunhofer Institut (2003)
Slide 39Loke et al.Avago Technologies
Well Proximity Effect• |VT| ↑ if FET is too close to resist edge due to dopant ions scattering off
resist sidewall into active area during well implants• |∆VT| depends on:
• FET channel distance to well mask edge• implanted ion species/energy
• Other effects: µ ↓, Leff ↑, Rextension ↑ Idsat ↓• Well mask symmetry now critical for FET matching • Modeled in BSIM4.5
high-energywell implant
Source: TSMC (CICC 2005)
90nm 90nm Core Core nFETnFET
∆V
T,g
m(V
)
Average Distance Between MOS Channel & Well Mask Edge
activearea
island
Slide 40Loke et al.Avago Technologies
ON vs. OFF Current Benchmark
1.2V1.0V1.2V1.0V
Comparison of 90nm Technology Foundry Vendors
1.2V1.0V1.2V1.0V
nFETpFET
0.1
1.0
10.0
100.0
1000.0
0 200 400 600 800 1000 1200
OFF
Lea
kage
Cur
rent
(nA
/µm
)
ON Drive Current (µA/µm)
• “No free lunch” principle prevails again: high ION high IOFF
• VT’s not scaling as aggressively as VDD (1.0V in 90nm & 65nm) • Technology providers offer variety of VT’s on same die to
concurrently meet high-speed vs. low-leakage needs
Slide 41Loke et al.Avago Technologies
Leakage Current Contributions
130nm 100nm 65nm
Source: Assenmacher, Infineon (2003)
ISUB Subthreshold leakage from source
IG Gate leakage (direct tunneling)
IGIDL Gate-induced drain leakage (GIDL)
IJ Junction reverse-bias leakage
• Relative contributions of OFF-state leakage (but magnitude of total leakage getting exponentially worse for deeper submicron nodes)
p-well
poly gate
n+ n+
VDD
IG
IGIDL
IJ
ISUB
Slide 42Loke et al.Avago Technologies
Subthreshold Conduction – Diode Action• Diffusion of carriers from source spilling over barrier into channel when
applying VG to lower φs
• Want tight coupling of VG to φs but have capacitive sharing with substrate• Large Cox high-K gate dielectrics, thinner gate oxides• Small CSi low substrate doping, fully-depleted SOI• Inverse subthreshold slope (S) ≈ 100mV/decade at 300K (60mV/dec ideal)
• e.g., VT=0.2V & ION= 100µA IOFF=1µA !!! • Get BJT in limit Cox ∞ & CSi 0
∆φs = ∆VG ×Cox
Cox + CSi
silicon surfacepotential (φs)
Coxgate oxide
capacitanceCSi
silicon depletion
capacitancep-substrate
gate
VG
VB
S = ln(10) ×Cox + CSi
Cox
kBTq
source
drainVG
Slide 43Loke et al.Avago Technologies
Basic Intuition on Body Effect• Body or backgate effect
• More reverse bias between substrate (body) & source increases |VT|
• Basic equation: VT = VT0 + γ ( 2φb+VSB – 2φb ) • Tug-o-war between VG & VB to control surface potential through Cox & Csi
Silicon surfacePotential (φs)
Coxgate oxide
capacitance
CSisilicon
depletion capacitance
p-substrate
gate
VG
VB
Slide 44Loke et al.Avago Technologies
p-well
poly gate
n+ n+
VDD
Drain-Induced Barrier Lowering (DIBL)• Worsens subthreshold leakage in short-channel devices• Soft punchthrough induced by drain-to-substrate depletion region
• |VT | ↓ as VD ↑ (drain-induced SCE)• VD ↑ drain-to-substrate depletion region grows with more reverse bias• Lateral electric fields in drain-induced depletion region lowers source-to-
channel barrier, allowing more carriers to diffuse from source to channel• Typical DIBL magnitude: ∆VT = –0.12V for ∆VD = +1.2V in 90nm
reduction of electron barrier height in conduction band (CB)
at edge of source
CB
VDD
source drain
p-well
poly gate
n+n+
Slide 45Loke et al.Avago Technologies
A Simple AnalogySo Many Effects, How Can We Make Life A Little Easier?
What’s happening to the surface potential?How is source-to-channel barrier height affected?
p-substrate
gate
VB
source
drain
VD
drain
substrate (body)
VG
VD
source
drainVG
source
drain|VB|
Slide 46Loke et al.Avago Technologies
Gate-Induced Drain Leakage (GIDL)• Drain-to-substrate leakage due to band-to-band tunneling current in
very high-field depletion region in drain overlap region
• Similar gate-induced source leakage (GISL) mechanism exists when source is raised above gate potential
• Modeled in BSIM4 not BSIM3
p-well
poly gate
n+ drainhalo
VDD
poly gate
gateoxide E-field & band bending
are strong function of VGD& weak function of VDB
drain
Slide 47Loke et al.Avago Technologies
Gate Leakage (Direct Tunneling)
Historical Trends
Source: Taur, IBM (2002)
• tox has been scaling aggressively with Lmin
• higher IFET
• tighter gate control less SCE• Significant direct tunneling for tox < 2nm• Gate leakage = f (tox, VG)
• Tunneling probability ∝ exp (-α tox)• Hole & electron tunneling in CB & VB• High-K gate dielectric achieves same Cox
with much thicker tox
• Modeled in BSIM4 not BSIM3
Slide 48Loke et al.Avago Technologies
Poly Depletion & Surface Charge Centroid Effects
• Increasing discrepancy between electrical & physical gate oxide thicknesses since charge is not intimately in contact with oxide interface
• Modeled in BSIM4 more accurate I-V & C-V calculations
Si surface charge centroid few Å’s awayfrom oxide interface
n+ poly gate
p-well
gate oxide
poly depletion (band bending) results from nonzero conductivity
gate charge centroidfew Å’s away from oxide interface
Cox = εox / EOT
EOT = Equivalent Oxide Thickness
Source: Wong, IBM (2002)
CCoxox
1.5nm (151.5nm (15ÅÅ))
polypoly--SiSigategate
SiSisubstratesubstrate
gategateoxideoxide
Slide 49Loke et al.Avago Technologies
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.1 1 101
Line
ar V
T at 8
5o C (V
)
L, Drawn Channel Length (µm)
high-VT
nom-VT
low-VT
low-VT
nom-VT
high-VT
pFET
nFET
Using FET’s with Multiple VT’sOne Foundry Example
• Be very careful when using multiple-VT FET’s, especially in analog land• VT separation typically advertised only for L ≈ Lmin
long L
no ∆VT between low-VT & nom-VT
devices
• Foundry may use different mechanisms for setting VT in low-VT vs. high-VT devices• Want to share as many implant masks as possible to save $$$• VT adjustment: channel implant vs. halo implant
short L
∆VT ≈ 0.1V between devices
∆VT
∆VT
Simulated Core FET VT (W=0.6µm)
Slide 50Loke et al.Avago Technologies
Lateral Channel Surface Doping Under Gate OxideOne Foundry Example
short-channelFET
low-VT FET
long-channelFET
nom-VT FET high-VT FET
sourceextension
drainextensionchannel
halo implant dose is significant to total channel dose
in short-channel FET’s
large channel implant dose is significant to total channel
dose regardless of L
Slide 51Loke et al.Avago Technologies
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
-40 -20 0 20 40 60 80 100 120 140 160
Line
ar V
T (V)
Temperature (C)
high-VT
nom-VT
low-VT
low-VT
nom-VT
high-VT
pFET
nFET -0.82mV/C
-0.67mV/C
-0.55mV/C
-0.88mV/C
-1.04mV/C-1.08mV/C
VT vs. Temperature• |VT| ↓ as T ↑
• T ↑Eg ↓ni ↑φb ↓ for constant NA|VT| ↓
• VT can vary a lot with temperature• Worse IOFF due to |VT| ↓ & S ↑
• Temperature sensitivity depends on W & L
φb = lnNA
ni
kBTq
Eg ↓ as Atomic Spacing ↑
Simulated Linear VT for 0.6/0.1µm 90nm Core FET
Eg EV
EC
Where are all the non-valentelectron energy levels?
Slide 52Loke et al.Avago Technologies
0 10 20 30 40 50 60 70 80 90 100
110
Temperature (C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 10 20 30 40 50 60 70 80 90 100
110
Gate OverdriveThreshold Voltage
Vol
tage
(V)
Temperature (C)
0 10 20 30 40 50 60 70 80 90 100
110
Temperature (C)
Voltage Headroom vs. Temperature• Huge issue in 90nm CMOS analog design (VDD=1.0V)
• Must operate FET with small gate overdrive to device in saturation• T ↓ µ ↑ but VT ↑
• With decreasing gate overdrive, worst case headroom may occur at cold temperature
• Not applicable to CMOS where gate overdrive >> VT
nom-VT90nm
core nFET
50µA
VGS
Idsat ≈ ½ µCox (W/L) (VGS - VT)2W/L=0.3/0.3µm W/L=1.2/0.3µm W/L=4.8/0.3µm
W/L
Slide 53Loke et al.Avago Technologies
Impact of Halos on rout• Halo at source side suppresses SCE in short-channel devices
• Halo at drain side creates Drain-Induced Threshold Shift (DITS) in long-channel devices• Drain bias very effective in modulating drain halo barrier VT ↓ Ids ↑• Worse DIBL compared to uniform-doped FET• Can degrade FET rout by 10-100×!!!• Critical limitation for building current sources
(cascoding difficult with low VDD)• Asymmetric FET’s with only source-side halo
shown to improve rout significantly
• Less degradation for devices with weaker halos• Modeled in BSIM4 not BSIM3, but still need improvement
Source: Cao et al., UC Berkeley (1999)
halo
uniform-doped
CB
VD
source drain
Slide 54Loke et al.Avago Technologies
Impact of Halos on Gate Capacitance• Halo implant increases off-state gate capacitance• Impact is worst for short-channel devices where
halos contribute most significantly to channel doping
• BSIM3 & BSIM4 models can reasonably account for poly depletion & charge centroid effects, but implementation is largely mathematical fitting
0
2
4
6
8
10
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
MeasurementSimulation - Original FitSimulation - Improved Fit
Cpa
ralle
l (pF)
Vgs
(V)
range of interest
depletion
Source
Gate
edge of depletion regionretrograded
well
halo
relativedoping
LOW HIGH
inversion
Source
Gate
inversion layer
C-V Characteristics of VCO Varactor
depletioncapacitance
modeling error
Slide 55Loke et al.Avago Technologies
Contact-to-Poly Capacitance
tungstencontact
poly-Sigate
Cross-sectional SEM of 90nm CMOS
active areaSTI
oxidenitridespacer
contact-to-polycapacitance
• Can add substantial parasitic capacitive coupling between gate &source/drain
• Worse if Miller multiplication exists, i,e, diffusion node is not AC ground & moves in opposite direction to gate signal
• Nitride spacer makes matters worse
active
poly gate
source/ drain spacer
contact ILD0
Slide 56Loke et al.Avago Technologies
Active Area Mechanical Stress (LOD) Effect• Silicon is piezoelectric – electrical properties (m*, Eg, VT, …) depends on
mechanical stress state• Compression slower nFET, faster pFET• Tension faster nFET, slower pFET
• STI compression in Si channel due to 10x CTE mismatch between Si & SiO2 and compressive stress of HDP-CVD SiO2 film
• Ids can easily change by 15-20% affects digital device ratios• Channel stress is strong function of distance from poly to active edge
• Can play tricks with tensile spacer & silicide films to relieve channel stress
• Modeled in BSIM4 not BSIM3
high compression lower compression
Source: Xi et al., UC Berkeley (2003)
SA SB SA SB
Slide 57Loke et al.Avago Technologies
Layout Implications of LOD Effect
IIN
85°C
Layout Guidelines for Optimal Matching• Same L & W• Same active area size, shape &
orientation (SA, SB)• Same environment
Example: Current Mirror
IOUT
IIN IOUT
Source: ST Microelectronics (2004)
IIN IOUT
IIN IOUT
GND
GND
GND
BAD!
CHEAP FIX
ANAL RETENTION ☺
Slide 58Loke et al.Avago Technologies
Characterizing Process Variations• Statistical variations in IC manufacturing variations in FET
characteristics • Circuits must function across operating VDD & temperature but also
across statistically acceptable process tolerances• Summarized by spread in nFET & pFET VT’s, or in Idsat’s, i.e., use VT
or Idsat to summarize cumulative effect of ALL process variances• Consider die-to-die, wafer-to-wafer & lot-to-lot variations
pFETIdsat
nFETIdsat
TT
FF
SS FS
SF
Idsat ∝ (VDD–VT) 2
pFETVT
nFETVT
TT
FF
SSFS
SF
acceptable
F = fastT = typicalS = slow
Slide 59Loke et al.Avago Technologies
Correlated vs. Uncorrelated Process Variations• Elliptical 2-D Gaussian distribution from natural variations with no
deliberate retargetting of process parameters
• Tougher to control poly CD than implant doses
1.5
2.0
2.5
3.0
3.5
4.0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.010/0.13µm nFET Idsat (mA)
10/0
.13 µ
m p
FET
I dsat (m
A)
3.0 σ
2.5 σ
MeasurementsSPICE Targets
TTTT
FFFF
SSSS FSFS
SFSF
correlated variations due to common processes e.g., poly photo/etch CD & gate oxide thickness
uncorrelated variations due to uncommon processes e.g., channel & well ion implants
Slide 60Loke et al.Avago Technologies
Skew Process for Design Margin Verification• Process wafers with Idsat’s that target SPICE corners of acceptable distribution• Statistical distribution is cumulative result of ALL variations for processes
targetted as NOMINAL• Countless possibilities of tweaks to achieve skew nFET/pFET Idsat combination• Fab typically employs SIMPLE means of retargetting nFET & pFET Idsat’s with
very few deliberate non-nominal process tweaks• FF vs. SS
• Adjust poly CD, no change in gate oxide thickness• Nominal implant doses
• FS vs. SF• Adjust surface channel or halo implant dose• Nominal poly CD & gate oxide thickness
• Consequences• Nominal & skew results frequently miss intended targets since nominal (by
definition) can land anywhere in distribution• Not 100% representative of natural process corners• Decent approximation for vanilla digital circuits• May be bad approximation for some analog & high-speed digital circuits if
they are insensitive to selected tweaks
Slide 61Loke et al.Avago Technologies
Impact of FET Mismatch130nm Differential Amplifier Example
in+ in-
out+out-
bias
waveforms should be differential
• Extensive work in FET mismatch modeling, pioneered for data converters
• Pelgrom’s basic model (applicable not just to FETs)
WLTV1
∝∆σ
Slide 62Loke et al.Avago Technologies
Technology Options Looking Forward
• Make faster FETs by increasing Cox or µ• Increase Cox
• High-K gate dielectric (e.g., HfSiON) tighter gate coupling, lower gate leakage
• Metal/silicided gate (e.g., W) circumvent poly gate depletion• Development is facing tough integration problems (low crystallization
temperature, interface quality, hysteresis, mobility)• Likely not ready for initial 45nm production
• Increase µ• Apply mechanical strain to channel perturbs m* in E-k diagram• Improved Ion/Ioff performance without sacrificing leakage• Remember: nFET likes tension, pFET likes compression• Emphasis on gate & source/drain straining, not substrate straining• Already used by Intel & IBM at 90nm, TSMC starting at 65nm
Idsat ≈ ½ µCox (W/L) (VGS – VT)2
Slide 63Loke et al.Avago Technologies
Strain EngineeringBasis of High Performance in 65nm & 45nm
• IBM example using Dual Stress Liners (DSL) – nitride liners
N PN PN P
tensile Compr
N P
Tensile nit Compr nit
Contact
ST
Source: Chan, IBM (CICC 2005)
Slide 64Loke et al.Avago Technologies
The Silicon-On-Insulator (SOI) Niche
• Only PD-SOI in production so far• Applications: high-end processors (e.g., IBM Cell, AMD)• What’s hot?
• Low junction capacitance• No body effect – allows taller FET stack with low VDD• Steeper subthreshold characteristic (FD-SOI only)
• What’s not?• Substrate memory effect – substrate hacky-sacked capacitively• Substrate heating – buried oxide is good insulator• Expensive substrate
• In most applications, bulk CMOS is still the way to go
buried oxide buried oxide
partially-depleted (PD-SOI) fully-depleted (FD-SOI)
Slide 65Loke et al.Avago Technologies
The Near Future of PatterningImmersion Lithography
• Remember oil immersion microscopy in biology class?• Extend resolution of refractive optics by squirting water puddle on wafer
surface prior to exposure• nwater ~1.45 vs. nair ~ 1• Tedious but much cheaper than big switch to 157nm reflective optics
• Will be mainstream at 45nm
NA = n sin α = d / 2 f
Source: ICKnowledge.com (2003)
Resolution =k1 λ
NA
Slide 66Loke et al.Avago Technologies
Conclusions• CMOS scaling continues to be driven by digital circuit needs,
analog modules available at a premium• New learning expected in 65nm & 45nm CMOS front-end as
we cope with design implications of strain engineering• Back-end advances in 65nm & 45nm CMOS are incremental• Always a time lag for SPICE models to include new effects
• Huge issue since tapeout mistakes are costlier than ever • Need to work closely with technology providers to quickly
find out about these new effects• Account for them or avoid them!!!
• Statistical & layout considerations more critical than ever• Designers with intimate knowledge of technology are best
positioned to avoid pitfalls & to turn bugs into features
Slide 67Loke et al.Avago Technologies
References (Part 1)• International Technology Roadmap for Semiconductors, Front End Processes (2003 Edition), 2003.• Technology Backgrounder: Immersion Lithography, ICKnowledge.com, 2003.• Technology Backgrounder: Atomic Layer Deposition, ICKnowledge.com, 2003.• H.-S. P. Wong, “Beyond the Conventional Transistor,” IBM Journal of Research & Development, vol. 46, no. 2/3, pp.
133-168, Mar. 2002.• C. R. Cleavelin, “Front End Manufacturing Technology,” IEEE IEDM Short Course on The Future of Semiconductor
Manufacturing, Dec. 2002.• D. Harame, “RF Device Technologies,” IEEE IEDM Short Course on RF Circuit Design for Communication Systems,
Dec. 2002.• S. Thompson et al., “A 90nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Levels of Cu
Interconnect, Low k ILD, and 1µm2 SRAM Cell,” IEEE IEDM Tech. Digest, pp. 61-64, Dec. 2002.• C. C. Wu et al., “A 90nm CMOS Device Technology with High-Speed , General-Purpose, and Low-Leakage
Transistors for System on Chip Applications,” IEEE IEDM Tech. Digest, pp. 65-68, Dec. 2002.• J. D. Plummer et al., Silicon VLSI Technology– Fundamentals, Practice and Modeling, Prentice-Hall, 2000.• S.M. Sze, Physics of Semiconductor Devices (2nd ed.), John Wiley & Sons, 1981.
Slide 68Loke et al.Avago Technologies
References (Part 2)• V. W. C. Chan et al., “Strain Engineering for CMOS Performance Improvement,” IEEE Custom Integrated Circuit Conf.,
Sept. 2005.• T. B. Hook et al., “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. Electron Devices, vol. 50, no. 9,
pp. 1946-1951, Sept. 2003.• J. Assenmacher, “BSIM4 Modeling and Parameter Extraction,” Technical Univ. Berlin Analog Integrated Circuits
Workshop, Mar. 2003. • X. Xi et al., BSIM4.3.0 MOSFET Model – User’s Manual, The Regents of the University of California at Berkeley, 2003.• Y. Taur, “CMOS Design Near the Limit of Scaling,” IBM Journal of Research & Development, vol. 46, no. 2/3, pp. 213-
222, Mar. 2002.• C. R. Cleavelin, “Front End Manufacturing Technology,” IEEE IEDM Short Course on The Future of Semiconductor
Manufacturing, Dec. 2002.• R. Rios et al., “A Three-Transistor Threshold Voltage Model for Halo Processes,” IEEE IEDM Tech. Digest, pp. 113-116,
Dec. 2002.• R.A. Bianchi et al., “Accurate Modeling of Trench Isolation Induced Mechanical Stress Effects on MOSFET Electrical
Performance,” IEEE IEDM Tech. Digest, pp. 117-120, Dec. 2002.• B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.• K. M. Cao et al., “Modeling of Pocket Implanted MOSFETs for Anomalous Analog Behavior,” IEEE IEDM Tech. Digest,
pp. 171-120, Dec. 1999.• A. Chatterjee et al., “Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS,”
IEEE Symp. VLSI Technology Tech. Digest, pp. 147-148, June 1999.• T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.• D. P. Foty, MOSFET Modeling with SPICE: Principles and Practice, Prentice-Hall, 1996.• A. Beiser, Concepts in modern Physics (4th ed.), McGraw-Hill, 1987.