ming-dou-ker documents

Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme
Documents Optimization of broadband RF performance and ESD robustness by -model distributed ESD protection scheme
Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology
Documents Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology
Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
Documents Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs
Documents Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
Documents Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications
Documents Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications
Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation
Documents Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation
Area-efficient layout design for CMOS output transistors
Documents Area-efficient layout design for CMOS output transistors
Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's
Documents Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's
Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
Documents Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation
Documents Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation
ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
Documents ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
Documents High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation
Documents On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation
Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
Documents Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
On-panel output buffer with offset compensation technique for data driver in LTPS technology
Documents On-panel output buffer with offset compensation technique for data driver in LTPS technology
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
Documents The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
[IEEE 2005 IEEE Conference on Electron Devices and Solid-State Circuits - Hong Kong (19-21 Dec. 2005)] 2005 IEEE Conference on Electron Devices and Solid-State Circuits - Methodology
Documents [IEEE 2005 IEEE Conference on Electron Devices and Solid-State Circuits - Hong Kong (19-21 Dec. 2005)] 2005 IEEE Conference on Electron Devices and Solid-State Circuits - Methodology
Transient analysis of submicron CMOS latchup with a physical criterion
Documents Transient analysis of submicron CMOS latchup with a physical criterion