Power Amplifiers in CMOS Technology

POWER AMPLIFIERS IN CMOS TECHNOLOGY:

A CONTRIBUTION TO POWER AMPLIFIER

THEORY AND TECHNIQUES

Mustafa Acar

Samenstelling Promotiecommissie:

Voorzitter: prof.dr.ir. T.J. Mouthaan Universiteit Twente

Secretaris: prof.dr.ir. T.J. Mouthaan Universiteit Twente

Promotor: prof.dr.ir. B. Nauta Universiteit Twente

Assistent-promotor: dr.ir. A. J. Annema Universiteit Twente

Leden: prof.dr.ir. F.E. van Vliet Universiteit Twente

prof.dr. J. Schmitz Universiteit Twente

prof.dr. J.R. Long TU Delft

prof.dr.ir. D.M.W. Leenaerts TU Eindhoven

Title: POWER AMPLIFIERS IN CMOS TECHNOLOGY:



Author: Mustafa Acar

ISBN: 978-90-365-3138-2

ISSN: 1381-3617

DOI-number 10.3990/1.9789036531382

CTIT Ph.D. Thesis Series No. 10-187

Centre for Telematics and Information Technology

P.O. Box 217, 7500 AE Enschede, The Netherlands

© 2011, Mustafa Acar

All rights reserved

The work described in this thesis was supported by the Dutch Technology

Foundation STW (Reliable RF, TCS.6015) and carried out in the IC Design Group,

CTIT Institute, University of Twente, The Netherlands.

POWER AMPLIFIERS IN CMOS TECHNOLOGY:



PROEFSCHRIFT

ter verkrijging van

de graad van doctor aan de Universiteit Twente,

op gezag van de rector magnificus,

prof.dr. H. Brinksma,

volgens besluit van het College voor Promoties

in het openbaar te verdedigen

op woensdag 2 februari 2011 om 14.45 uur

door

Mustafa Acar

geboren op 02 februari 1979

te Gaziantep/Turkije

Dit proefschrift is goedgekeurd door

de promotor prof.dr.ir. B. Nauta

de assistent-promotor dr.ir. A. J. Annema

Only when the last tree has died,

the last river has been poisoned and the last fish has been caught,

will we realize that we cannot eat money

―A cree indian (native american) proverb

Contents

1 Introduction 1

2 Reliability Issues and Modeling of RF CMOS Power Ampli-fiers 52.1 Gate-Oxide Breakdown . . . . . . . . . . . . . . . . . . . . . . 52.2 Hot Carrier Degradation . . . . . . . . . . . . . . . . . . . . . . 72.3 Punch-Through . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Drain-Bulk Breakdown . . . . . . . . . . . . . . . . . . . . . . . 92.5 Negative Bias Temperature Instability . . . . . . . . . . . . . . 92.6 RF CMOS Power Amplifier Breakdown Simulation Methodology 9

3 Theory: Class-E Power Amplifier 133.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Known Design Equations . . . . . . . . . . . . . . . . . . . . . 163.4 Analytical Analysis of Class-E PA . . . . . . . . . . . . . . . . 17

3.4.1 Circuit Description and Assumptions . . . . . . . . . . 183.4.2 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . 183.4.3 Design sets for Class-E operation . . . . . . . . . . . . 20

3.5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.5.1 Achievable Waveforms . . . . . . . . . . . . . . . . . . 243.5.2 Extreme Waveforms . . . . . . . . . . . . . . . . . . . . 26

3.6 Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . 283.6.1 Simplified Design Equations . . . . . . . . . . . . . . . 283.6.2 Optimum design sets . . . . . . . . . . . . . . . . . . . 303.6.3 An Optimization Strategy . . . . . . . . . . . . . . . . . 313.6.4 Design Examples . . . . . . . . . . . . . . . . . . . . . . 32

3.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 Theory: Class-E Power Amplifier with Switch-on Resistance 374.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384.3 Analytical Analysis of Class-E Power Amplifier . . . . . . . . . 394.4 Circuit Description and Assumptions . . . . . . . . . . . . . . . 40

i

4.5 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 404.6 Design sets for Class-E operation . . . . . . . . . . . . . . . . 424.7 Design Examples and Discussion . . . . . . . . . . . . . . . . . 444.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5 Theory: Sub-optimum Operation of Class-E Power Amplifiers 475.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485.3 Variable Slope Class-E Power Amplifiers (Class-EV S) . . . . . . 50

5.3.1 Analysis of Class-EV S Power Amplifier . . . . . . . . . . 505.3.2 Circuit Description and Assumptions . . . . . . . . . . . 515.3.3 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . 515.3.4 Design sets for Class-EV S operation . . . . . . . . . . . 545.3.5 Comparison and Design Example . . . . . . . . . . . . . 555.3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.4 Variable Voltage Class-E Power Amplifiers(Class-EV V ) . . . . . 605.4.1 Analysis of Class-EV V Power Amplifier . . . . . . . . . 605.4.2 Circuit Description and Assumptions . . . . . . . . . . . 615.4.3 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . 625.4.4 Design sets for Class-EV V operation . . . . . . . . . . . 635.4.5 Efficiency and Output Power of Class-EV V . . . . . . . 645.4.6 Proof of Concept Design . . . . . . . . . . . . . . . . . . 665.4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.5 Reliability Simulations for Variable Voltage Class-E (Class-EV V ) 705.5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 74

6 Extended Drain NMOS (ED-NMOS) Power Amplifiers 756.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.3 NMOS and ED-NMOS Sub-Optimum Class-E . . . . . . . . . . 776.4 Scalable Layout Design of RF Power Devices . . . . . . . . . . 796.5 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 806.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7 Segmented Power Devices 877.1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877.3 Digital Detection of Oxide Breakdown . . . . . . . . . . . . . . 887.4 Life Time Extension . . . . . . . . . . . . . . . . . . . . . . . . 897.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8 Summary and Conclusions 958.1 Summary of the Thesis . . . . . . . . . . . . . . . . . . . . . . . 958.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978.3 Original Contributions . . . . . . . . . . . . . . . . . . . . . . . 98

ii

8.4 Recommendations for Future Research . . . . . . . . . . . . . . 98

Samenvatting 99

References 103

Appendix A 1118.4.1 Physical Meaning of the Design Set K . . . . . . . . . . 1118.4.2 Physical Meaning of the variables d, q and p . . . . . . 1118.4.3 Analytical Solution for the Set of Equations . . . . . . . 1128.4.4 Analytical Expression for KX(q, d) . . . . . . . . . . . . 113

Appendix B 117

Appendix C 1198.5 Defect distribution . . . . . . . . . . . . . . . . . . . . . . . . . 1198.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

List of Publications 125

List of Patents 127

Acknowledgement 129

Dankwoord 131

Biography 133

iii

List of Figures

1.1 Three main approaches to the design of RF CMOS power am-plifiers in this thesis . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 A generic schematic of RF PA . . . . . . . . . . . . . . . . . . . 3

2.1 Gate oxide breakdown in a MOS transistor [2] . . . . . . . . . . 62.2 Hot carrier degradation in a MOS transistor [2] . . . . . . . . . 72.3 (a) Punchthrough in a MOS transistor. (b) The effect on the

I-V curve [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.4 Degraded MOSFET model as it is used in the simulator for

describing both oxide breakdown and hot-carrier degradation . 10

3.1 (a) Single-ended Class-E PA (b) Idealized model of single-endedClass-E PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Drawing to show the relations between the elements of the de-sign set K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Normalized switch voltage and switch current of RF choke Class-E PA for d = 0.8, 1 and 1.2 . . . . . . . . . . . . . . . . . . . . 17

3.4 (a) p(q, d) and (b) ϕ(q, d) as a function of q for d = 0.8, 1, 1.2 . 213.5 Elements of the design set KP (q), KC(q), KL(q) and KX(q) as

a function of q for d = 0.8, 1, 1.2 . . . . . . . . . . . . . . . . . . 233.6 Normalized Output Power as a function of q for d = 0.8, 1 and 1.2 233.7 Normalized (a) switch voltage, (b) switch current (c) load cur-

rent (d) capacitor, C current (e) inductor, L current for differentvalues of q for d = 1. . . . . . . . . . . . . . . . . . . . . . . . 25

3.8 RMS value of the normalized switch current IS/I0 as a functionof q for d = 0.8, 1 and 1.2 . . . . . . . . . . . . . . . . . . . . . 26

3.9 Normalized (a) switch voltage and switch current for q = 2.422,(b) switch voltage and switch current for q = 3. For both (a)and (b) d = 1 is assumed. . . . . . . . . . . . . . . . . . . . . . 27

3.10 Design-1, Class-E Design Optimization Flow Chart . . . . . . . 323.11 Design-2, Class-E Design Optimization Flow Chart . . . . . . . 33

iv

4.1 (a) Single-ended Class-E PA (b) Model of Class-E PA with fi-nite dc-feed inductance and switch-on resistance (c) Normalizedswitch (transistor) voltage and current for the model of Class-EPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2 (a) Design set K = KL, KP , KC , KX and drain efficiency (η) asa function of q for m = 0, 0.1, 0.2 . . . . . . . . . . . . . . . . . 42

5.1 Operation classes of single ended switching PA . . . . . . . . . 485.2 (a) Single-ended Class-EV S PA (b) Model of Class-EV S PA (c)

Switch voltage normalized to VDD and switch current normal-ized to supply dc current, I0, of Class-EV S PA with finite dc-feedinductance with the turn-on slope of k = −1.5, k = 0(Class-E)and k = 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3 Elements of the design set KP (q), KC(q), KL(q), KX(q) as afunction of q for different values of k . . . . . . . . . . . . . . . 54

5.4 Loss-factors (a) (F 2

I F 2

V

KP) for limited size transistor Class-EV S and

(b) (F 2

I

KC) for freely chosen size transistor Class-EV S PA . . . . 56

5.5 (a) Class-EV V PA including driver and matching network (b)Model of Class-EV V PA (c) Normalized switch voltage and switchcurrent of Class-EV V PA with turn-on voltage of α = 2, α = 0(Class-E) and α = 1 . . . . . . . . . . . . . . . . . . . . . . . . 60

5.6 PAE and Pantenna using technology and design parameters in [80] 655.7 Simulated (cadence, pss) normalized drain voltage waveform vs.

analytical model of Class-EV V for (a) α = 0, (b) α = 1, (c)α = 2 for QL = 5, 10, 20. The chosen duty-cycle= 50%, R = 1Ω,q = 0.01, VDD = 1V and m = 0.01 . . . . . . . . . . . . . . . . 66

5.8 Simulated (cadence, pss) (a) Efficiency and (b) Normalized Out-put Power (KP ) vs. analytical model for QL = 5, 10, 20. Thechosen duty-cycle= 50%, R = 1Ω, q = 0.01, VDD = 1V andm = 0.01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.9 Measurement Results for α = 0, 1 and 2 . . . . . . . . . . . . . 675.10 Schematic of the PA circuit design, used for evaluating the sim-

ulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705.11 Simulated drain voltage and drain current signals for the upper

NMOSFET in the circuit of Fig. 5.10, in three different opera-tion modes. The α = 0 mode coincides with Class-E operation 71

5.12 Output power plotted against stress time for the three differ-ent operation modes of the Class-EV V PA used in this paper.The dashed horizontal line shows the 22.5mW criterion used fordefining circuit failure in this chapter . . . . . . . . . . . . . . . 71

5.13 PAE plotted against stress time for the three different operationmodes of the Class-EV V PA used in this chapter . . . . . . . . 72

v

5.14 Failure probability plots of the Class-EV V PAs used in this chap-ter. Clearly the α = 1 mode and α = 2 mode have superiorperformance in circuit lifetime over the α = 0 mode . . . . . . . 73

6.1 Cross section drawing of (a) Standard Thick Oxide NMOS tran-sistor (b) Extended-Drain Thick Oxide NMOS (ED-NMOS)transistor.The oxide thickness (tox) = 50A . . . . . . . . . . . . 76

6.2 (a) Sub-optimum Class-E PA (b) Model of sub-optimum Class-E PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.3 According to the sub-optimum Class-E model, (a) drain effi-ciency (η) (b) PAE and output power ratio of standard thickoxide NMOS and ED-NMOS. Break-down voltage (BVGD) ofED-NMOS is assumed to be 2 times higher than NMOS and mfor ED-NMOS is 0.0147 and for NMOS 0.0074 at 2GHz. The mvalues from the compact model was calculated data that agreeswith the measurement results by ≈80−90% . . . . . . . . . . . 78

6.4 A generic layout drawing showing the scalable layout optimiza-tion approach of the ED-NMOS RF power devices. Each unittransistor has 5µm finger length (E). Some connections are notdrawn for the sake of simplicity of the layout picture . . . . . . 79

6.5 (a) Classical symmetric multi-fingered layout (b) asymmetricmulti-fingered device layout . . . . . . . . . . . . . . . . . . . . 80

6.6 General description of the measurement set-up using an activeharmonic load-pull system and the measured drain waveformof the NMOS power device to show the sub-optimum Class-Eoperation. VDD= 2.9V . . . . . . . . . . . . . . . . . . . . . . . 80

6.7 Measured power added efficiency (PAE) and Transducer Gain(=POUT /PAV ) of ED-NMOSI, ED-NMOSII, ED-NMOSIII andStandard Thick-Oxide with respect to output power at 2GHzoperation frequency. ED-NMOS’ have 6V supply voltage whileStandard Thick-Oxide has 3V . . . . . . . . . . . . . . . . . . . 81

6.8 Measured maximum PAE and the corresponding output powerof ED-NMOSI at 2, 3 and 4 GHz with 5.5V supply voltage . . 82

6.9 Measured PAE and output power under sub-optimum Class-E operation of Standard Thick-Oxide NMOS with 3V supplyvoltage for 6 hours operation and ED-NMOSI for 5.5V for 4hours and 6V for 2 hours. The thick-oxide NMOS shows areliability problem by gradually losing its PAE, whereas ED-NMOSI shows no sign of reliability problem. The increase inVDD after 4 hours increases the output power of ED-NMOSI . 83

6.10 Die photos of the ED-NMOSI, ED-NMOSII, ED-NMOSIII, andStandard Thick-Oxide NMOS power devices. The shaded re-gions in the chip photo have designs that are not related withthis work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

vi

7.1 (a) Conventional cascode PA, (b) Segmented PA to increaselifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7.2 Simulated probability mass function for 107 breakdown events,uniformly distributed over 16 segments: the median and meanof the fullest segment is much higher than those over all segments 89

7.3 Simulated POUT and PAE as a function of the number of break-downs (operation time) for 3 situations: continuously using16/16 segments resulting in EOL=110 events, constant-area re-dundancy using 8/16 + 8/16 segments yielding EOL=190 events(+70% lifetime), switching off the worst segment using 16-15-14-13 segments for which EOL=400 events (+260% lifetime) . . 90

7.4 Circuit schematic of each of the 16 PA segments including break-down detection monitoring circuitry, digital control logic anddecoders not shown. . . . . . . . . . . . . . . . . . . . . . . . . 91

7.5 Measured breakdown-indicating sense-voltage as a function ofstress time, under accelerated conditions. For each of the 4 op-eration modes the corresponding effective circuit configurationof the segment is shown . . . . . . . . . . . . . . . . . . . . . . 92

7.6 Measured performance of 1 out of the 16 PA segments, at 900MHz without harmonic tuning . . . . . . . . . . . . . . . . . . 92

7.7 Micrograph of the demonstration vehicle in 90nm: the total PAis subdivided into 16 segments with their own OBD monitor cir-cuitry. Digital control used for addressing each segments state.Total chip area is 3.0mm2 . . . . . . . . . . . . . . . . . . . . . 93

8.1 (a) Supply Voltage-Resistive Load (b) Idealized Class-E PA . . 1118.2 Probability mass functions over all sections, and of the fullest

two sections; For both figures the same defect density but dif-ferent number of sections . . . . . . . . . . . . . . . . . . . . . 121

8.3 The ratio between the number of breakdowns in the fullest sec-tion and the average number of breakdowns, as a function ofthe number of section for 2 total number of events . . . . . . . 122

8.4 The ratio between the number of breakdowns in the fullest sec-tion and the average number of breakdowns, as a function ofthe number of breakdowns for 16 sections . . . . . . . . . . . . 123

vii

List of Tables

3.1 Known explicit design equations for Class-E . . . . . . . . . . . 163.2 Design set for (0.6 < q < 1) . . . . . . . . . . . . . . . . . . . . 293.3 Design set for (1 < q < 1.65) . . . . . . . . . . . . . . . . . . . 293.4 Design set for (1.65 < q < 1.9) . . . . . . . . . . . . . . . . . . 293.5 Design set for maximum output power . . . . . . . . . . . . . . 303.6 Design set for maximum operation frequency . . . . . . . . . . 30

viii

Chapter 1

Introduction

Since the introduction of the first analog cellular phone in 1971 the communi-cation industry in general and wireless industry in specific has followed a fastgrowth. More and more electronic equipment communicating wireless withother devices at ever higher communication speeds are presented to modernconsumers. Some examples of this include, GSM, Bluetooth, WLAN, UMTS,ambient networks, femtocells, car-radio, and future 100Mb/s cellular systems.With the advent of new evolutions in wireless communications such as 3G,4G 1 the demand from the market on low-cost, miniaturized, low-power, andhighly integrated wireless communication devices has increased. In order tomeet these demands integration of RF building blocks into mainstream CMOStechnology has been an ongoing trend [1].

One of the most challenging RF blocks to implement in mainstream CMOStechnology is the power amplifier(PA). So far, many RF building blocks ofmobile communication devices have been implemented successfully in CMOStechnology except for the PA. This is mainly because mainstream CMOS tech-nology is optimized for low voltage while power amplifiers operate at highvoltages2. Low breakdown voltages of CMOS transistors pose many reliabilitychallenges for PAs.

In this thesis, three new approaches are introduced in order to enable thedesign of reliable RF PAs in CMOS technology, see Fig. 1.1. These three newapproaches will be explained by using a generic schematic of an RF PA in Fig.1.2, which shows the basic trade-offs in the design of PAs.

An important trade-off is seen between the the peak drain voltage (N ·VDD)

14G (also known as Beyond 3G), an abbreviation for Fourth-Generation, is a term usedto describe the next complete evolution in wireless communications. A 4G system will beable to provide a comprehensive IP solution where voice, data and streamed multimedia canbe given to users on an ”Anytime, Anywhere” basis, and at higher data rates than previousgenerations.

2As an example, the supply voltage for GSM phones ≥ 3V [2], requiring at least 6Vtransistor breakdown voltage whereas the maximum reliable voltage for 65nm CMOS thin-oxide transistors is 1.2V.

1

Reliable RF CMOS PA

(chapter 6)

Exploration of High-VoltageRF transistor Techniques

Extended-DrainVariable-Slope Class-E(chapter 3 - chapter 5)

Exploration of Switch-ModePower Amplifier Classes

Variable-Voltage Class-E

Exploration of DegradationDetection and Elimination Techniques

Segmented Power Device(chapter 7)

Fig. 1.1: Three main approaches to the design of RF CMOS power amplifiersin this thesis

and the tuning or class of operation of the PA. The peak drain voltage on thetransistor of the PA depends on the tuning or the class of operation3. Thevoltage factor N varies between ≈ 2 (Class-F) and ≈ 4 (Class-E) for switchingPAs, showing how significantly the tuning can influence the reliability limitsof PAs. In this thesis, the tuning methods of switching PAs has been exploredand new classes of switching PAs are found, allowing the optimum operationof RF PAs under given reliability, output power and efficiency conditions hasbeen found ( [3]- [7]).

Another important trade-off is between the supply voltage VDD and theload resistance R. The output power, POUT , is proportional to V 2

DD/R in RFPAs. In sub-micron CMOS technology if standard thin oxide transistors areused the allowed reliable supply voltage will be lower than 0.5V4. If the PA isdirectly connected to an antenna of 50Ω the output power will be only 5mW,which is too low for many of the wireless applications5. In order to be ableto reach to POUT ≥ 1W the required load resistance R would have to be only0.25Ω, which would decrease the power efficiency of the PA to unpracticallylow values [8]6. For high power (≥ 1W) RF amplifiers it is essential to increasethe supply voltage to be able to preserve efficiency and have wide-bandwidth.In this thesis, also high voltage transistors in standard sub-micron CMOStechnology were explored and it is found that drain-extension [9] allows a trade-off between matching network efficiency and power added efficiency, (PAE =

3The main focus of this thesis is switching PAs.4the reliable gate-drain voltage for 65nm CMOS standard thin-oxide transistors is 1V.

Therefore, the allowed supply voltage will be lower than 0.5V.5The required output power of wireless systems for example for GSM is more than 3W

and for HyperLAN is 1W.6A load resistance of 0.25Ω would mean a transformation ratio of n= 200 (from 50Ω

antenna resistance) and the matching network efficiency would be less than 60%, for anassumed passive quality factor of 20 [13].

2

η − PIN/PDC) where η = POUT /PDC is drain efficiency.The third concept introduced in this thesis is degradation detection and

elimination. For PAs, the typical definition of reliable operation time as ”thetime until the occurrence of the first failure (breakdown) of the gate dielectricin a transistor” [10] is overly strict7. Due to large size of power transistorsthe effect of a single breakdown, that can be modeled as a resistance in theorder of a few kΩ between gate-drain, gate-source or the gate-channel [10], onthe performance is small. Recently, it has been shown [11] that e.g. a cascodeClass-E PA can still function properly after a number of oxide-breakdowns.Transistor degradation can be monitored by e.g. oxide degradation, thresholdvoltage-shifts and mobility reduction. Lifetime of PAs can be increased signifi-cantly by segmenting the power transistors into many lower-power segments inparallel, all with their own breakdown detection circuitry, and switching off thesections with the most breakdowns [12]. This segmentation technique allowssystem level reliability monitoring by degradation detection and elimination.

Tuning/MatchingNetworks

Pin

Pout

V /RDD

2~R=R /nL

RL

VDD

PDC

NVDD

Fig. 1.2: A generic schematic of RF PA

The next chapter will address the main reliability issues and modeling ofRF CMOS power amplifiers. Afterwards, an analytical model linking knownand new sub-classes of Class-E PAs is presented in chapter 3. The analyticalsolution in chapter 3 is extended by including switch-on resistance in chapter 4.Likewise, the theory in chapter 4 is extended to cover sub-optimum operationin chapter 5. Chapter 5 is followed by example implementations benefitingfrom the low peak drain voltage of the new classes of operation in chapter6. An RF PA implementation in standard 65nm CMOS technology with 3Woutput power and 70% PAE at 2GHz is presented. Afterwards, the degradationdetection and elimination concept in RF CMOS PAs is introduced in chapter7. In chapter 7, digital detection of oxide breakdown and life-time extension inCMOS technology are explained. Chapter 8 ends the thesis with conclusions.

7Generally in order to obtain high output power, CMOS RF PAs are designed at theedge of their reliability limits, which can cause reliability issues (e.g. oxide breakdown) inthe presence of antenna mismatch, mistuning etc.

3

Chapter 2

Reliability Issues andModeling of RF CMOSPower Amplifiers

Several degradation mechanisms can significantly affect the performance ofCMOS power amplifiers. Estimating the influence of the degradation mech-anisms on the life-time of the RF power amplifiers and dealing with themthrough careful design is essential in the implementation of RF power ampli-fiers in CMOS technology.

This chapter describes the most well-known degradation mechanisms: gate-oxide breakdown, hot carrier degradation, punch through, drain-bulk break-down and negative bias temperature instability (NBTI) that can significantlyinfluence the performance of CMOS power amplifiers. Moreover, a degradedNMOS transistor model and simulator taking into account both oxide break-down and hot carrier degradation are presented.

2.1 Gate-Oxide Breakdown

Gate-Oxide breakdown is the sudden formation of a conductive path in thegate-oxide of a MOS device as a result of application of a high voltage. Theallowable gate-oxide voltage becomes smaller as the gate oxide thickness isreduced in each process generation1.

As can be seen in Fig. 2.1, the channel voltage varies from the source todrain. As a result, the oxide stress, the voltage difference between the top ofthe oxide and the bottom of the oxide is a function of position. The higheststress areas occur at the source and drain oxide edges and therefore from adesign standpoint, we must ensure that the gate-source and the gate-drain

1The rule of the thumb is 5MV/cm oxide thickness, for example 250nm CMOS 2.5V and65nm CMOS 1.2V.

5

source-sidestress=

drain-sidestress=

Distance

Voltage

VD

VG-VT

VS

Bottom ofOxide

Top ofOxide

VGD

VGS

(VG)

Channel

Depletion

Fig. 2.1: Gate oxide breakdown in a MOS transistor [2]

voltages (VGS and VGD) never exceed pre-specified values, by design [2].Although it is often assumed that oxide breakdown occurs instantly at

a predetermined ”breakdown voltage,” in fact the failure is a probabilisticevent, with increasing probability as voltage, stress time, or oxide area areincreased [2].

Oxide breakdown is considered a two-step process [14]. A gradual build-upof damage occurs in the oxide before the sudden formation of a breakdownpath. The anode-hole injection model [15], the anode hydrogen release model[16] and the thermochemical model [17] have been proposed for describing thedegradation of oxide breakdown.

After a breakdown path has been formed it can manifest itself in differentways [18]:

• In hard breakdown, a large gate current increase can be observed. Thistype of breakdown is typically found in thick oxide devices and highvoltage stress, which is not addressed in this thesis.

• In soft breakdown [19] a small sudden gate current increase and a suddengate current noise increase is observed.

• Progressive breakdown [20] is the term used for the non-instantaneousformation of a hard breakdown path.

Hard breakdown has the most disastrous effect on device performance. Theeffect of progressive breakdown is similar, but only after the degradation hasprogressed significantly.

6

2.2 Hot Carrier Degradation

Hot carrier degradation is an effect caused by high energetic charge carriersflowing in the channel of a mosfet. In short channel devices, the lateral fieldcan be extremely high, and consequently carriers can achieve a very high en-ergy before losing momentum to a collision with the crystal lattice. Some ofthese ”hot energy carriers” collide with the lattice before arriving at the drainwith sufficient energy to result in impact ionization, see Fig. 2.2 [2]. This,in addition to potential avalanche multiplication, can result in surface defects,resulting in a reduced carrier mobility in the channel. This can also result intrapped charge in the gate oxide or oxide/silicon interface, shifting the localthreshold voltage. Usually this damage occurs in the drain region where theelectric field is very high, causing the damage to manifest itself as an increasein on-resistance and knee voltage, reducing the power amplifier performance.Unlike the gate oxide breakdown, the hot carrier degradation is not intrin-sically catastrophic. Instead, it causes a gradual degradation in the deviceperformance over a period of time [2].

Fig. 2.2: Hot carrier degradation in a MOS transistor [2]

Although hot carrier degradation is caused by a different mechanism thangate-oxide breakdown, the damage due to hot carriers can result in an increasedrate of gate oxide damage [2]. For hot carrier degradation to be noticeable, itis necessary to have high drain-source voltage, and substantial drain current,at the same time. Thus, from a circuit design perspective, the hot carrierdegradation can be prevented by avoiding channel current when drain voltageis high. This happens ordinarily in a switching amplifier (e.g. Class-E poweramplifiers), where high efficiency is achieved by having a small transistor volt-age while the transistor conducts current and vice versa, making switchingpower amplifiers less prone to hot carrier degradation. However, hot carrierdegradation can be a serious issue in linear power amplifiers [2].

7

2.3 Punch-Through

Under normal circumstances the drain-source current of a MOS transistorflows close to the surface when a large enough gate bias is applied to createan inversion channel. In the absence of a gate bias, very little current flowsbecause the drain-bulk and the source-bulk diodes are effectively connectedback-to-back with opposite polarities. As larger voltages are applied to thedrain, the drain-bulk depletion region extends farther to accommodate theelectric potential drop. This depletion region will eventually extend all the wayto meet the depletion region of the source-bulk junction, thereby diminishingthe potential barrier that stops the direct flow of current between the drain andthe source, as depicted in Fig. 2.3(a) [2]. This punch-though process results ina large current flow that can occur even in the absence of any significant gatebias (Fig. 2.3(b)). This punching effect already gives rise significant increasein drain current before the depletion regions touch: When they approach eachother, the potential barrier height drops rapidly, increasing current from oneside to the other. Punch-though is exacerbated by smaller channel length, andlarger VDS . The significance of punch-through reduces rapidly with increasingchannel length [2].

VDS

IDS

Fig. 2.3: (a) Punchthrough in a MOS transistor. (b) The effect on the I-Vcurve [2]

Punch-through is not intrinsically destructive, although the simultaneousoccupance of high voltage and high current can easily result in thermal failure ifsustained. However, the process can generate its own hot carriers, potentiallycausing similar reliability issues as discussed in section 2.2. From a designperspective, punch-through can be dealt with by making sure that VDS andVDB of a single transistor remains at all times below a certain pre-specifiedvalue for any given channel length [2].

8

2.4 Drain-Bulk Breakdown

In a standard CMOS process the bulk is connected to a fixed electrical poten-tial and the drain-bulk diode experiences a reverse bias directly proportionalto the absolute drain voltage, VD. This diode has a reverse breakdown volt-age primarily determined by the doping of the bulk (the lightly doped side).Therefore, it is important to make sure that the drain-bulk voltage does notreach this breakdown voltage in addition to maintaining smaller than its crit-ical level [2]. Fortunately, this breakdown voltage is relatively high in todaysCMOS processes (e.g., ≥ 10 V in 65 nm CMOS).

2.5 Negative Bias Temperature Instability

Negative Bias Temperature Instability (NBTI) effect is created by trap gen-eration at the Si/SiO2 interface in PMOS transistors under the negative biascondition at elevated temperatures and degrades the device driving current.The interaction of inversion layer holes with hydrogen passivated Si atoms canbreak the Si-H bonds, creating an interface trap and one H atom that candiffuse away from the interface (through the oxide) or can anneal an existingtrap [21]. The broken bonds act as interfacial traps and increase the thresholdvoltage of the device, thus affecting the performance of the integrated circuit.A similar mechanism can be observed in NMOS transistors labeled PBTI [18].NBTI impact gets more severe in scaled technology due to higher die tem-peratures and utilization of ultra thin gate oxide [21]. When PA topologiesinvolving PMOS transistors are used NBTI effect should be taken into account.

2.6 RF CMOS Power Amplifier Breakdown SimulationMethodology

The occurrence of a breakdown event in the gate-oxide of a MOS transistor,may not necessarily lead to circuit failure, first shown in [10] for digital circuits.In [22]- [24] the impact of breakdown paths on RF Power Amplifier (PA) per-formance was investigated and the results showed a very high robustness, evento multiple gate oxide breakdown events. If multiple breakdown events can beaccurately taken into account for predicting circuit lifetime of such circuits, de-sign guidelines may be relaxed, allowing higher voltage levels and hence higheroutput power of the power amplifiers or longer life-time for the same voltagelevels. Therefore, a reliability simulator that incorporates multiple breakdowneffects is a very beneficial tool for RF power amplifier design.

In this section, the simulation methodology of Guido Sasse [25] for assess-ing circuit-level failure probability of RF circuits that can withstand multipleoxide breakdown events is introduced. The simulation methodology makes useof the model shown in Fig. 2.4 and Spectre as circuit simulator. Up to presentsuch a simulator has never been shown before [25]. This simulator can be usedby circuit designers in order to increase performance of RF circuits as the re-striction on the maximum allowable voltage levels can be relaxed for individual

9

circuits. The simulator combines both multiple gate-oxide breakdown effectsand hot carrier degradation. The model used for degraded MOS operation isbased on well-accepted models for these effects.

Fig. 2.4: Degraded MOSFET model as it is used in the simulator for describingboth oxide breakdown and hot-carrier degradation

Present-day reliability simulators [26], [27] typically only include effects ofhot-carrier degradation and/or NBTI. Modules for incorporating gate-oxidebreakdown have been developed such as in [28], but here circuit failure wasassumed to coincide with the first breakdown event in a circuit. In this relia-bility simulator, a new methodology is presented in which multiple breakdownevents can accurately be taken into account for predicting the lifetime of RFCMOS circuits.

The simulation model described in this section takes into account the effectof gate-oxide breakdown and hot-carrier degradation. The simulation modelmakes use of the model shown in Fig. 2.4 for modeling degraded MOS tran-sistor operation. The two conductances GBD,D and GBD,S are used to modelgate oxide breakdown, while the voltage source ∆VT and the current controlledcurrent source (CCCS) Ac · ID take into account hot-carrier degradation.

The model used for describing post-breakdown behavior of MOS transistoris based on the work done by [10]. In that work, the breakdown path wasmodeled as a conductive path of ∼1 mS and the effect of this conductive pathon MOS transistor performance was related to the location of the path withrespect to the channel. Breakdown paths located near the drain and sourceregions proved to exhibit the most disastrous effect on device performance.Breakdown paths in the middle of the channel are manifested as conductivepaths with a conductance ≪1 mS. Only breakdown events occurring at theoverlap regions are considered in the model in Fig. 2.4. This assumption isallowed for the circuits put under investigation in this thesis: in these circuitsthe probability of inducing breakdown paths in the overlap regions exceeds theprobability of inducing them elsewhere by far, due to the relatively high levels

10

of the gatedrain voltage VGD in the MOS transistors used in these circuits.Degraded MOS transistor performance after hot-carrier stress is assumed tooriginate completely from the generation of interface states. The model takesinto account a threshold voltage shift as well as a reduction in the channelmobility; these are both related to the number of generated interface statesthrough [9]:

∆VT =1

ηV T

q∆Nit

AGCox(2.1)

1

µi=

1

µ0

(

1 +Kµ∆Nit

AG

)

(2.2)

In these expressions ∆Nit is the number of generated interface states. AG

is the total gate area of the device, ηV T and Kµ are technology dependent pa-rameters, q is the elementary electron charge and Cox is the oxide capacitanceof the device. Furthermore, µ0 refers to the channel mobility of an undegradeddevice and µi to that of a degraded device. The degradation in channel mobil-ity is accounted for by the CCCS Ac · ID in Fig. 2.4. The following expressioncan be derived:

Ac =α∆Nit

1 + α∆Nit(2.3)

Here, α is a constant, dependent on parameters µ0, Kµ and AG in equation(2.2). The oxide breakdown parameters GBD,D and GBD,S are given by:

GBD,D = nBD,D · 10−3 S (2.4)

GBD,S = nBD,S · 10−3 S (2.5)

Here nBD,D and nBD,S refer to the number of breakdown events that havetaken place at the gatedrain respectively gatesource overlap region.

For simulating circuit performance of circuits that have been under opera-tion for a given amount of time, the appropriate values of the model parametersof Fig. 2.4 if Nit, nBD,D and nBD,S are known.

Further details of the modeling of the degradation rate of the simulatorand the implementation of the simulator can be found in [18] and [25]. TheRF reliability simulation model is used in chapter 5 in life-time prediction ofdifferent classes of power amplifiers.

11

Chapter 3

Theory: Class-E PowerAmplifier

3.1 Abstract

This chapter presents the analytical solution in time domain for the idealsingle-ended Class-E Power Amplifier (PA). Based on the analytical solutiona non-iterative procedure for choosing the circuit parameters is presented forClass-E PAs with arbitrary duty-cycle and finite dc-feed inductance (e.g., con-tinuously ranging from Class-E with small finite drain inductance to Class-Ewith RF choke). The obtained analysis results link all known Class-E PAdesign equations as well as presenting new design equations. An importantreliability concern ”peak drain voltage” is shown to be dependent on the duty-cycle. The result of the analysis gives more degrees of freedom to designers intheir design and optimization by further expanding the design space of Class-EPA1.

3.2 Introduction

The Class-E tuned power amplifiers introduced by [29], [30] offers a means ofhighly efficient power amplification. The Class-E power amplifier consists of aload network and a single transistor that is operated as a switch at the carrierfrequency of the output signal. The most simple type of load network consistsof a capacitor shunting the transistor and a series-tuned output circuit, whichmay have a residual reactance shown in Fig. 3.1. Note that the total shuntcapacitance C is due to the intrinsic transistor capacitance (Cint) and the loadnetwork capacitance (Cext). The Class-E PA eliminates the power losses dueto the discharge of the output capacitance of the transistor in an elegant way

1This chapter was published in IEEE Transactions on Circuits and Systems I (TCAS-I), [7].

13

by making sure that the voltage (VC) is zero at the moment the switch is closedsee Fig. 3.1.

Cint Cext

LC0

L0 X

R

C

L C0L0 X

R

IR

IC

IL

IS

VC

VC(t

)/V

DD

VDD

VDD

tuned at

time

Fig. 3.1: (a) Single-ended Class-E PA (b) Idealized model of single-endedClass-E PA

After the first introduction of Class-E PAs by Ewing [29] in his doctoralthesis in 1964 many papers analyzing Class-E power amplifier have been pub-lished [30]- [49] and many different aspects of Class-E power amplifier (PA)has been analyzed. The published papers can be categorized in two maingroups: Class-E PA with RF choke [29]- [38] and Class-E PA with finite dcfeed inductor [39]- [49].

The ideal Class-E PA with RF choke has been analyzed and the analyticaldesign equations are given in the literature [30, 31].

An early analysis of Class-E PAs with finite dc feed inductance is publishedby [39] in 1987, followed by e.g. [40] and [41]. The common property of all thesepapers [47] is that the procedure for obtaining the final circuit design elementsis either long, complex and iterative [39], [40] or does not provide much insightinto the circuit design or is not analytically exact [41]. The inclusion of someeffects such as finite switch-on resistance, finite load quality factor etc. are

14

reported to turn the design procedure into an even more lengthy and iterativeprocess [44]- [46].

This chapter presents an analytical solution for the ideal Class-E PA, show-ing the relation between the circuit elements and the input parameters. Thesolution reveals the existence of infinitely many design equations for the idealClass-E PA shown in Fig 3.1b due to freedom in the value of the dc-feedinductor and in the switch duty-cycle. Based on the analytical solution a non-iterative procedure for choosing the circuit design elements is presented in thischapter. The given design equations in [31], [49] and [50] are subsets of theanalytical design equation in this chapter. The presented analytical designequations expand the design space of Class-E PA, thereby offering much morefreedom in the design procedure of a Class-E PA.

In this chapter:

• The analytical design equations for ideal single-ended Class-E and theirderivation are given. An arbitrary switch duty-cycle is allowed which isvery important in Class-E PA design [52] whereas only 50% duty-cyclecase is considered in [3].

• A design optimization routine for Class-E PA is introduced; this helpsdesign optimal Class-E PA under certain boundary conditions.

The outline of this chapter is as follows. Known Class-E PA design equa-tions are briefly discussed in section 3.3. The derivation of the Class-E PAequations as well as the assumptions, the circuit description and the mainhighlights of the derivation are explained in section 3.4. The Class-E wave-forms obtained as a result of the analysis are shown and interpreted in section3.5. A number of applications utilizing the infinitely many solutions of Class-Eare given in section 3.6. Section 3.7 summarizes the most important findingsin this chapter.

15

3.3 Known Design Equations

Tab. 3.1: Known explicit design equations for Class-E[31] [49] [50]

In literature, design equations for Class-E PA can be found that can be used toset the correct values for components in a Class-E PA circuit. For the circuitin Fig 3.1 different design equations are reported in [31], [49] and [50]. Thesedifferent design equations form different design sets K = KL, KC , KP , KX,each consisting of values KL, KC , KP and KX that relate circuit componentvalues to input parameters such as supply voltage, operating frequency andoutput power2 as illustrated in Fig. 3.2.

w

C

LX or CX

POUT

R

L

VDD

2

KP(q,d)

KL(q,d)

KX(q,d)

KC(q,d)

Fig. 3.2: Drawing to show the relations between the elements of the design setK

The design sets in [31], [49] and [50] are summarized in Table 3.1 3

The three design sets K given in Table 3.1 are specific forms of the Class-EPA shown in Fig 3.1, with their specific assumptions:

• the design set corresponding to the work in [31] assumes an RF-choke:L → ∞,

2L0 and C0 seen in Fig 3.1 can be determined from the chosen quality factor (QL =ω0L0/R) where ω0 = 1/

√L0C0. For the physical meaning of the design set elements K see

Appendix-A.3In [31], some symbols (e.g. ψ,B) similar to the design set K elements are used. In order

to prevent any confusion we find it wise to show the relation between the given symbolsin [31] and in this chapter ψ = tan(KX), B = KC/R.

16

• the parallel circuit Class-E PA in [49] and [48] assumes a zero reactancefor X .

• the even harmonic resonant Class-E PA in [50] assumes that 1/√

LC =2n where n = 1, 2, 3, ...∞.

All of these three subclasses of the Class-E PA (in Fig 3.1) have their specificadvantages and disadvantages. It is reported that the Parallel Circuit Class-E PA [48], [49] and the Even Harmonic Resonant Class-E PA [50] are moresize-efficient than the RF-choke Class-E PA [31]. In comparison to RF-chokeand Even Harmonic Resonant Class-E the Parallel Circuit Class-E PA allowsusing higher load resistance, which typically results in a more efficient outputmatching network and in a possible reduction in the required supply voltage,which might enable the implementation of the Class-E PA in low-voltage tech-nologies. On the other hand, using an RF-choke reduces the sensitivity of theClass-E PA to drain inductance variations.

This chapter presents an analytical solution for the design set K for Class-E PAs. This solution shows the existence of not only the aforementioned 3design sets, but of infinitely many design sets K due to freedom in both thevalue of dc-feed inductance and in the switch duty-cycle. This yields muchmore design freedom and much more opportunities to trade advantages anddisadvantages of the many design sets K.

3.4 Analytical Analysis of Class-E PA

5

3

4

2

0

1

4

2

3

1

0000

d=1.2

d=1

d=0.8

d=1

d=0.8

d=1.2

p/w 2p/wp/w 2p/w0

switch-on switch-off

VC(t

)/V

DD

I S(t

)/I 0

switch-on switch-offtime time

Fig. 3.3: Normalized switch voltage and switch current of RF choke Class-EPA for d = 0.8, 1 and 1.2

Analysis of the Class-E PAs are already described in literature, see e.g. [31],[39], [46], [48], [49], [50] and [51]. In [31], [49] and [50] an analysis only for

17

one sub-class of Class-E PAs is done. The analysis given in [39], [46] and [51]are based on Laplace transform technique and provide only particular solutionswith the presentation of the load network parameters in a table format [48]. Inthe analysis given in [48], only 50% switch duty-cycle operation is consideredand numerical solution techniques are used to derive design equations.In this chapter, a complete analytical derivation is done for ideal Class-E PAswith finite dc-feed inductance and arbitrary duty-cycle. This section presentsthe analytical derivation of design sets K for Class-E PAs. The complex math-ematical results of the current section are simplified and discussed in somedetail in sections 3.5 and 3.6.

3.4.1 Circuit Description and Assumptions

The circuit schematic of the Class-E PA is given in Fig. 3.1. In the analysisand derivations in this chapter a number of assumptions are made:

• the only real power loss in the circuit occurs on load R

• the switch is lossless with zero on-resistance and infinite off-resistance

• the loaded quality factor (QL) of the series resonant circuit (L0 and C0)is high enough in order for the output current to be sinusoidal at theswitching frequency

Fig. 3.3 illustrates the switching behavior and the switch definition used inthis derivation: in the time interval 0 ≤ t < d · π/ω the switch is closed and inthe time interval d·π/ω ≤ t < 2π/ω it is opened. This switching action repeatsitself with a period of 2π/ω. Note that the chosen value of d determines theswitch duty-cycle. For example, d = 1 corresponds to conventional 50% switchduty-cycle operation.

In order not to have any switching losses it is necessary to satisfy thefollowing well-known Class-E conditions 3.1 and 3.2 [30, 31]:

VC(2π/ω) = 0 (3.1)

dVC(t)

dt

∣

∣

∣

∣

t=2π/ω

= 0 (3.2)

3.4.2 Circuit Analysis

Two fundamental boundary conditions (e.g. continuity of the capacitor voltageand the continuity of the inductor current) are used together with the Class-Econditions ((3.1) and (3.2)) in order to solve the relation between the inputparameters and the circuit element values in Class-E PAs.In the analysis, the current into the load, IR sin(ωt + ϕ), is assumed to besinusoidal. Note that theoretically this occurs only for infinite Q of the series

18

resonant network consisting of L0 and C0. It is however a widely used assump-tion that simplifies analysis considerably: In the time interval 0 < t < d ·π/ω,the switch is closed and hence the capacitance voltage VC(t) = 0 and the cur-rent through the capacitance IC(t) = C · dVC(t)/dt = 0. In this time interval,the switch current IS(t) is

IS(t) = IL(t) + IR sin(ωt + ϕ)

=VDD

Lt + IL(0) + IR sin(ωt + ϕ) (3.3)

where IL(0) = −IR sin(ϕ)

In the time interval d · π/ω < t < 2π/ω, the switch is opened. Then, in theClass-E PA the current through capacitance C is

IC(t) =1

L

∫ t

dπ/ω

(VDD − VC(t)) dt +

IL

(

dπ

ω

)

+ IR sin(ωt + ϕ) (3.4)

Relation (3.4) can be re-arranged in the form of a linear, nonhomogeneous,second-order differential equation after substituting IC(t) as C ·dVC(t)/dt anddifferentiating both sides with respect to t.

LCd2VC(t)

dt2+ VC(t) − VDD − ωLIR cos(ωt + ϕ) = 0 (3.5)

which has as solution

VC(t) = C1 cos(qωt) + C2 sin(qωt) + VDD −q2

1 − q2pVDDcos(ωt + ϕ) (3.6)

where q =1

ω√

LC(3.7)

p = ωLIR/VDD (3.8)

C1 =q2 cos (2 qπ) cos (ϕ)

1 − q2p + (3.9)

sin (2 qπ) q sin (ϕ)

1 − q2p − cos (2 qπ)

VDD

C2 = sin (2 qπ) q2 cos (ϕ)

1 − q2p − (3.10)

q cos (2 qπ) sin (ϕ)

1 − q2p − sin (2 qπ)

VDD

The coefficients C1 and C2 follow from the Class-E equations (3.1) and (3.2).It follows from (3.3) and (3.6) that VC(t) and IS(t) can be expressed in terms

19

of VDD and ω only if d, q, p and ϕ are known. In Appendix-A, the physicalmeaning of d, q and p are explained. The derivation of these four parametersis the next step in the derivation of the Class-E design equations.

To derive expressions for the four unknowns so far, d, q, p and ϕ initialoff-state conditions: VC(dπ/ω) = 0 and IL(dπ/ω) = VDDdπ/(ωL) − IRsin(ϕ)can be used.

The following two non-linear relations for ϕ, p, q and d follow from theinitial off state conditions. These two relations can be used to solve ϕ and panalytically in terms of q and d which yields, together with (3.6), (3.3) thesolution of any Class-E PA. Therefore, here q and d are chosen as free designvariables. In theory, q can take any positive real value and d can take any realvalue4 in the range 0 < d < 2. The two relations for ϕ, p, q and d are:

f1(p, ϕ, q, d) = p(

a1(q, d) sin(ϕ) − (3.11)

b1(q, d) cos(ϕ))

− c1(q, d) = 0

f2(p, ϕ, q, d) = p(

a2(q, d) sin(ϕ) − (3.12)

b2(q, d) cos(ϕ))

− c2(q, d) = 0

The functions a1(q, d)...c2(q, d) and the details of the analytical solution for pand ϕ are given in the Appendix-B.

3.4.3 Design sets for Class-E operation

The mathematical derivation of the existence of infinitely many solutions dueto freedom in the value of dc-feed inductor and in the switch duty-cycle leadingto true Class-E operation can be simplified considerably, yielding an easy-to-use design procedure for Class-E PAs. In the previous subsection, it was men-tioned that p and ϕ both can be solved as a function of q and d; the resultingrelations are shown in Fig 3.4. Using the relations for ϕ, p, q and d design setK = KL, KC , KP , KX can readily be derived.

KL : The expression for KL can be derived by using the fact that (with theassumption of an ideal switch) the conversion efficiency from DC power to ACpower is 100%:

I2R

R

2= I0VDD (3.13)

4In practical designs, the useful range of both q and d are limited as will be shown laterin this chapter.

20

d=1.2

d=1d=0.8

p

q

jd=0.8

d=1

d=1.2 q

Fig. 3.4: (a) p(q, d) and (b) ϕ(q, d) as a function of q for d = 0.8, 1, 1.2

In this relation, I0 is the average supply current5:

I0 =ω

2π

∫ 2π/ω

0

IS(t) dt

= IR

(πd2

4p− d

2sin(ϕ) − cos(dπ + ϕ)

2π+

cos(ϕ)

2π

)

(3.14)

Substitution of (4.9) and (3.8) in (3.13) yields

KL(q, d) =p

d2π2p − cos(dπ+ϕ)

π − d sin(ϕ) + cos(ϕ)π

(3.15)

Since p and ϕ both are functions of q and d as given in the Appendix-B andplotted in Fig 3.4, KL(q) is a function of e.g. only q and d.

KC: KC follows directly from (3.7) and (3.15):

KC(q, d) =1

q2KL(q, d)(3.16)

KP: An expression for KP as a function of p and q can easily be found usingIR =

√

2POUT /R and (3.8):

KP (q, d) =1

2

p2

KL(q, d)2(3.17)

5The dc current from the supply can be conducted to ground only via the switch.

21

KX: An analytical expression for KX can be derived using two fundamen-tal quadrature Fourier components of VC(t). The analytical expression forKX(q, d) in terms of q and d is given in Appendix-B.

VR =1

π

∫ 2π/ω

0

VC(t) sin(ωt + ϕ) dt

VX =1

π

∫ 2π/ω

0

VC(t) cos(ωt + ϕ) dt

KX(q, d) =VX

VR(3.18)

The values for KL(q, d), KC(q, d), KP (q, d) and KX(q, d) are plotted inFig. 3.5 as a function of q for d = 0.8, 1 and 1.2. Fig. 3.5 shows that allthe elements of the design set K depend very much on both q and d. Forexample, the maximum value of KC for d = 0.8 can be about 4.2 times higherthan the maximum value of KC for d = 1.2; allowing using wider transistors6.Besides, the peak value of the switch voltage, VC(t), for d = 0.8 is observedto be smaller than that for d = 1.2, which is an important feature for Class-EPA design in technologies with low break-down voltages.

In Fig.3.6, normalized output power (U = POUT

IMAXVMAX) is given as a function

of q for d = 0.8, 1 and 1.2. Fig.3.6 shows that U is a strong function of both qand d; U is maximum for d = 1.

6Generally, in Class-E PA design the parasitic output capacitance of the switch (transis-tor) should be smaller than C = KC/(ωR) ; implying that higherKC allows wider transistorswhich increases the drain efficiency due to the associated lower switch-on resistance.

22

d=1.2

d=1

d=0.8

d=0.8

d=1

d=1.2

d=1

d=1.2

d=0.8

d=0.8

d=1.2

d=1

q q

q q

KP KC

KL KX

Fig. 3.5: Elements of the design set KP (q), KC(q), KL(q) and KX(q) as afunction of q for d = 0.8, 1, 1.2

0.06

0.02

0.1

0.08

0.04

21.510.5

0

0.12

q

d=1.2d=1

d=0.8

Fig. 3.6: Normalized Output Power as a function of q for d = 0.8, 1 and 1.2

23

3.5 Waveforms

Section 3.4 showed that the design set K = KL, KC , KP , KX is a functionof q and d therefore, there exist infinitely many Class-E realizations for achosen value of d. Although the switch voltage waveforms of all these Class-Erealizations satisfy (3.1) and (3.2), the Class-E waveforms for different designsets are different. The Class-E waveforms and the implications on Class-Edesign are discussed in this section.

3.5.1 Achievable Waveforms

For different values of q and d, the Class-E waveforms exhibit significantlydifferent peak voltage and peak current values, having their own pros and consin circuit design. Therefore, investigation of Class-E waveforms is importantfrom an application point of view. Implementing a Class-E PA using a singletransistor, as in Fig 3.1a, the following properties of Class-E waveform areimportant:

• the peak value of the switch voltage should be sufficiently low not toexceed the breakdown voltage limits of the transistor.

• the value of the switch current at turn-off moment should be sufficientlylow when the switch (transistor) is driven by a sinusoidal driving signal7.

• the rms value of the switch current8, the inductor, L, current, the capac-itor, C, current and the load current should be low to minimize resistivepower losses.

As mentioned, Fig 3.3 shows that the waveform of the switch voltage and thecurrent strongly depend on d. For d = 0.8 (40%), the peak value of normalizedswitch voltage is about 30% lower than the peak value of switch voltage ford = 1.2 (60%). However, it should also be noted that both the maximumvalue of the switch current and the value of the switch current at the turn-offmoment are much higher for d = 0.8 than for d = 1.2.

Fig 3.7 shows a number of normalized signal waveforms in the Class-EPA as a function of time for different values of q for d = 1 (50%). In thefigure, the switch voltage is normalized with respect to the supply voltage; theswitch current, the load current, the capacitor, C, current and the inductor,L, current are normalized with respect to the dc current (I0).

As q goes from the conventional 1.412 to 2.2 the peak value of the nor-malized switch voltage increases from 3.56 to (approximately) 4. Fig 3.7bshows that for high values of q the switch current, at the moment the switchis opened, increases. Fig 3.7d and Fig 3.7e show that the rms current in thecapacitor, C and inductor also increase rapidly with increasing q.

7For sinusoidal driving signals of the switch (transistor) it is difficult to provide high peakvalues of the switch current when the input driving signal is going to zero [48].

8The on-resistance of the switch (transistor) is usually dominant over other resistivelosses.

24

VC(t

)/V

DD

I S(t

)/I 0

I L(t

)/I 0

I R(t

)/I 0

I C(t

)/I 0

q=2.2q=2

q=1.7q=1.4

q=0 q=2.2

q=2

q=1.7q=1.4

q=0

q=2.2

q=2

q=1.7q=1.4

q=0

q=2.2

q=2

q=1.7q=1.4

q=0

q=2.2

q=2q=1.7 q=1.4

q=0

Fig. 3.7: Normalized (a) switch voltage, (b) switch current (c) load current (d)capacitor, C current (e) inductor, L current for different values of q for d = 1.

25

d=1.2

d=1

d=0.8

q

IS_RMS/I0

Fig. 3.8: RMS value of the normalized switch current IS/I0 as a function of qfor d = 0.8, 1 and 1.2

The relation between q and the normalized load current shows a differentbehavior than that for the capacitor and the inductor current. The lowest rmsvalue of the normalized load current occurs for q ≈ 1.4.

The rms value of the normalized switch current is shown in Fig 3.8 as afunction of q. Fig 3.8 shows that from q = 0 to q = 2 the rms value of thenormalized switch current decreases monotonically; from q = 2 to q = 2.2 therms value of the normalized switch current increases.

It can be concluded from the results obtained above that there is no valueof q that can satisfy all the four points of the ”wish list” above at the sametime. However, depending on the importance of design criteria a reasonablevalue of q can be selected.

3.5.2 Extreme Waveforms

In the infinitely many Class-E solutions, some are very useful while othersappear to be quite impractical because of their extreme waveform behavior.This section discusses the (regions of) most extreme behavior; for simplicityreasons d = 1 assumed. This value corresponds to conventional 50% switchduty-cycle. It was shown in this chapter that any q-value corresponds to aspecific Class-E solution. Extreme behavior occurs for values of q where either

1. p(q, d = 1) → ∞, resulting in ϕ(q, d = 1) = 0The design set K for this condition isKL → ∞, KC = 0, KP = 0, KX → −∞

2. ϕ(q, d = 1) = π/2, corresponding to p(q, d = 1) = π/2.The design set K for this condition isKL → ∞, KC = 0, KP = finite, KX → −∞

26

It can be shown that both of these situations occur once in every range 2n <q ≤ 2n+1 where n = 1, 2, 3... Note that the first extreme Class-E PA has zerooutput power, while the second one has non-zero output power.

For the range 2 < q ≤ 3 the extreme behavior occurs for q = 2.422 andq = 3. Fig 3.9 shows the normalized voltage and the current for these twocases. Fig 3.9a shows that the peak value of the normalized switch current, forq = 2.422, approaches to ±∞ while the peak value of the normalized voltagereaches to 4. Fig 3.9b shows the same voltage and current for the case thatq = 3: the peak value of the voltage reaches to ±∞ whereas the peak value ofthe current is around 3.5.

In the design of Class-E PA, design sets K corresponding to extreme Class-E behavior should be avoided in order not to encounter infinitely high voltagesor currents. Note that while only distinct q-values result in true extremebehavior, a small q-region around the distinct values result in impracticalClass-E behavior.

IS(t)/I0VC(t)/VDD

IS(t)/I0

VC(t)/VDD

Fig. 3.9: Normalized (a) switch voltage and switch current for q = 2.422, (b)switch voltage and switch current for q = 3. For both (a) and (b) d = 1 isassumed.

27

3.6 Design Optimization

In this section, useful examples are given to help engineers in designing Class-Epower amplifiers. The simplified versions of the analytical equations for only50% switch-duty cycle operation given in this section allow the designers todesign Class-E PAs without the need to use the analytical solution. However,by using the analytical solution, it is quite straightforward to derive simpledesign equations for arbitrary switch duty-cycle operation.

Section 3.5.2 discussed Class-E realizations with infinite currents or volt-ages; these infinitely large signals make it impossible to implement these Class-E PAs in any technology. However, also Class-E realizations with finite sig-nals may be not feasible because of technology limits. This section discussesalso practical, technology related, limitations to Class-E realizations. Thetechnology-related limitations taken into account in this section are

• the breakdown limits of the active device (the switch), which sets themaximum value for VDD,

• the minimum value of the parasitic capacitance C, which is determinedby the output capacitance of the active device,

• the minimum value of the load resistance R, which determines (with thequality factor of the components in the output matching network) themaximum acceptable losses of the output matching network,

• the parasitic inductances present in the circuit, which set the lowest valueof inductors that can be used in the Class-E PA, and

• the tolerable physical sizes of passives, which sets an upper bound on thequality factor and maximum value of the reactive components.

Clearly these boundary conditions narrow the useful range of q, by excludingcertain regions of q for a chosen d. The analytical design equations in thischapter enable the selection of the best performing true Class-E PA insidethe remaining design space. A simplified approach as well as an example areprovided in this section.

3.6.1 Simplified Design Equations

The exact analytical expressions are somewhat hard to handle. However, usingthe total design space for Class-E PAs typically is not very useful. A restrictionto values of q that result in reasonable power output for manageable componentvalues and quality factors enables a significant simplification for a chosen valueof d.

In this section d = 1 which corresponds to the traditional 50% duty-cycleoperation; clearly depending on the performance benefits different values of dcan also be chosen and curve fitted by using the analytical solution given inthis chapter. As explained, the switch duty-cycle has important impact on the

28

performance of Class-E PAs especially at high frequency of operation (> 1GHz)[52]. The design space for which output power and component properties arevery well suited for today’s applications and technologies corresponds roughlyto the q-range 0 < q < 1.9 for d = 1.

For this q-range, the exact analytical expressions can easily be fitted to(four) simple polynomial expressions, each covering a part of the range.

1. for the range 0 < q < 0.6 and d = 1the design elements KC , KP , KX don’t change significantly and KL >10. Therefore, in this range the design equations for the RF-choke Class-E PA [31], see Table 3.2, can be used.

2. for the range 0.6 < q < 1 and d = 1the exact results can be fitted reasonably well using second order poly-nomials. The resulting (fitted) design set relations are shown in Table3.2.

Tab. 3.2: Design set for (0.6 < q < 1)

3. for the range 1 < q < 1.65 and d = 1a reasonably accurate fit is presented in Table 3.3.

Tab. 3.3: Design set for (1 < q < 1.65)

4. for the range 1.65 < q < 1.9 and d = 1a reasonably accurate fit is presented in Table 3.4.

Tab. 3.4: Design set for (1.65 < q < 1.9)

29

The difference between the fitted design equations and the exact analyticalrelations is in the order of ≈ 2%. The difference can be further reduced bycurve fitting with higher order of polynomials.

In [47], similar simplified design equations for Class-E PA is obtained byapplying polynomial curve-fitting techniques on the interpolated numericalsolutions for the set K. The technique used in [47] depends on numerical solu-tion methods and the design equations given don’t take into account capacitivevalues for X .

3.6.2 Optimum design sets

The choice for using one of the infinitely many possible design equations de-pends on the boundary conditions imposed by the operating conditions and bythe technology. For example, the maximum output power for given R and VDD

is obtained for q = 1.412 where KP (q, d = 1) reaches its maximum. The cor-responding design set K was already published in e.g. [49] through numericalsolution methods:

Tab. 3.5: Design set for maximum output power

Similarly, for given R and C the maximum operation frequency is reachedat q = 1.468 where KC(q, d = 1) reaches it’s maximum. The design set K formaximum operation frequency is given in Table VI.

Tab. 3.6: Design set for maximum operation frequency

The design equations given in Table 3.4 for 1.65 < q < 1.9 is very useful inthe design of integrated low power Class-E PAs. Mainly, there are two designchallenges for low power Class-E (e.g. Biomedical applications or Low PowerSensors Systems etc. [53], [54]) PAs;

• Low output power with high power-added efficiency (PAE)

• Small size

Two conventional approaches seen in the literature to design low power PAsare either to lower supply voltage [53] or to use a matching network to step-up the 50Ω antenna impedance to higher values in order to lower the output

30

power. The former solution may require DC-DC converter like additionalcircuits increasing size, design complexity and cost while the latter solutionmay decrease the efficiency due to the loss in the matching network dependingon the required impedance transformation ratio [55].

Using the design set in Table 3.4 for 1.65 < q < 1.9 will help to decreasethe output power without the need to resort to methods such as decreasing thesupply voltage or increasing the load resistance. Since POUT = KP V 2

DD/R,decreasing KP nearly to zero as q approaches to 1.9 helps to design low-powerClass-E PAs. Besides, the decrease in the rms value of the switch current for1.65 < q < 1.9 as seen in Fig 3.8 helps decreasing the power loss on the switch;increasing PAE.

Clearly many more optimum design sets can be derived, each optimizing forsome operating condition, for some component value or for some (in)sensitivity.

3.6.3 An Optimization Strategy

In the design phase of a Class-E PA, all the component values must be foundfor some target operating conditions. These operating conditions are in termsof (angular) frequency, output power and supply voltage. In this section, allthe component values and operating conditions are grouped into a set P . Fortrue Class-E operation the component values and operating conditions arelinked together via the design set K(q, d). Note that X may be inductive orcapacitive, depending on the sign of KX(q, d) or on the value of q: for examplefor d = 1 if q < 1.412 then X = ωLX while for q > 1.412 X = − 1

ωCX.

K = KC(q, d), KL(q, d), KP (q, d), KX(q, d)

=

ωCR,ωL

R,POUT R

V 2DD

,X

R

P =

L, R, C, POUT , V 2DD, ω, X

Inspection of the relations for the elements in K, shows that every element inK links three elements of P together; Fig 3.2 shows these relations graphically.In Fig 3.2, each circuit element or input parameter is placed in the corners ofa triangle and the related design set element is shown in the inner part ofthe triangle. In the triangles for KC(q, d), KL(q, d), KX(q, d) two elementsare shared by the other triangles, whereas in KP (q, d) only one element R isshared. Therefore, either VDD or POUT must be known in order to be able tomake a uniquely defined Class-E PA design. At the same time the set P turns

into a smaller set P ′ =

L, R, C, POUT

V 2

DD

, ω, X

.

It can be shown with the help of Fig 3.2 that if any two elements of the setP ′ are known, the rest of the elements can be expressed in terms of q. For achosen d the selection of a proper q, a q-value that satisfies possible boundaryconditions in terms of e.g. component values, then fixes the total design. Thenext subsection presents two optimization examples.

31

3.6.4 Design Examples

This section presents two applications of the analytical design equations tothe circuit design of Class-E PAs. The design flows of these two examples aregiven in Fig 3.10 and Fig 3.11. In each of the flows two elements from P ′ areassumed to be known a priori. The remaining variables then can be expressedin terms of q for a chosen value of d. A suitable q value that satisfies someparticular boundary conditions can easily be selected from the graph, afterwhich the Class-E design is completed.

pre-specified values:

I =1 A

V =1 Vmax

max

0

0.06

0.02

0.1

0.08

0.04

21.510.5

0.12

P =OUT V I U(q,d)max max

d=1.2d=1

d=0.8

PO

UT

q

Fig. 3.10: Design-1, Class-E Design Optimization Flow Chart

The aim in the first design example in Fig 3.10 is to demonstrate a proce-dure to find the maximum output power that can be obtained from a discretetransistor when it is designed as a Class-E PA. In this procedure, a discretetransistor with a certain maximum drain current (Imax = 1A) and drain volt-age (Vmax = 1V) is assumed to be used for Class-E PA design. For poweramplifier designers it is very important to know in advance how much powercan be obtained from a discrete transistor. The maximum output power can bedetermined from the transistor utilization factor (normalized output power),as POUT (q, d) = U(q, d)ImaxVmax. For the chosen duty-cycle a range of q canbe chosen for the desired POUT level. For example, for POUT > 0.08W (shown

32

with arrow in Fig 3.10) q is restricted to the range 0 < q < 1.2 for d = 0.8.

12

10

8

6

4

2

pre-specified values:w = 1G rad/s

P /V = 1W/1VOUT DD

22

0.6 0.8 1.0 1.2 1.4 1.6 1.8

1

0.5

0

-0.5

q

R=K (q)P W

L=K (q)L

C=

K (q)

K (q)/K (q)

X K (q)K (q)

P

C P

X P=

nH

nF

W

LR

C

X

Unknown design parametersas a function of forq d=1

Fig. 3.11: Design-2, Class-E Design Optimization Flow Chart

In the second design given in Fig 3.11, the goal is to design a Class-E poweramplifier with the angular frequency ω, output power and supply voltage are asω = 1 G rad/s, POUT = 1 W and VDD = 1 V respectively. By using the designset K the other design parameters are obtained in terms of q and plotted inFig 3.11. Choosing a value for q finalizes the design. In this example d = 1 isassumed. A suitable q depending on the boundary conditions for the rest ofthe design variables can be chosen to determine all the design parameters. Forexample, the maximum load resistance R = 1.35 Ω is obtained for q = 1.412for which the inductor (L), the capacitor (C) and the excess reactance (X)are 0.99 nH, 0.51 nF and j0 Ω respectively. Depending on the chosen valueof QL the of L0 and C0 can easily be determined and the design is finalized.

As it is seen in both of the design examples the optimization routine makes

33

the design process very straightforward. In fact, once any two elements of the

set P ′ =

L, R, C, POUT

V 2

DD

, ω, X

are given and the design set K is known in

terms of q all the circuit element values can easily be calculated without theneed to understand the details of the derivation procedure.

The two design examples in Fig 3.10 and Fig 3.11 clearly illustrate thatoptima are heavily dependent on both the property to optimize and on the apriori fixed values.

34

3.7 Conclusion

This chapter presents an analytical solution in time domain for the Class-EPA by taking into account both the switch duty-cycle and the finite dc-feedinductance. The analytical solution shows the existence of infinitely manydesign equations for Class-E PAs due to the freedom both in the value ofswitch duty-cycle and in the dc-feed inductance.

By using this analytical solution a non-iterative procedure for choosing thecircuit design parameters for Class-E PAs is presented. The well-known Class-E design equations in literature are specific solutions out of the total Class-Edesign space.

By means of the analytical design equations the waveform characteristicsof Class-E PAs are investigated and a number of trade-offs are discussed. Toenable easy Class-E design, a (non-iterative) design procedure is given thatenables optimization of the Class-E PA under e.g. boundary conditions oncircuit element values and operating conditions. Within this method the extradegrees of freedom associated with the continuum of different Class-E designequations is exchanged for optimization, e.g. reliability increment.

35

Chapter 4

Theory: Class-E PowerAmplifier with Switch-onResistance

4.1 Abstract

This chapter extends the analytical design equations derived in chapter 3 tocover switch-on resistance. Many critical design trade-offs of the Class-E poweramplifier (e.g power efficiency) are influenced by the switch-on resistance andthe value of dc-feed drain inductance. In literature, the time-domain mathe-matical analyses of the Class-E power amplifier with finite dc-feed inductanceassume zero switch-on resistance in order to alleviate the mathematical diffi-culties, resulting in non-optimum designs.

This chapter presents analytical design equations for Class-E power ampli-fiers taking into account both finite drain inductance and switch-on resistance1.The analysis indicates the existence of infinitely many design equations, con-clusions include:

1) Class-E conditions (e.g. zero voltage and zero slope) can be satisfied inthe presence of switch-on resistance.

2) The drain-efficiency (η) of the Class-E power amplifier is upper limitedfor a certain operation frequency and transistor technology.

3) Using a finite dc-feed inductance instead of an RF-choke in a Class-Epower amplifier can increase η by ≈ 30%.

1This section was published in IEEE International Symposium on Circuits and Systems(ISCAS), [5]. Reviewer Comment: As well as I know, it is the first time to analyze a classE amplifier with finite dc-feed inductance and switch-on resistance.

37

4.2 Introduction

The Class-E power amplifier (PA) has been very popular due to it’s highefficiency and the simple circuit structure [30]. However, the ”finite dc-feedinductance” and the ”non-zero switch-on resistance” significantly influence theperformance of the Class-E PAs [52]. To alleviate the analytical complexity,theoretical analyses of the Class-E PA in the literature assumed either non-zero switch-on resistance and infinite dc-feed inductance (RF-choke) [56]- [77]or zero switch-on resistance and finite dc-feed inductance [39]- [41].

It is well-known that using a finite dc feed inductance instead of an RF-choke in Class-E has benefits [39] including:

• a reduction in overall size and cost

• a higher load resistance for the same supply voltage and output power;yielding more efficient output matching networks for PAs with low supplyvoltage and high output power (e.g. handset PAs, base-station PAs etc.)

• larger switch parallel capacitor C (Fig. 4.1a) for the same supply volt-age, output power and load; enabling higher drain efficiency or higherfrequency of operation

LC0

L0 X

R

C

C0L0 X

R

IR

IC

IL

IS

VC

C

I S(t

)/I 0

VC(t

)/V

DD

VDD

VDD

tuned at

Ron

V on

L

C V offC

time

time

Fig. 4.1: (a) Single-ended Class-E PA (b) Model of Class-E PA with finite dc-feed inductance and switch-on resistance (c) Normalized switch (transistor)voltage and current for the model of Class-E PA

38

In order to design Class-E PAs with optimum performance an improved an-alytical model that takes into account both the finite drain inductance andnon-zero switch-on resistance is therefore needed [52].

In [44], the switch-on resistance is taken into account in the design ofClass-E PAs. In [44], the shunt capacitor (C see Fig. 4.1) is assumed to bedisconnected at the switch turn-on moment; which makes the analysis only anapproximation. In [59], the shunt capacitor voltage (VC(t)) is assumed to bezero at the switch turn-off moment; which is not analytically exact and can beaccepted only for very small switch-on resistance (Ron << R).

The analysis and the design approach given in [46] offers no initial designguidelines, which tends to make it tedious because of the inherently largenumber of iterations that are required [57].

Moreover, the design methodologies presented in [60]- [65] either relies oniteration [60]- [64] or assigning initial values to some design variables [65].In [66], an analytical solution for a sub-class of Class-E PA2 is presented.This chapter presents an analysis (time domain) and design equations forClass-E PAs with finite dc-feed inductance and non-zero switch-on resistance.The analysis in this paper is based on closed form expressions similar to thosepresented in the previous chapter. The analysis yields analytical design equa-tions that show the relation between the various design parameters.

4.3 Analytical Analysis of Class-E Power Amplifier

A single ended switching PA topology is given in Fig .4.1a. For correct inputparameters and the circuit element values, the circuit properly operates as aClass-E PA by satisfying the Class-E conditions (4.1) [3]:

VC(2π/ω) = 0 anddVC(t)

dt

∣

∣

∣

∣

t=2π/ω

= 0 (4.1)

The design set K = KL, KC , KP , KX derived in chapter 3, in Table 3.1, forFig. 3.1b can be derived also for Fig. 4.1. The design set K relates circuitelement values to operating conditions such as supply voltage, operating fre-quency and output power for the switching PA. In chapter 3, an analyticalsolution for K is given that enables infinitely many ideal Class-E realizations,to be selected by one parameter q = 1

ω√

LC. In this chapter, one more step

is taken and the switch-on resistance Ron is included in the analysis. As itis shown (later) in this chapter that the design set K can be expressed as afunction of only two parameters q and m = ωRonC both of which are freedesign variables and can take any positive real value.

2The Class-E topology given in [66] assumes zero switch parallel capacitor; which is onlyapplicable for very dedicated technologies with very small RonCout product, where Cout isthe switch (transistor) output capacitance.

39

Table 4.1: Design Set K for Class-E PA3

KL = ωLR

KC = ωCRKP = POUT R/V 2

DD

KX = X/R

As mentioned, the analytical solution in chapter 3 is extended to cover Class-EPAs including RON in this chapter.

4.4 Circuit Description and Assumptions

The circuit model of the Class-E PA is given in Fig. 4.1b. For the analysisand the derivations in this chapter the assumptions in chapter 3 are extendedas follows:

• the only real power loss occurs on R and Ron

• the switch (transistor) operates instantly with on-resistance (Ron) andinfinite off-resistance


• the duty cycle is 50%4

Fig. 4.1c shows the switching behavior and the switch definition used: in thetime interval 0 ≤ t < π/ω the switch is closed and in π/ω ≤ t < 2π/ω it isopened. This switching repeats itself with a period of 2π/ω.

4.5 Circuit Analysis

In the analysis, the current into the load, IR sin(ωt + ϕ), is assumed to besinusoidal as in chapter 3. Note that theoretically this occurs only for infiniteQL of the series resonant network consisting of L0 and C0. It is however awidely used assumption [39], [44] that simplifies analysis considerably:In the time interval 0 < t < π/ω, the switch is closed. The KCL at the drainnode can be written as:

IL(t) − IS(t) − IC(t) + IR sin(ωt + ϕ) = 0 (4.2)

Relation (4.2) can be arranged in the form of a linear, non-homogenous, second

3L0 and C0 seen in Fig. 4.1 can be determined from the chosen loaded quality factor(QL = ω0L0/R) where ω0 = 1/

√L0C0.

4The analysis can be extended easily to cover any duty-cycle by using the analysis in theprevious chapter.

40

order differential equation

LCd2VCon

(t)

dt2+

L

Ron

dVCon

dt+ VCon

− VDD

−ωLIR cos(ωt + ϕ) = 0 (4.3)

which has as solution. Note that in comparison to the equation (3.5), LRon

dVCon

dtappears as an additional term in (4.3).

VCon=

(

q4 sin (ωt + ϕ)m +(

−q2 + q4)

cos (ωt + ϕ))

pVDD

1 + (m2 + 1) q4 − 2 q2

+VDD + eaωtCon2+ ebωtCon1

(4.4)

where, a =−1+

√1−4 q2m2

2m , b =−1−

√1−4 q2m2

2m and p = ωLIR

VDD. Con1

and Con2

follow from the continuity of the capacitor voltage (C) and the inductor (L)current at the switch-on moment.In the time interval π/ω < t < 2π/ω, the switch is opened. Then, in theClass-E PA the current through capacitance C is

IC(t) =1

L

∫ t

π/ω

(VDD − VCoff(t)) dt + IL

(π

ω

)

+ IR(t) (4.5)

Relation (4.5) can be re-arranged in the form of a linear, nonhomogeneous,second-order differential equation

LCd2VCoff

(t)

dt2+ VCoff

(t) − VDD − ωLIR cos(ωt + ϕ) = 0 (4.6)


VCoff(t) = Coff1

cos(qωt) + Coff2sin(qωt) + VDD

− q2

1 − q2pVDD cos(ωt + ϕ) (4.7)

Coff1and Coff2

follow from the Class-E conditions (4.1).It follows from (4.4) and (4.7) that VCon

(t) and VCoff(t) can be expressed

in terms of VDD and ω hence be solved analytically only if ϕ, q, p and m areknown. The derivation of the four parameters ϕ, p, q and m is the next stepin the solution.

By using the continuity of the inductor current and the capacitor voltageat the switch turn-off moment we can derive two independent equations whichcan be shown to have the same format:

fi(p, q, ϕ, m) = p(

ai(q, m) cos(ϕ) + bi(q, m)sin(ϕ))

+ ci(q, m) = 0, where

i = 1, 2.The variables p and ϕ can be solved by using f1(p, q, ϕ, m) and f2(p, q, ϕ, m)in terms of q and m as given in Appendix-B. Here, q and m are free variablesthat can mathematically take any positive real value.

41

4.6 Design sets for Class-E operation

The results of the mathematical derivation of the solutions leading to Class-Eoperation can be used to derive an an easy-to-use design procedure for Class-E PAs. Using the result of the derivation for p(q, m) and ϕ(q, m), analyticalexpressions for the design set K = KL, KC , KP , KX can readily be derived.

KP

KC

KL

KX

Dra

in E

ffic

ien

cy (

)h

o

m=0

m=

0.1

m=0.2m=0

m=0.1

m=0.2

m=0m=0.1

m=0.2

m=0

m=0.1 m=0.2

m=0

m=0.1

m=0.2

q

q

q

q

q

Fig. 4.2: (a) Design set K = KL, KP , KC , KX and drain efficiency (η) as afunction of q for m = 0, 0.1, 0.2

KL : follows from the principle of power conservation:

I2RR/2 + Pswitch = I0VDD (4.8)

42

In this relation, I0 is the average supply current:

I0 =ω

2πRon

∫ π/ω

0

VCon(t)dt (4.9)

and,

Pswitch =ω

2πRon

∫ πw

0

(VCon(t))

2dt

Substitution of (4.9) and p in (4.8) yields

KL(q, m) =−(pVDDq)2mπ

ω∫ π

w

0 (VCon(t)

2 − VDDVCon(t))dt

Since p and ϕ are all functions of q and m, KL(q) is a function of e.g. only qand m.KC: follows directly from the definition of q and KL:

KC(q, m) =1

q2KL(q, m)

KP: can easily be found as a function of q and m by using IR =√

2POUT /Rand the definition of p:

KP (q, m) = p(q, m)2/(2KL(q, m)2)

KX: can be derived using two fundamental quadrature Fourier componentsof VC(t).

VR =

∫ πω

0

VCon(t)

πsin(ωt + ϕ) dt +

∫ 2πω

πω

VCoff(t)

πsin(ωt + ϕ) dt

VX =

∫ πω

0

VCon(t)

πcos(ωt + ϕ) dt +

∫ 2πω

πω

VCoff(t)

πcos(ωt + ϕ) dt

KX(q, m) = VX/VR

Drain efficiency(η): can be derived as a function of q and m.

η(q, m) = 1 − Pswitch

VDDI0= 1 −

∫ πw

0 (VCon(t)

2)dt

VDD

∫ πω

0VCon

(t)dt

We verified the given design equations in this chapter by simulating themodel given in Fig. 4.1b by transient and pss (periodic steady state) simula-tions in Spectre (Cadence). Very good agreement in the waveforms and thedrain efficiency are observed between the simulations and the theory with adiscrepancy of ≈ 2%; attributed to the finite value of QL = 10.

43

Design Details q=0 q=1.47 q=1.78

f(GHz) 2.4 2.4 2.4VDD(V) 0.5 0.5 0.5

QL 2.4 0.5 10

POUT /PDC (mW) 10.6/22.2 11.8/17.0 12.1/15.2m 0.1 0.1 0.1

Drain Efficiency(η) 47.7% 69.4% 79.6%L 20.29 0.72 0.4

LX(nH) 0.38 0 -C(pF) 2.59 2.82 3.48R(Ω) 3.06 19.47 5.06

CX(nF) - - 6.88(W(u)/L(u)) 297/0.1 323/0.1 398/0.1

KL 100 0.56 1.19KC 0.12 0.83 0.27KP 0.12 0.83 0.20KX 1.89 0 -1.90

Technology 90nm CMOS 90nm CMOS 90nm CMOS

Table 4.2: Comparison and design summary of the three Class-E PA designsfor m = 0.1 and q = 0, 1.47, 1.78 in CMOS 90nm transistor technology

In theory, q can take any positive real number however, as it is seen in Fig.4.2 KC , KP and η approach zero for q > 2. Therefore, the useful range of theanalytical solution can be assumed to be restricted to 0 < q < 2 in Class-EPA designs. Similarly, as m increases KP and η drops as observed in Fig. 4.2;indicating the degradation in Class-E PA performance.

4.7 Design Examples and Discussion

The analytical design equations reveal very important properties of the Class-E PAs. For example, we can express m ≈ βω where β = RonCout. β is acharacteristic property of the transistor technology used as a switch in Class-E PA design5. For a certain operation frequency and transistor technology mhas a certain value. As it is seen in Fig. 4.2, there is a maximum efficiency levelthat could be achieved for a given m; showing that the transistor technologyand the frequency of operation sets an upper limit for η of a Class-E PA.

The chosen value of q considerably influence η as observed from Fig. 4.2and the simulation results given in Table-4.2. We designed three Class-E PAsfor an output power of 10mW6. Finite dc-feed Class-E PA(q=1.78) has η that

5In order to minimize Ron, maximum possible transistor size can be chosen for whichtransistor output capacitance Cout = C.

6Slightly higher output power than 10mW is attributed mostly to deviation of transistor

44

is ≈ 30% higher than RF-coke Class-E PA(q = 0); indicating how much η canbe influenced by the chosen design equations.

Although the Class-E PA(q = 1.47) has lower η than the Class-E PA(q =1.78) it’s load resistance(R) is ≈ 4 times higher than that of the Class-EPA(q = 1.78); which is very advantageous for low supply voltage - high outputpower Class-E amplifiers7

The Class-E PA(q = 1.78) can be used for low power applications (e.g.wireless sensors) where the transmit power levels are low ≈ (1 − 3)mW [53]and high efficiency is crucial. If the Class-E PA(q = 1.78) is designed for anoutput power of 1mW , it needs R ≈ 50Ω; meaning that a matching networkbetween the PA and the antenna is not needed.

characteristic from an ideal switch behavior at high frequency.7In order to obtain high output power from low supply voltage Class-E PAs a matching

network that steps down 50Ω antenna impedance to low impedance values is used. In theabsence of high Q inductors the matching network can be very lossy for high transformationratios.

45

4.8 Conclusion

In this chapter, we present a time domain analysis and closed form analyticaldesign equations for Class-E power amplifiers with finite dc-feed inductanceand non-zero switch-on resistance. Important outcomes of the analysis include:

1) Class-E conditions (e.g zero voltage and zero slope) can be satisfied inthe presence of the switch-on resistance.

2) Drain efficiency (η) for Class-E PAs is upper limited by the transistortechnology and the operation frequency.

3) Using a finite dc-feed inductance instead of an RF-choke in Class-EPAs increases η. Depending on the transistor technology and the operationfrequency the increase in η can be as high as ≈ 30%.

46

Chapter 5

Theory: Sub-optimumOperation of Class-EPower Amplifiers

5.1 Abstract

In this chapter, we extend the analytical solutions for the Class-E power ampli-fier to the ideal single-ended Variable Slope Class-E (Class-EV S) and VariableVoltage Class-E (Class-EV V ) power amplifier.

Class-EV S switches at zero voltage but not necessarily at zero slope. Itis shown in this chapter that a Class-EV S power amplifier can have highertolerance to switch (transistor) output capacitance compared to the normalClass-E power amplifier. The higher tolerance can be exchanged for higherdrain efficiency or reliability. The presented design equations for Class-EV S

power amplifiers give more degrees of freedom in the design and optimizationof switching RF power amplifiers.

Class-EV V switches at zero slope but not necessarily at zero voltage. Itis shown in this chapter that the peak switch voltage of Class-EV V poweramplifier is lower (up to ≈ 30% ) than in the conventional Class-E poweramplifier, which can be utilized to obtain e.g. higher output power (up to≈ 200% more) with lower power-added efficiency (maximum ≈ 20% less) fromtechnologies with low-breakdown voltages. By using a first-order RF reliabilitysimulation methodology where the oxide breakdown and hot-carriers are bothtaken into account it is shown that Class-EV V mode of operation can increasethe overall life-time of the power amplifier.

Another very important advantage of the analytical design equations ofsub-optimum operation of Class-E is to reveal some modes of variable slopeoperation that could cause reliability issues. For example, some sub-optimummodes of operation increases the peak drain voltage much higher than the

47

nominal value which may be destructive for the switch (transistor). Using theanalytical design equations from this chapter, such modes can be avoided.

5.2 Introduction

The Class-E power amplifier (PA) can achieve high efficiency due to its tunedload network that shapes the switch voltage to zero-voltage and zero-slopeat the switch turn-on moment. Many different aspects of the Class-E poweramplifier (PA) have been extensively studied in the last three decades [4]- [77].The reportedly ”sub-optimum operation” with nonzero-voltage or nonzero-slope switching [31] is hardly used because of its believed inferior performance[77].

This chapter presents analytical design equations based on closed formexpressions, similar to those presented in chapter 3 and chapter 4, for VariableSlope Class-E (Class-EV S) PAs and Variable Voltage Class-E (Class-EV V )PAs, Fig. 5.1.

Section 5.3 presents an analysis and some discussions on Class-EV S PAswith finite dc-feed inductance to utilize their increased tolerance to switch(transistor) output capacitance. Class-EV S switches at zero voltage but notnecessarily at zero slope. Analytical design equations are derived showing therelation between the various design parameters1. It is shown in section 5.3that Class-EV S with finite dc-feed inductance can have very high tolerance toswitch (transistor) output capacitance (≈ 110% more than Class-E with finite-dc feed inductance and ≈ 680% more than Class-E with an RF-choke) allowingusing large transistors hence yields higher drain efficiency than conventionalClass-E PAs. Besides, the switch voltage of the Class-EV S PA for negativeturn-on slopes resembles to a half-sinusoid and lower peak value than that ina conventional Class-E PA which is beneficial for reliability.

Single Ended Switching Power Amplifier

Variable Slope Class-E Variable Voltage Class-E

Class-E

Fig. 5.1: Operation classes of single ended switching PA

1Section 5.3 was published in IEEE International Conference on Electronics, Circuits andSystems (ICECS), [4].

48

Section 5.4 presents an analysis and some discussions on Class-EV V PAs toutilize their lower peak switch voltage feature to obtain higher output powerwith reasonably high power-added efficiency from transistor technologies withlow-breakdown voltages2. Class-EV V switches at zero slope but not necessarilyat zero voltage. In the analysis, the finite dc-feed inductance, L, the switch(transistor) input/output capacitance, Cin/Cout, and on-resistance, Ron, (Fig.5.2b) are all taken into account. As a result of the analysis, analytical designequations are presented showing the relation between the input parametersand the circuit component values. It is shown in this section that Class-EV V

can have up to 30% lower peak switch voltage than conventional Class-E PAs;which can be used to obtain up to 200% more output power with maximumabout 20% lower power-added efficiency3 assuming the same transistor size,reliable peak voltage, matching network and driver.

Section 5.5 presents reliability simulation results using a first-order RF reli-ability simulation methodology which takes into account the oxide breakdownand hot-carriers [18]. According to simulation results, Class-EV V mode of op-eration can increase the overall life-time of the power amplifier significantly.

2Section 5.4 was published in IEEE International Microwave Symposium (IMS), [6].3Power is lost due to discharging of the capacitor (C) to ground via the switch at the

switch turn-on moment.

49

5.3 Variable Slope Class-E Power Amplifiers (Class-EV S)

LC0

L0 X

RC

LC0

L0 X

R

VDD

VDD

C

RON

IS(t)/I0

VC(t)/VDD

VC

dVC(t)/dt=1.5

dVC(t)/dt=0

dVC(t)/dt=-1.5

k=-1.5

k=0

k=1.5k=-1.5

k=0

k=1.5

Fig. 5.2: (a) Single-ended Class-EV S PA (b) Model of Class-EV S PA (c) Switchvoltage normalized to VDD and switch current normalized to supply dc current,I0, of Class-EV S PA with finite dc-feed inductance with the turn-on slope ofk = −1.5, k = 0(Class-E) and k = 1.5

5.3.1 Analysis of Class-EV S Power Amplifier

A single ended switching PA topology is given in Fig. 5.2. If the correct inputparameters and the circuit element values are chosen, the circuit properlyoperates as a Class-E PA by satisfying the following conditions (5.1) and (5.2)[31], [77]:

VC(2π/ω) = 0 (5.1)

dVC(t)

dt

∣

∣

∣

∣

t=2π/ω

= ωVDDk (5.2)

where ωVDDk is the slope of VC(t) at the moment the switch is closed. Forconventional Class-E operation k = 0. However, in Class-EV S operation k isa real value that can be selected freely and therefore gives a degree of freedomin the design of a Class-EV S PA. For k = 0, (5.1) and (5.2) are the well-knownconventional Class-E conditions from which it follows that conventional Class-E operation is a special case of general Class-EV S operation.

For the switching PA in Fig. 5.2a a design set K = KL, KC , KP , KX,as in chapter 3 and chapter 4, can be derived that relates circuit elementvalues and operating conditions such as supply voltage, operating frequencyand output power. In chapter 3 and chapter 4, an analytical solution is giventhat enables infinitely many ideal Class-E realizations, to be selected by oneparameter q = 1/(ω

√LC). The expressions for the elements in the design set

50

K are given in Table 5.1; the values of the elements (as a function of q) arepresented in chapter 3 for conventional Class-E operation.

Table 5.1: Design Set K for Class-EV S PA4

KL = ωLR


DD

KX = X/R

In this chapter, the analytical solution in chapter 3 is extended to cover Class-EV S PAs as well. Therefore, an analytical solution for the design set K isderived which also allows a non-zero slope of the switch voltage at the turn-onmoment of the switch; the slope is here defined by the value for k. This sectionpresents the derivation of the design set K for Class-EV S PAs.


The circuit schematic of the Class-EV S PA is given in Fig. 5.2a. For theanalysis and derivations in this chapter a number of assumptions are made:

• the only real power loss in the circuit occurs on load R

• the switch (transistor) is lossless, operating instantly with zero on-resistanceand infinite off-resistance5


• the duty cycle is 50%

Fig. 5.2b illustrates the switching behavior and the switch definition usedhere: in the time interval 0 ≤ t < π/ω the switch is closed and in the timeinterval π/ω ≤ t < 2π/ω it is opened. This switching action repeats itself witha period of 2π/ω.


In the analysis, the current into the load, IR sin(ωt + ϕ), is assumed to besinusoidal with the same assumption of simplifying the analysis as in chapter3 and chapter 4. In the time interval 0 < t < π/ω, the switch is closedand hence the capacitance voltage VC(t) = 0 and the current through the

4L0 and C0 seen in Figure 5.2 can be determined from the chosen loaded quality factor(QL = ω0L0/R) where ω0 = 1/

√L0C0.

5Note that non-zero switch on resistance RON can be easily included as a design param-eter as in chapter 4.

51

capacitance IC(t) = C · dVC(t)/dt = 0. In this time interval, the switchcurrent IS(t) is

IS(t) = IL(t) + IR sin(ωt + ϕ)

=VDD

Lt − IL(0) + IR sin(ωt + ϕ) (5.3)

where IL(0) = C · ωVDDk − IR sin(ϕ)

In the time interval π/ω < t < 2π/ω, the switch is opened. Then, in theClass-E PA the current through capacitance C is

IC(t) =1

L

∫ t

π/ω

(VDD − VC(t)) dt + IL

(π

ω

)

+ IR(t) (5.4)

Relation (5.4) can be re-arranged in the form of a linear, nonhomogeneous,second-order differential equation after substituting IC(t) as C ·dVC(t)/dt anddifferentiating both sides with respect to t.

LCd2VC(t)

dt2+ VC(t) − VDD − ωLIR cos(ωt + ϕ) = 0 (5.5)


VC(t) = C1 cos(qωt) + C2 sin(qωt) + VDD − (5.6)

q2

1 − q2pVDD cos(ωt + ϕ)

where q = 1/(ω√

LC) and p = ωLIR/VDD. The coefficients C1 and C2 followfrom the initial off state conditions, VC(π/ω) = 0 and IL(π/ω) = VDD

ωL (π −p sin(ϕ) + k

q2 ) similar to 3.10 and 3.11.

It follows from (5.3) and (5.7) that VC(t) and IS(t) can be expressed interms of VDD and ω only if ϕ, q, p and k are known. The variable k is alreadydefined as a free variable that can take real numbers. The derivation of thethree parameters ϕ, q and p is the next step in the derivation.

To derive expressions for the three unknowns so far, ϕ, q and p, threeindependent equations are required. For this, the two basic Class-EV S equa-tions (5.1) and (5.2) can be used, together with some other equation. A suit-able extra equation can be based on stationary behavior of Class-EV S PA:VL(t) = |constant| and VC(t) = |constant|. Working out the latter for station-ary behavior yields

VDD =ω

2π

∫ 2π/ω

0

VC(t) dt (5.7)

With (5.7), (5.1) and (5.2) three non-linear equations with unknowns ϕ, q, pand the free variable k are obtained. These three equations can be arrangedin the same form:

52

fi(p, q, ϕ, k) = p(

ai(q, k) cos(ϕ) + bi(q, k)sin(ϕ))

+ ci(q, k) = 0, where i =

1, 2, 3.Solving the non-linear set of the equations for ϕ, q and p is now more or lessstraightforward. For example, f1(p, q, ϕ, k) and f2(p, q, ϕ, k) can be used tosolve p and ϕ in terms of q and k. If the obtained expressions for p(q, k)and ϕ(q, k) are substituted in f3(p, q, ϕ, k) it can be seen that f3(q, k) = 0independent of q and k; which proves that the obtained expressions for p(q, k)and ϕ(q, k) are the analytical solution of the system of equations. For everyreal value q and k there is a solution for p and ϕ.

(p(q, k), ϕ(q, k)) =

(p1(q, k), ϕ1(q, k)) if q > 1(p2(q, k), ϕ2(q, k)) if q < 1

where,

ϕ1(q, k) = arctan(ϕa(q, k), ϕb(q, k))

ϕ2(q, k) = − arctan(ϕa(q, k),−ϕb(q, k))

ϕa(q, k) = (qπ sin (qπ) + 2 − 2 cos (qπ)) q sin (qπ)

ϕb(q, k) =(

4 − 2 sin (qπ)2 − 4 cos (qπ)

)

q2 +

q sin(qπ)(

(cos(qπ) − 1)(2k + π))

−4 + 2 sin (qπ)2

+ 4 cos (qπ)

p1(q, k) = −p2(q, k)

p1(q, k) = x0

√

(

x1 + x2q + x3q2 + x4q3 + x5q4)

x0 =(q + 1)(q − 1)

2 sin(qπ)2q4

x1 = 4(

sin(πq)2(

sin(πq)2 + 4 cos(πq) − 8)

+

8(1 − cos(πq)))

x2 = 4(2k + π) sin(πq) ·(

(cos(πq) − 3) sin(πq)2 + 4(1 − cos(πq)))

x3 =(

−π2 − 12)

sin (πq)4 − 64 + 64 cos (πq) +

(

−2 π2 cos (πq) + 2 π2 + 72 − 40 cos (πq))

sin (πq)2

x4 = 8 sin (πq)3(

(− cos (πq) + 3) k + π (2 − cos (π q)))

+16(cos(πq) − 1) sin(πq)(2k + π)

x5 =(

π2 + 4)

sin (πq)4

+ 32 − 32 cos (πq) +

(16 cos (πq) − 32) sin (πq)2

53

5.3.4 Design sets for Class-EV S operation

The results of the complex mathematical derivation of the (infinitely many)solutions leading to Class-EV S operation can be simplified considerably, yield-ing an easy-to-use design procedure for general Class-EV S PAs. In the pre-vious subsection it was mentioned that p and ϕ both can be solved as afunction of q and k. Using the relations for ϕ, p, q and k, design setsK = KL, KC , KP , KX can readily be derived.

k=1.5

k=-1.5

k=0

k=-1.5

k=1.5

k=0

k=-1.5k=1.5

k=0

k=1.5

k=-1.5k=0

q q

q q

1.5

1.25

1.0

0.75

0.5

0.25

0.0

1.5

1.25

1.0

0.75

0.5

0.25

0.0

20

15

10

5

00.8 1.2 1.6 2.0 0.5 1.0 1.5 2.0

0.5 1.0 1.5 2.00.5 1.0 1.5 2.0

5

0

-5

-10

-15

capacitive

inductive

KP

KL KX

KC

Fig. 5.3: Elements of the design set KP (q), KC(q), KL(q), KX(q) as a functionof q for different values of k

KL : The expression for KL can be derived by using the assumption in 5.8:

I2R

R

2= I0VDD (5.8)


I0 =ω

2π

∫ 2π/ω

0

IS(t) dt

=IR

2π

(π2

2p+ 2 cos(ϕ) − π sin(ϕ) +

kπ

q2p

)

(5.9)


KL(q, k) =p(q, k)

π2p(q,k) + 2 cos(ϕ(q,k))

π − sin(ϕ(q, k)) + kπq2p

(5.10)

54

Since p and ϕ both are functions of q and k, KL(q, k) is a function of only qand k.KC: KC follows directly from the definition of q and (5.10):

KC(q, k) =1

q2KL(q, k)(5.11)

KP: An expression for KP as a function of p and q can easily be found usingIR =

√

2POUT /R and the definition of p:

KP (q, k) =1

2

p(q, k)2

KL(q, k)2(5.12)

KX: An analytical expression for KX can be derived using two fundamentalquadrature Fourier components of VC(t).

VR =1

π

∫ 2π/ω

0

(VC(t) sin(ωt + ϕ)) dt

VX =1

π

∫ 2π/ω

0

(VC(t) cos(ωt + ϕ)) dt

KX(q, k) =VX

VR

The values for KL, KC , KP and KX are plotted in Fig. 5.3 as a functionof q for certain k values. KC for finite dc-feed Class-EV S (q=1.35,k=-1.5)is about 2.1 times larger than for finite dc-feed Class-E (q=1.41,k=0) andabout 7.8 times larger than for RF-choke Class-E (q=0,k=0). The analyticaldesign equations were verified with transient and periodic steady state (pss)simulations (Spectre) by using an (almost) ideal switch with very low on resis-tance (RON << R). Good agreement in the waveforms are observed betweensimulations and the theory with a difference less than 4%. The difference isattributed to finite QL=20 and non-zero RON .

5.3.5 Comparison and Design Example

A very important performance criteria for switching PAs is the drain efficiency(η). In this section, we compare η for Class-E PA and Class-EV S PA by takinginto account two crucial conditions in switching PA designs:

a) the peak switch voltage must not exceed the switch (transistor) break-down voltage (VBD),

b) the switch output capacitance (COUT ) must be smaller than C.Existence of a small switch-on resistance (RON ) is assumed which causes asmall power consumption (Pcond ≈ I2

RMSRON ) but doesn’t influence the volt-

55

age and the current waveforms6. Taking into account these assumptions, thedrain efficiency can be expressed as7:

η =PDC − Pcond

PDC= 1 − RON

VDD

I0

(IRMS

I0)2

= 1 − F 2I

RON

KP V 2

DD

POUT

= 1 − F 2I F 2

V

KP· RON

V 2BD

· POUT (5.13)

= 1 − F 2I

KC· β2 · ω2 (5.14)

where FV = VBD

VDD, FI = IRMS

I0and β = RONCOUT .

(a) (b)

FI

2 2F /KV P

FI

2/KC

k=0

k=-1.5k=1.5

k=1.5

k=0

k=-1.5

q q

Fig. 5.4: Loss-factors (a) (F 2

I F 2

V

KP) for limited size transistor Class-EV S and (b)

(F 2

I

KC) for freely chosen size transistor Class-EV S PA

(5.14) is derived from (5.13) with the assumption that COUT = C. In(5.13), the term F 2

I F 2V /KP is dependent on the tuning strategy while RON/V 2

BD

and POUT are dependent on the transistor technology and the given designspecs respectively. Similarly, in (5.14) the term F 2

I /KC is dependent on thetuning strategy and the terms β2 and ω2 are dependent on the transistor tech-nology and the design specs respectively. Therefore, it is possible to comparethe drain efficiency of Class-EV S and Class-E PAs by using (5.14) and (5.13)

6IRMS is the rms value of the switch current.7While this approach to efficiency calculation is not expected to predict η with great

accuracy, it is very useful to compare the different classes of PA’s performance as it is usedby [76] to compare Class-E and Class-E/F PAs.

56

Design Details Class-E Class-EV S Class-EV S

(q,k) (1.41,0) (1.35,-1.5) (1.35,-1.5)

Frequency 40 GHz 40GHz 40GHz

POUT 70.8mW 110.9mW 59.2mW

PDC 101.2mW 127.6mW 107.9mW

η 69.9% 86.9% 54.9%

KP , KC , 1.365, 0.685, 1.245, 1.437, 1.245, 1.437,

KL, KX 0.732, 0 0.382, -0.163 0.382, -0.163

L, C, 29pH, 0.27pF, 15pH, 0.57pF, 15pH, 0.57pF,

R, CX 9.22 Ω, → ∞ 10 Ω, 2.45pF 10 Ω, 2.45pF

W/L 0.63mm/0.1u 1.32mm/0.1u 0.63mm/0.1u

Technology CMOS 90nm CMOS 90nm CMOS 90nm

VDD 0.917V 1V 1V

QL 20 20 20

Table 5.2: Comparison and design summary for Class-E and Class-EV S PAs

assuming that the technology and the design specs are the same. For the de-signs where the device size is limited8 to well below the theoretical maximumsize C (5.13) can be used to evaluate the drain efficiency whereas for the de-signs for which the device size can be chosen freely large (5.14) can be usedfor drain efficiency comparison.

In Fig. 5.4, the loss-factors (F 2I F 2

V /KP , F 2I /KC) for Class-EV S are plotted

for 0.65 < q < 1.7 and k = −1.5, 1.5 and k = 0 (Class-E). It is seen in Fig.5.4a that the loss factor F 2

I F 2V /KP for limited device case is the lowest for

k = 0 (Class-E). For the case in which the optimal transistor size is freelychosen, k = −1.5 (Class-EV S) has 19% lower loss factor (F 2

I /KC) than k = 0(Class-E). The conclusions derived from Fig. 5.4 are verified by simulating(Spectre) three PAs designed in 90nm CMOS technology. The condition b)and C = KC/(ωR) show that the maximum allowed switch (transistor) sizedecreases as ω increases. As it is given in Table-5.2, in the second columna Class-E PA is designed at a very high frequency on purpose so that C istotally made from the switch (transistor) output capacitance. A Class-EV S

PA operating at the same frequency is designed as seen in the third column ofTable-5.2. Since Class-EV S PA has a higher C (2.1 times) a larger transistorwidth (2.1 times) is used thus a higher η is obtained as seen in Table-5.2;which is supporting the theoretical result given in (5.14). In the third column,

8this may occur at low frequencies where the maximum size is excessively large or fortechnologies where large devices are prohibitively expensive [76].

57

the switch (transistor) for Class-EV S PA is reduced to the same size as in theClass-E PA and lower efficiency than for the Class-E PA is obtained; which issupporting the theoretical result in (5.13).

58

5.3.6 Conclusion

In this section, we have presented the analytical solution for Class-EV S PAwith finite dc-feed inductance. Based upon the analytical solution, analyticaldesign equations for Class-EV S PA with finite dc-feed inductance are given;which expands the design space of switching PAs. The given design equationswere verified with simulations.

The tolerance to the switch (transistor) output capacitance for Class-EV S

PA with finite dc-feed inductance can be about 2.1 times more than Class-E PA with finite dc-feed inductance and about 7.8 times more than Class-EPA with RF-choke. Therefore, Class-EV S PA allows bigger switch (transistor)resulting in higher drain efficiency in comparison to Class-E PA. Besides, cer-tain modes of variable slope operation causing important reliability concernby increasing the peak drain voltage9 can be prevented by using the analyticaldesign equations.

9Such modes of variable slope operation, k > 0 may occur as a result of antenna mismatchor spread in the value of the components etc.

59

5.4 Variable Voltage Class-E Power Amplifiers(Class-EV V )

LC0

L0

R+jX

Lm

Cm

R0+Rm

Lm

Cm

C0L0

RL

RL

L

Cou

t

Pantenna

Pmatch

Pswitch

Pin

VDD

VDD

C

CCin

IR

IC

IL

IS

VDD,driver

2VDD,driver

Rd Ld

Ld

RON

VC

0

VC(t

)/V

DD

I S(t

)/I 0

VonVoffC C

Fig. 5.5: (a) Class-EV V PA including driver and matching network (b) Modelof Class-EV V PA (c) Normalized switch voltage and switch current of Class-EV V PA with turn-on voltage of α = 2, α = 0 (Class-E) and α = 1

5.4.1 Analysis of Class-EV V Power Amplifier

A single ended switching PA topology and its model are given in Fig. 5.5aand Fig. 5.5b respectively. An analytical solution for the model in Fig. 5.5bto operate as a Class-E PA (e.g. switching at zero-voltage and zero-slope) isgiven in chapter 3 and chapter 410. In section 5.1, switching with variable slopeaspect was generalized and analytical design equations for Class-EV S (e.g.switching at zero-voltage and variable-slope) is given. In the current section,the variable voltage aspect is generalized and general analytical solution forClass-EV V (e.g. switching at variable-voltage and zero-slope) is given basedon the model in Fig. 5.5b. If the correct input parameters and circuit elementvalues are chosen, the circuit in Fig. 5.5a properly operates as a Class-EV V

PA by satisfying the following conditions (5.15):

VC(2π/ω) = αVDD anddVC(t)

dt

∣

∣

∣

∣

t=2π/ω

= 0 (5.15)

where αVDD is the voltage of VC(t) at the moment the switch is closed; forconventional Class-E operation α = 0. However, in Class-EV V operation α is a

10Note that the analysis in chapter 3 is extended in chapter 4 by taking into account anon-zero switch-on resistance.

60

real value11 that can be selected freely and therefore gives a degree of freedomin the design of a Class-EV V PA. A design set K = KL, KC , KP , KX , KR(Table-5.3) can be derived that relates circuit element values and operatingconditions such as supply voltage, operating frequency and output power forthe switching PA in Fig. 5.5a. In this section, closed form analytical expres-sions for each element of the Class-EV V are derived; which enables infinitelymany Class-EV V realizations, to be selected by the parameters q = 1/(ω

√LC),

m = ωRonC (chapters 3, 4, 5.1) and α. The design parameters q and m are freevariables like α and mathematically can be assigned any positive real value12.

Table 5.3: Design Set K for Class-EV V PA13

KL = ωLR


DD

KX = X/R

This section presents the derivation of the design set K for Class-EV V PAs.


The circuit model of the Class-E PA is given in Fig. 5.5b. For the analysisand the derivations in this section a number of assumptions are made:

• the only real power loss occurs on RL, Ron, Rd, R0 and Rm.

• The capacitors Cin and Cout are assumed to be linear.

• the switch (transistor) operates instantly with on-resistance (Ron) andinfinite off-resistance


• the duty cycle is 50%14

Fig. 5.5c shows the switching behavior and the switch definition used: in thetime interval 0 ≤ t < π/ω the switch is closed and in π/ω ≤ t < 2π/ω it isopened. This switching repeats itself with a period of 2π/ω.

11Theoretically, α < 0 is possible however, for MOS type of switches the junction diodesget forward biased when α < 0; decreasing efficiency.

12Although mathematically q, m can be assigned any positive real value and α can beassigned any real value, as it is shown (later) that only certain ranges results in designequations that are feasible in practice.

13L0 and C0 seen in Fig. 5.5a can be determined from the chosen loaded quality factor(QL = ω0L0/R) where ω0 = 1/

√L0C0.

14Note that the duty-cycle information can be easily included in the analysis as a designparameter as in chapter 3. Here 50% duty-cycle is chosen for the sake of simplicity of theanalysis

61


In the analysis, the current into the load, IR(t), is assumed to be sinusoidal.IR(t) = IR sin(ωt + ϕ)

In the time interval 0 < t < π/ω, the switch is closed. The KCL at the drainnode can be written as:

IL(t) − IS(t) − IC(t) + IR(t) = 0 (5.16)

Relation (5.16) can be arranged in the form of a linear, non-homogenous,second order differential equation

Cd2VCon

(t)

dt2+

1

Ron

dVCon

dt− VDD − VCon

L

−ωIR cos(ωt + ϕ) = 0 (5.17)


VCon=

q4 sin (ωt + ϕ)m −(

q2 − q4)

cos (ωt + ϕ)

1 + (m2 + 1) q4 − 2 q2pVDD

+VDD + eaωtCon2+ ebωtCon1

(5.18)

where, a =−1+

√1−4 q2m2

2m , b =−1−

√1−4 q2m2

2m and p = ωLIR

VDD. Con1

and Con2

follow from the continuity of the capacitor voltage (C) and the inductor (L)current at the switch-on moment.In the time interval π/ω < t < 2π/ω, the switch is opened. Then, in theClass-EV V PA the current through capacitance C is

IC(t) =1

L

∫ t

π/ω

(VDD − VCoff(t)) dt + IL

(π

ω

)

+ IR(t) (5.19)

Relation (5.19) can be re-arranged in the form of a linear, nonhomogeneous,second-order differential equation

LCd2VCoff

(t)

dt2+ VCoff

(t) − VDD − ωLIR cos(ωt + ϕ) = 0 (5.20)


VCoff(t) = Coff1

cos(qωt) + Coff2sin(qωt) + VDD

− q2

1 − q2pVDD cos(ωt + ϕ) (5.21)

Coff1and Coff2

follow from the Class-EV V conditions (5.15).It follows from (5.18) and (5.21) that VCon

(t) and VCoff(t) can be expressed

in terms of VDD and ω hence be solved analytically only if ϕ, q, p, m and α

62

are known. The derivation of the four parameters ϕ, p, q, m and α is the nextstep in the solution.

By using the continuity of the inductor current and the capacitor voltageat the switch turn-off moment two independent equations follow that have thesame format:

fi(p, q, ϕ, m, α) = pai(q, m, α) cos(ϕ) + pbi(q, m, α)sin(ϕ)

+ci(q, m, α) = 0, where i = 1, 2

The variables p and ϕ can be solved by using f1(p, q, ϕ, m, α) and f2(p, q, ϕ, m, α)in terms of q, m and α as given in the appendix. Here, q, m and α are freevariables that can mathematically take any positive real value.

5.4.4 Design sets for Class-EV V operation

The results of the mathematical derivation of the solutions leading to Class-EV V operation can be used to derive an easy-to-use design procedure for Class-EV V PAs. Using the result of the derivation for p(q, m, α) and ϕ(q, m, α), ana-lytical expressions for the design set K = KL, KC , KP , KX , KR can readilybe derived.

KL : follows from the principle of power conservation:

I2RR/2 + Pswitch = I0VDD (5.22)


I0 =ω

2πRon

∫ π/ω

0

VCon(t)dt (5.23)

and Pswitch is the power spent on Ron:

Pswitch =ω

2πRon

∫ πw

0

VCon(t)2dt


KL(q, m, α) =−(pVDDq)2mπ

ω∫ π

w

0(VCon

(t)2 − VDDVCon

(t))dt

Since p and ϕ are all functions of q, m and α, KL is a function of only q, mand α.KC: follows directly from the definition of q and KL: KC(q, m, α) = 1/(q2KL(q, m, α))KP: can easily be found as a function of q, m and α by using IR =

√

2POUT /Rand the definition of p:

KP (q, m, α) = p(q, m, α)2/(2KL(q, m, α)2)

63

KX: can be derived using two fundamental quadrature Fourier componentsof VC(t).

VR =

∫ πω

0

VCon(t)

πsin(ωt + ϕ) dt +

∫ 2πω

πω

VCoff(t)

πsin(ωt + ϕ) dt

VX =

∫ πω

0

VCon(t)

πcos(ωt + ϕ) dt +

∫ 2πω

πω

VCoff(t)

πcos(ωt + ϕ) dt

KX(q, m, α) = VX/VR

5.4.5 Efficiency and Output Power of Class-EV V

Taking the three loss mechanisms (Pin, Pswitch, Pmatch) shown in Fig. 5.5and the existence of certain switch (transistor) breakdown-voltage15 (VBD =z(q, m, α) ·VDD) into account the efficiency and the power on the antenna canbe expressed:Drain Efficiency(η): derived as a function of q, m and α.

η(q, m, α) = 1 − Pswitch

VDDI0= 1 −

∫ πw

0VCon

(t)2dt

VDD

∫ πω

0VCon

(t)dt

Power-Added Efficiency(PAE): as a function of q, m and α.

PAE(q, m, α) =Pantenna − Pin

VDDI0

= η(q, m, α)

1

1 +√

n−1+QL

Qm

− c1c2

2d2Qd

KC(q, m, α)

KP (q, m, α)

where, Pantenna = POUT − Pmatch, n = RL

R , Pin ≈ ωCinV 2DDdriver

/(2Qd),c1 = Cin/Cout, c2 = Cout/C, d = VDD/VDDdriver

. Qm is the quality factor ofthe inductors Lm and L0. Qd is the quality factor of Ld (Fig. 5.5b).Power on Antenna(Pantenna): as a function of q, m and α.

Pantenna(q, m, α) =KP (q, m, α)

z(q, m, α)2n

1 +√

n−1+QL

Qm

V 2BD

RL

The values of c1, d and VBD depend on the characteristics of the transistortechnology. For a certain operation frequency and transistor technology, monly depends on the value of c2 since m = ωβ/c2 where β = RonCout which

15Here VBD refers to gate-drain oxide breakdown voltage which is assumed to be lowerthan junction breakdown voltages. It is also assumed that VDDdriver

is chosen as max.reliable gate-source oxide breakdown voltage.

64

q=1.8

q=1.2

q=0

q=0.6

q=1.2

q=0.6

q=0

q=1.8

a a

Pa

nte

nn

a

PA

E

Conventional Class-E Conventional Class-E

Fig. 5.6: PAE and Pantenna using technology and design parameters in [80]

depends on the transistor technology. Therefore, for a given transistor tech-nology, impedance transformation ratio (n), Qm and Qd, PAE and Pantenna

both are a function of only q, m and α. In Fig. 5.6, PAE and Pantenna

are plotted as a function of α for a few values of q using the design andtechnology parameters in [80]. In [80]16, QL = 3, Qd = 3, n = 3, c2 = 1,ω = 2π ·1.7 ·109 rad/sec and the transistor technology is 0.13µm CMOS (thickoxide) for which VBD ≈ 2.5·3.56 V17, c1 ≈ 4 and RonCout ≈ 10−12; resulting inm ≈ 0.011. In [80], an optimization procedure based upon approximations andsimulation results is given for Class-E PAs. The PAE measurement resultsgiven in [80] (67%, for conventional Class-E PA) is close to theoretical valuegiven in Fig. 5.6 (≈ 71%). The difference can be attributed to the losses dueto ground bonding and dc-feed inductance; which are not taken into accountin the analytical design equations in this section.

Fig. 5.6 shows the strong dependence of PAE and Pantenna both on q andα. It can be seen in Fig. 5.6 that the maximum Pantenna for Class-EV V (q =0.6, α = 2) is 1.65 times higher than the maximum Pantenna for conventionalClass-E PA (q = 1.2, α = 0). Besides, for q = 0.6 Class-EV V (α = 1) can haveabout 80% more Pantenna with only 3% less PAE than conventional Class-EPA (α = 0). For the same q = 0.6, Class-EV V (α = 2) can have about 200%more Pantenna with about 16% less PAE than the conventional Class-E PA(α = 0).

16Value of q is calculated as 1.2 from the circuit element values in [80] and Qm for Lm

and L0 (bondwire) is assumed to be 30.17In [80], breakdown voltage is doubled by using a cascode topology.

65

5.4.6 Proof of Concept Design

We verified the given design equations in this section by simulating the modelin Fig. 5.5b in spectre (Cadence).

(a)

(b) (c)

SimulationQ =5L

SimulationQ =10L

SimulationQ =20L

AnalyticalModel

SimulationQ =5L

SimulationQ =10L

SimulationQ =20L

AnalyticalModel

V(t

)/V

CD

D

time

time time

SimulationQ =5L

SimulationQ =10L

SimulationQ =20L

AnalyticalModel

V(t

)/V

CD

D

V(t

)/V

CD

D

0 0.5p/w p/w 1.5p/w 2p

0 0.5p/w p/w 1.5p/w 2p 0 0.5p/w p/w 1.5p/w 2p

Fig. 5.7: Simulated (cadence, pss) normalized drain voltage waveform vs.analytical model of Class-EV V for (a) α = 0, (b) α = 1, (c) α = 2 forQL = 5, 10, 20. The chosen duty-cycle= 50%, R = 1Ω, q = 0.01, VDD = 1Vand m = 0.01

a

Dra

in E

f f,h

AnalyticalModel

Simulation

Simulation

Simulation

(a)

AnalyticalModel

Simulation

Simulation

Simulation

Norm

aliz

ed

P ou

t,K

P

QL=5

QL=10

QL=20

QL=5

QL=10

QL=20

a(b)

Fig. 5.8: Simulated (cadence, pss) (a) Efficiency and (b) Normalized OutputPower (KP ) vs. analytical model for QL = 5, 10, 20. The chosen duty-cycle=50%, R = 1Ω, q = 0.01, VDD = 1V and m = 0.01

Fig. 5.7 shows the normalized switch voltage (VC(t)/VDD) of the analyt-ical model and the simulation results (periodic steady state) for α = 0, 1, 2.The simulations were done for three different values of QL = 5, 10, 20. Verygood agreement in the waveforms is observed between the simulations and thetheory. The difference between the simulations and the analytical model for

66

a = 2, Fig. 5.7c is negligibly small for all the values of QL. The four curvesare on top of each other. The slight discrepancy observed for α = 0 andα = 1 towards lower values of QL is attributed to the sinusoidal load currentassumption in the analysis.

Fig. 5.8 shows that both the drain efficiency (η) and the normalized outputpower (KP ) as a function of α closely agree with the analytical model.

Table-5.4: Measurement Results and Design Details

Details Class-E Class-EV Vα=1Class-EV Vα=2

(q,α,m,QL,n) (0,0,0.001,5,2.3) (0,1,0.001,5,2.3) (0,2,0.001,5,2.3)

Freq., VDD 5MHz, 1.4V 5MHz, 1.6V 5MHz, 1.9V

POUT , PDC 19.9, 29.4mW 30.4, 48.4mW 55.2, 108.3mW

R, η 22Ω, 67.7% 22Ω, 62.8% 22Ω, 51.0%

Lm, L, Vpeak 1.6, 12uH, 4.2V 1.4, 12uH, 4.2V 1.3, 12uH, 4.2V

C, Cm 0.26, 0.72nF 0.42, 0.72nF 0.79, 0.72nF

a=1 a=2

vC(t)

vRL(t)

vC(t) vC(t)

vRL(t) vRL

(t)

a=0

1

2

1

2

2

1

Fig. 5.9: Measurement Results for α = 0, 1 and 2

Three PAs in Table-5.4 are implemented on pcb by using a discrete tran-sistor (Maxim START499) with maximum allowed peak voltage (VC ≈ 4.5V), ceramic capacitors and air-core inductors. Measurement results at lowfrequency (5MHz) are given in Table-5.4 and Fig. 5.9; which verify that Class-EV V can have higher output power with reasonable efficiency in comparison to

67

conventional Class-E. In the measurements, an Agilent 54642A Oscilloscope,34401A DMV and an E3631A DC power supply are used. The switch (transis-tor) of the Class-E PA is directly driven with a square signal from an Agilent33250A signal source. Due to lack of the RF source at low frequency Pdrive

couldn’t be measured but is calculated to be about 3 mW.

68

5.4.7 Conclusion

This section shows the analytical design equations, and the time domain an-alytical solution for Class-EV V PAs, including finite dc-feed inductance andswitch input/output capacitance and on-resistance. In comparison to con-ventional Class-E PAs, Class-EV V PAs can have lower peak switch voltage;which can be utilized either to increase the reliable life-time or to obtain highoutput power using low-voltage transistor technologies (e.g. CMOS) withoutcompromising reliability.

This section shows (theoretically and experimentally) that Class-EV V PAscan have up to ≈ 200% more output power than conventional Class-E PAsunder the same drive, load and reliable peak voltage conditions, with only amodest PAE penalty.

69

5.5 Reliability Simulations for Variable Voltage Class-E(Class-EV V )

In this section, the reliability simulation methodology in chapter 2 [25] is usedto demonstrate that the tuning strategy in Class-E PAs significantly influencesthe life-time. The reliability simulation methodology is shortly introduced inchapter 2. The methodology is based on the model,Fig. 2.4, taking intoaccount both gate-oxide breakdown and hot-carrier degradation. Further de-tails of the simulation methodology and the model in Fig. 2.4 can be foundin [18], [25].

Fig. 5.10: Schematic of the PA circuit design, used for evaluating the simulator

A cascode Class-E PA topology seen in Fig. 5.10 is simulated by usingthe reliability simulation methodology. Three PAs operating in three differentmodes of Class-EV V namely α = 0, 1 and 2 are designed. All three PAs havetheir own values for LD, CD, L0, C0, LX as well as VDD. The dimensions forthe two MOSFETs are identical for all three circuits, Vbias was set to 1.2Vand RL was set to 25Ω. The PAs were designed in a 90 nm CMOS process,operating at 900MHz.

The designs of the three PAs are chosen such, that they have identicalinitial performance in terms of output power Pout, but considerably differentvoltage signals within the circuit. In this way the PAs can be tuned for reli-ability specifications. The circuits were designed to deliver a power of 25mWto RL, while the input voltage originates from a driver circuit that switchesbetween 0 and 1.2V. The output voltage is sinusoidal. The difference in thethree operation modes can be recognized in Fig. 5.11. In this figure, the volt-age signal at node VD1 is shown for all three different operation modes, aswell as the drain current flowing through transistor T1. This figure clearlyreveals the difference between the three different designs: in the α = 0 modetransistor T1 suffers from a high VGD, but the drain current is relatively low.As a consequence it can be expected that degradation in terms of gate-oxidebreakdown is severe, but hot-carrier degradation is negligible. In the α = 1mode, the peak-level of VD1 is reduced, but the drain current level is increased,

70

for the α = 2 mode this trend is further pursued. In terms of oxide breakdownthe gatedrain voltage of transistor T1 is the dominating stress voltage for alldesigns. The drain current in MOSFET T2 follows the same trend as the draincurrent in T1 for all three designs.

Fig. 5.11: Simulated drain voltage and drain current signals for the upperNMOSFET in the circuit of Fig. 5.10, in three different operation modes. Theα = 0 mode coincides with Class-E operation

Fig. 5.12: Output power plotted against stress time for the three different op-eration modes of the Class-EV V PA used in this paper. The dashed horizontalline shows the 22.5mW criterion used for defining circuit failure in this chapter

We used our new simulator for the evaluation of all three designs. InFig. 5.12, Pout is plotted against stress time. For all designs three differentsimulation results are shown. In the α = 0 and α = 1 mode this results inthree distinct lines. Breakdown events can clearly be recognized as suddendrops in Pout. The degradation in Pout occurs continuously for the α = 2

71

Fig. 5.13: PAE plotted against stress time for the three different operationmodes of the Class-EV V PA used in this chapter

mode; this indicates that for this design hot-carrier degradation dominatesover gate-oxide breakdown. In the α = 1 mode we recognize both discretedrops in Pout, as well as the effect of hot-carrier degradation, in between thebreakdown events. As our simulator makes use of a Monte-Carlo approachfor determining values for the time at which breakdown events occur, theresult of a single simulation will not prove to be very useful for the evaluationof a circuit. Performing many simulations in a Monte-Carlo run providesinformation on the probability of circuit failure. We evaluated all three circuitdesigns using 100 different simulations; the result is shown in Fig. 5.14. In thisfigure, FBD is the probability of circuit failure, obtained from our simulationresults. We defined circuit failure as the moment when Pout has decreased by10%, i.e. when Pout drops below 22.5mW. Fig. 5.14 clearly reveals the largedifference in circuit failure for the three different designs. The α = 1 modeproves to be the most robust circuit.

72

Fig. 5.14: Failure probability plots of the Class-EV V PAs used in this chapter.Clearly the α = 1 mode and α = 2 mode have superior performance in circuitlifetime over the α = 0 mode

From the results shown in Fig. 5.14 we can find that for the α = 1 mode63% of all circuits has encountered failure after 4.3X107 years. If circuit failurewould be supposed to coincide with the first breakdown event, this value wouldbe only 2.4X105 years. This is an increase in circuit lifetime of a factor over100. This is a huge increase and it demonstrates the large benefit of the newsimulator and Class-EV V .

73

5.5.1 Conclusion

In this section, a first-order RF reliability simulation methodology where theoxide breakdown and hot-carriers are both taken into account is used to showthat Class-EV V mode of operation can increase the overall life-time of thepower amplifier.

74

Chapter 6

Extended Drain NMOS(ED-NMOS) PowerAmplifiers

6.1 Abstract

This chapter reports RF power devices achieving 70% power-added efficiency(PAE) with 1, 2 and 3.4W output power at 2GHz. The power devices operateas sub-optimum Class-E power amplifiers, see chapter 5, having the advan-tage of 1.6 times higher output power with a slightly lower PAE than con-ventional Class-E. The power devices use high voltage extended-drain NMOS(ED-NMOS) transistors in standard 65nm CMOS. A scalable layout designthat we used preserves the high PAE for the various output power levels1.

6.2 Introduction

The strong trend towards integration in hand-held communication devices forcost and size advantages started an intensive research effort on the implemen-tation of high power and high efficiency RF power amplifiers (PA) in modernCMOS technologies [68]- [71]. In RF PA design, using high supply voltageis desirable to achieve both high efficiency and high output power. However,CMOS technology is optimized for low voltage operation2. The reported RFpower amplifiers in CMOS technology achieve good power efficiency for powerlevels up to 1W [68], [69] but still lack sufficient efficiency at higher powerlevels [2].

In this chapter, we present CMOS RF power devices having 70% power-

1This chapter was published in IEEE Radio Frequency Integrated Circuits (RFIC) Sym-posium, [9].

2e.g. Reliable supply voltage is 1V for standard thin-oxide and 2.5V for standard thick-oxide transistors in 65nm CMOS technology.

75

added efficiency (PAE) with 1, 2 and 3.4W output power at 2GHz [9]. Tothe authors’ knowledge, the efficiency and the output power levels presentedin this study are beyond what has been published on state of the art CMOSpower devices at 2GHz [68]- [2].

The large-signal operation mode of our power devices is sub-optimum Class-E [6]. An advantage of the sub-optimum Class-E is its lower peak drain voltagecompared to conventional Class-E operation. The lower peak drain voltageallows biasing the device at a higher supply voltage, resulting in a higheroutput power with a slight decrease in PAE.

G GS D

STI STI STI STI

S Dn-extensionN+ N+P+N+ N+

Pwell

P-subP-sub

Lg=0.28 mm Lg=0.28 mm

Fig. 6.1: Cross section drawing of (a) Standard Thick Oxide NMOS transistor(b) Extended-Drain Thick Oxide NMOS (ED-NMOS) transistor.The oxidethickness (tox) = 50A

D

S

G

VDD

L

C0 L0 X

CIN

D

S

G

Ron

BVGD

VDD

L

(a)

Tuned

at w0

C0 L0

Tuned

at w0

C

R R

PIN Ps witc h

POUTVC

(b)

X

COUT

PDC

2p/wp/wtime

1

0

2

3

4

.

.

ConventionalClass-E

Sub-optimumClass-E

2p/wp/wtime

0

VIN(t) VC(t)/VDD

0

Zero voltageswitching

Non-zerovoltage

switching

VIN

VIN_PP

Fig. 6.2: (a) Sub-optimum Class-E PA (b) Model of sub-optimum Class-E PA

76

In the design of the power devices, we use extended drain NMOS (ED-NMOS) transistors [71], which have higher breakdown voltage than the stan-dard transistors. Fig. 6.1 shows the construction of the ED-NMOS transistorsfor which we utilized only the standard process steps and the masks availablein 65nm CMOS technology. Moreover, our scalable design approach in thelayout design of the power devices preserves the high efficiency (70% PAE) forthe various output power levels (1, 2 and 3.4W). The scalable design approachoptimizes the power device layout geometry for minimum power loss.

6.3 NMOS and ED-NMOS Sub-Optimum Class-E

Fig. 6.2a shows the Class-E power amplifier that is widely used in high fre-quency applications due to its simple circuit topology and high efficiency. Inchapter 5, it was shown that by satisfying certain relations between the cir-cuit element values the Class-E circuit topology can operate as sub-optimumClass-E with the advantage of lower peak voltage. The lower peak voltageallows using higher supply voltage. For example, a sub-optimum Class-EPA designed to operate at 2GHz with ED-NMOS transistor will have about1.25 times higher supply voltage (VDD), about 1.6 times higher output power(POUT ), and about 6 percentage points lower PAE than a conventional Class-EPA designed with ED-NMOS transistor under the same input power, outputimpedance and breakdown voltage (BVGD)3.

The following closed form analytical equations for a sub-optimum Class-EPA were derived in chapter 54:

PAE(m) =η(m)

1 + 12π · η(m) · KC(m)

KP (m) · c · d2(6.1)

POUT (m) = KP (m) · V 2DD

R(6.2)

where m = ω · RON · COUT , d = VIN PP /VDD and c = CIN/COUT5.

KC(m) and KP (m) are non-linear expressions showing the required relationbetween the circuit elements (e.g. R, C) and the operating conditions (e.g. ω,POUT ).

3In chapter 5, only the theory of the sub-optimum Class-E is presented without highfrequency measurements. In this chapter, we present the first high frequency measurementsof the theory. The decrease in the PAE depends on the operation frequency, the transistortechnology and the chosen sub-optimum Class-E mode [6]. Here, the breakdown voltagerefers to gate-drain oxide breakdown voltage.

4The analysis in chapter 5 can be generalized to cover both Class-EV V and Class-EV S .The definitions in [69], η = POUT /PDC = 1 − Pswitch/PDC , PAE = POUT /(PDC + PIN ),are used.

5In order to minimize the switch-on resistance (RON ), we can use the maximum possibletransistor size for which transistor output capacitance COUT = C.

77

The product RON ·COUT is a characteristic property of the transistor tech-nology6 used as a switch in the sub-optimum Class-E PA design. Therefore, thedrain-efficiency (η) is a function of only frequency (ω) for a certain technology.

Fig. 6.3a compares the η of the standard thick-oxide NMOS against the ηof the ED-NMOS when both of them are operating as sub-optimum Class-EPA. The extension on the drain increases the transistor switch-on resistance(RON ), which decreases the η of the ED-NMOS with respect to the standardthick oxide NMOS. The η of both the ED-NMOS and the NMOS decreases asthe frequency increases.

Fig. 6.3b shows that the ED-NMOS can have ≈4 times higher outputpower than the NMOS due to its 2 times higher supply voltage. The higheroutput power advantage under the same input drive power and load impedanceconditions gives a very important advantage to ED-NMOS over NMOS interms of PAE. Despite having lower η the ED-NMOS has higher PAE thanthe NMOS up to 7GHz, as Fig. 6.3 shows. Therefore, the model in Fig. 6.2bproves that ED-NMOS can have more output power by allowing higher supplyvoltage than NMOS without sacrificing its PAE up to 7GHz.

DE( )NMOS h

DE

( )

ED-NMOS h

PAEED-NMOSPAENMOS

Po

ut E

D-N

MO

S/P

ou

t NM

OS

frequency(GHz) frequency(GHz)

dra

in e

ffic

ien

cy (

%)

po

wer-

ad

ded

eff

icie

ncy (

%)

(a) (b)

Fig. 6.3: According to the sub-optimum Class-E model, (a) drain efficiency(η) (b) PAE and output power ratio of standard thick oxide NMOS and ED-NMOS. Break-down voltage (BVGD) of ED-NMOS is assumed to be 2 timeshigher than NMOS and m for ED-NMOS is 0.0147 and for NMOS 0.0074 at2GHz. The m values from the compact model was calculated data that agreeswith the measurement results by ≈80−90%

6RON · COUT ∼ RON · Wg ≃ Lg

µnCOX (VGS−VT H). All the terms, the channel length

(L), the charge-carrier effective mobility (µn), oxide capacitance density (COX) and gate-source and threshold voltage difference (VGS − VTH) depend on the technology except forthe transistor gate width (Wg).

78

6.4 Scalable Layout Design of RF Power Devices

Fig. 6.4 schematically shows the generic scalable layout of the RF powerdevice. The device is a parallel connection of N(= Wg/E) unit cell transistorswhere E is the finger width and Wg is the total device gate width. The powerdevice dimensions (X, Y) have a direct impact on the PAE. Depending on thepower level and the operation frequency the scalable layout design approachallows us to iterate towards the optimum device dimensions (X, Y) having themaximum PAE by minimizing the input power and the resistive power lossesin both drain and source. The iterative optimization approach determines thefinal device dimensions using extensive parasitic extraction simulations.

...

...

...

...

...

...

...

...

...

...

......

...

...

...

Source

Source

Drain

Drain

Drain

Drain

Dra

in

Gate

Gate

Gate

X

Y

0

1

2

3

N-2

N-1

N

N-3

RFIN RFOUT

So

urc

e

Fig. 6.4: A generic layout drawing showing the scalable layout optimizationapproach of the ED-NMOS RF power devices. Each unit transistor has 5µmfinger length (E). Some connections are not drawn for the sake of simplicityof the layout picture

In the layout of the power devices in CMOS, the parasitic capacitancesdue to metal connections can be as large as the device intrinsic capacitances.Minimizing the parasitic capacitances is vital to achieve high power efficiencyat high frequency. Fig. 6.5b shows that we use an asymmetric multi-fingereddevice layout [75] instead of the classical symmetric multi-fingered layout inFig. 6.5a. The asymmetric layout allows larger metal track distances (dY >dX

→ CY <CX), which decreases the parasitic metal capacitances by ≈ 20%.

79

polyM1

M2

M7

ALU

Via1

Via7

D S D S D S S D

Cx

(a) (b)

Cy

dx d y

Fig. 6.5: (a) Classical symmetric multi-fingered layout (b) asymmetric multi-fingered device layout

6.5 Measurement Results

6.4

6V

2p/w00

D

S

G

VDD

Bias-Tee

PowerDevice

bond-pad

Measured Waveform

Z @L1 0w

Z @ 2L2 0w

2 .4 V

VBBias-Tee

Z @S1 0w

PAV

PIN

Non-zerovoltage

switching

VC(t)

Active Harmonic

Load-Pull System

On-Chip

time

Fig. 6.6: General description of the measurement set-up using an active har-monic load-pull system and the measured drain waveform of the NMOS powerdevice to show the sub-optimum Class-E operation. VDD= 2.9V

Three power devices: ED-NMOSI, ED-NMOSII and ED-NMOSIII withthe total gate widths of Wg, 2Wg and 4Wg respectively, where Wg=2.56mmwere designed. For comparison purposes, a standard thick-oxide NMOS powerdevice with the same gate width as ED-NMOSII to demonstrate the benefits ofED-NMOS over standard thick oxide NMOS device was also designed . Fig. 6.6shows the circuit diagram of the measurement set-up. On-wafer measurementswere performed in an active harmonic load-pull system [74]. With the secondharmonic load tuning, the power devices can operate as sub-optimum Class-EPA. The wafer is thinned to 120µm for good heat transfer.

The measurement results in Fig. 6.7 show that the PAE of all the power de-

80

ED-NMOSI

ED-NMOSIIED-NMOSIII

NMOS

NMOS

ED

-NM

OSI

ED

-NM

OSIII

ED-NMOSII

Fig. 6.7: Measured power added efficiency (PAE) and Transducer Gain(=POUT /PAV ) of ED-NMOSI, ED-NMOSII, ED-NMOSIII and StandardThick-Oxide with respect to output power at 2GHz operation frequency. ED-NMOS’ have 6V supply voltage while Standard Thick-Oxide has 3V

vices reaches at least 70%. The output power of the ED-NMOS devices increasein proportion to the device size without any degradation in PAE and powergain, showing that efficiency losses for larger devices can be overcome by thescalable layout design. Note that the output power of ED-NMOSIII is limitedby the maximum allowed current in our measurement system. The transducergain of the ED-NMOS devices (≈20dB) is higher than the transducer gain ofthe standard thick-oxide NMOS (≈17dB). Less than 3% deviation in the out-put power, the PAE and the transducer gain was observed after measuring 20different samples. The minimum required load resistance for the largest powerdevice (ED-NMOSIII) is 4.4Ω, which allows efficient matching networks to berealized on-chip or on PCB.

The PAE and the output power of ED-NMOSI was measured at 2, 3 and4GHz in order to demonstrate the higher frequency performance of ED-NMOSpower devices, Fig.6.8. The PAE is 60% and 55% at 3 and 4GHz respectively7.In [70], a CMOS PA at 5.2GHz with 27% PAE and 25dBm output power isreported. In comparison to [70], ED-NMOSI achieves higher efficiency.

7Note that at 3 and 4GHz only the first harmonic load impedance was tuned due to thelimitations of the measurement system

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freq (GHz)

ma

xim

um

PA

E(%

)

Po

ut

(dB

m)

Fig. 6.8: Measured maximum PAE and the corresponding output power ofED-NMOSI at 2, 3 and 4 GHz with 5.5V supply voltage

Fig. 6.9 shows the preliminary reliability performance of the ED-NMOScompared to the thick-oxide NMOS power device. When operated from a 3Vsupply the thick-oxide NMOS shows a reliability problem by degrading itsPAE by 15 percentage points over 6 hours of continuous operation. The ED-NMOSI was operated from a 5.5V supply for the first 4 hours and 6V for thelast 2 hours and observed no degradation in its PAE and output power. Thereliability test time is limited by the on-wafer measurement system.

Fig. 6.10 shows the die photo. A significant portion of the power device iscomposed of the bond-pads and the metal connections. The total area of ED-NMOSII is 0.175mm2 whereas its active area is 0.031mm2. The power densityof ED-NMOSII (0.4W/mm) is ≈6 times higher than the power density of thestandard thick-oxide NMOS (0.06W/mm), giving an important cost advantageto the ED-NMOS.

82

time (hour)

po

we

r-a

dd

ed

eff

icie

ncy

(%

) ED-NMOSI

ED-NMOSI

NMOS

NMOS Po

ut

(dB

m)

V =3VDD

V =5.5VDD

V =6VDD

Fig. 6.9: Measured PAE and output power under sub-optimum Class-E op-eration of Standard Thick-Oxide NMOS with 3V supply voltage for 6 hoursoperation and ED-NMOSI for 5.5V for 4 hours and 6V for 2 hours. The thick-oxide NMOS shows a reliability problem by gradually losing its PAE, whereasED-NMOSI shows no sign of reliability problem. The increase in VDD after 4hours increases the output power of ED-NMOSI

ED-NMOSIED-NMOSII

Standard

Thick-Oxide

NMOS

ED-NMOSIII

0.5mm

0.4

mm

0.5mm

0.3

5m

m

Fig. 6.10: Die photos of the ED-NMOSI, ED-NMOSII, ED-NMOSIII, andStandard Thick-Oxide NMOS power devices. The shaded regions in the chipphoto have designs that are not related with this work

83

ED-NMOSI

ED-NMOSII

ED-NMOSIII

Table-I: Comparative Table of The State of The Art PAs

[74]

[75]

[76]

Freq.(GHz)

PAE

(%)max

P

(Watt)OUT Technology

(CMOS)

V

(V)DD

2

1.7

1.9

2

2

2

60

58

45

70

70

70

1

1.3

2

1

2

3.4

65nm

0.13 mm

0.13 mm

65nm

65nm

65nm

5

2.5

5.5

6

6

6Th

isW

or k

61*

63*

66* 64**

61**

59**

(*) off-chip output matching network with inductor quality factor =30(**) on-chip output matching network with inductor quality factor = 20

Table-I shows a comparison among the reported state of the art RF PAand this work. To make a fair comparison, the PAE results with * and **indicate the calculated PAE values by assuming a single stage low-pass L-Coutput matching network with realistic inductor quality factor. In terms ofthe frequency and the output power [68], [69] and ED-NMOSI are similar toeach other. However, ED-NMOSI has better PAE than [68] and [69]. Notethat the reported 60% PAE in [68] excludes output matching network losses.In comparison to ED-NMOSII, [3] has significantly lower PAE. This low PAEcould be due to the high number of stacked transistors in [2].

The demonstrated output power and PAE is sufficient to use the ED-NMOSin PAs for cellular applications (e.g. GSM/GPRS) or as drivers for high powerRF transistors (e.g. GaAs); enabling advanced transmitter architectures sim-ilar to [72]. For lower power applications like Bluetooth, wireless-LAN, itwill be possible to connect the ED-NMOS directly to the antenna withoutneeding a matching network, improving the overall efficiency. Moreover, theED-NMOS can replace dedicated expensive technologies in future base-stationapplications such as tower-top antenna arrays where the power levels for eachunit PA cell are in the 1 − 5W range [73].

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6.6 Conclusions

In this chapter, RF power devices were reported having more than 70% PAEfor 1, 2 and 3.4W output power at 2GHz in standard 65nm CMOS technology.The power devices operate as sub-optimum Class-E power amplifiers, takingthe advantage of higher output power with a slight PAE penalty in comparisonto the conventional Class-E under the same input drive, load impedance andreliability conditions. The power devices were designed with the high-voltageextended-drain NMOS transistors that only use the existing process steps andmasks in standard 65nm CMOS technology without adding extra cost. Theoutput power of the power devices scales with the device sizes without anydegradation in the PAE, demonstrating that power efficiency can be preservedfor high power devices in CMOS technology.

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Chapter 7

Segmented Power Devices

7.1 Abstract

Lifetime of power systems can be increased significantly by segmenting thepower transistors in many lower-power segments in parallel, all with their ownbreakdown detection circuitry, and switching off the sections with the mostbreakdowns. The concept is demonstrated on an RF PA in standard 90nmCMOS using only thin oxide transistors.

7.2 Introduction

In modern CMOS technologies, reliability issues limit the maximum operatingvoltage of transistors. This voltage limitation prevents the integration of effi-cient power amplifiers (e.g., audio or RF) since stacked devices are needed toovercome breakdown, which reduces efficiency. Transistor reliability is stronglyrelated to operating voltage, higher voltages result in faster degradation andhence in lower reliability and shorter life time. Degradation can be monitoredby oxide degradation, threshold voltage-shifts and mobility reduction1.

An approach is introduced to extend the lifetime of high-voltage analog cir-cuits in CMOS technologies based on redundancy, like that known for DRAMS.A large power transistor is segmented into N smaller ones in parallel. If a sub-transistor is broken, it is removed automatically from the compound transistor.The principle is demonstrated in an RF CMOS Power Amplifier (PA) in stan-dard 1.2V 90nm CMOS.

1This chapter was published in IEEE International Solid-State Circuits Conference(ISSCC), [12].

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Fig. 7.1: (a) Conventional cascode PA, (b) Segmented PA to increase lifetime

7.3 Digital Detection of Oxide Breakdown

A single oxide breakdown event (OBD) shows up as a sudden increase in oxide-leakage, which can be modeled as the sudden formation of a resistance of afew kΩ from gate to drain, to source or to bulk [10]. Due to the large size ofpower transistors, the relative effect of a single OBD on the performance issmall, consequently defining reliable operation time as ”the time to the firstoxide breakdown of the gate dielectric in a transistor” [10] is overly strict [11].However, in order to have a reasonable overall lifetime, normally an extramargin against degradation is built into the design, i.e., non-degraded powertransistors have to be able to deliver more power than needed in the case ofzero OBD, so they still function properly after a few OBDs. In the segmentedpower device approach, this extra margin will be exploited in order to increaselife time.

A number of OBDs is acceptable for power circuits and stochastic proper-ties can even be used to increase lifetime. In our system each power transistor(width W) is segmented in N parallel transistors (width W/N), each with OBDmonitoring circuitry and predriver including enable/disable functionality, asshown in Fig. 7.1.

During operation, the number of OBDs in each power transistor (segment)is monitored by measuring the oxide-resistance, the number of OBDs is approx-imately proportional to the gate conductance. Upon detection of too manyOBDs in a power transistor in a segment, i.e., oxide conductance that is toohigh, that segment is shut down.

During operation some OBDs occur, mainly in the most heavily stressedparts of a circuit, here, in the (segmented) power transistors. In case of a weakspot in a transistor, the breakdowns occur mainly in that transistor, and only

88

that segment is shut down. If no weak spots are present, the distribution of theOBDs will be spatially uniform across all segments, while the total number ofOBDs increases with operation time. Statistics will be used in the next sectionto increase lifetime.

Fig. 7.2: Simulated probability mass function for 107 breakdown events, uni-formly distributed over 16 segments: the median and mean of the fullest seg-ment is much higher than those over all segments

7.4 Life Time Extension

If M breakdowns are spatially uniformly distributed across N segments, thedistribution of OBDs in one segment is binomial (Gaussian-like): some seg-ments have more breakdowns than others. For example, 107 uniform OBDsacross 16 sections, the average OBD count in a segment is 6.7. The seg-ment with the most breakdowns, however, has on average 11.6 OBDs. Elim-ination of that segment decreases the total number of OBDs in active seg-ments much more than proportionally. For the above example, Fig. 7.2 showsthe probability distribution both over all of the 16 segments, and in the seg-ment that ends up with the most OBDs. Mathematically, the difference be-tween the medians of OBDs in any segment and in the ”fullest” segment ismedian ≈ (

√2 · erf−1(1− 2/N)+ 0.4)σav, see appendix C, where σav is the

standard deviation of the number of OBDs averaged over N segments: moresegments (N) and more variance is beneficial.

89

Fig. 7.3: Simulated POUT and PAE as a function of the number of breakdowns(operation time) for 3 situations: continuously using 16/16 segments resultingin EOL=110 events, constant-area redundancy using 8/16 + 8/16 segmentsyielding EOL=190 events (+70% lifetime), switching off the worst segmentusing 16-15-14-13 segments for which EOL=400 events (+260% lifetime)

To demonstrate the effect of stochastic lifetime extension an RF PA wasdesigned in 90nm CMOS, with thin gate oxide, VDD = 1.2V, and each powertransistor segmented in 16 sections (N=16). Fig. 7.3 shows Spectre simulationresults of the output power (POUT ) and power added efficiency (PAE) of theClass-E PA as a function of the number of OBDs. The x-axis can be interpretedas a time axis if the OBDs are evenly distributed over time. End-of-life (EOL)is defined as either PAE < 30% or POUT < 80mW. The curves marked with”16 segments” correspond to always using all 16 segments, with EOL around110 OBDs. The curves marked ”8 + 8 segments” correspond to using halfthe segments and replacing all these at EOL detection with the remaining8 segments. This redundancy type of operation (with the same total area)has EOL after about 190 OBDs: a 70% increase in lifetime. For the curvesmarked with ”16−15−14−13 segments” the PA starts with all 16 segments andsequentially shuts down the worst segment, at EOL 3 segments are disabled.EOL is at about 400 OBDs: a 260% increase in lifetime.

90

Fig. 7.4: Circuit schematic of each of the 16 PA segments including breakdowndetection monitoring circuitry, digital control logic and decoders not shown.

Fig. 7.4 shows the circuit schematic of one PA segment, shown in grey arethe driver and the cascoded output stage (M1 and M2). The four operationmodes are: RF operation, disabled, and OBD-measurement for each of thetransistors M1 and M2. Control signals Cn are listed in Fig. 7.4 for the variousmodes. OBD-measurement is done by determining the gate oxide conductance(about proportional to the number of OBDs). The breakdown measurementsare done in three steps: gate-conductance in M1 is sensed in one step whileM2 is measured in two steps.

OBDs for M1 and M2 were quasi-continuously measured in one segment (bycontinuously cycling through the 4 modes) to verify the monitoring function.Figure 7.5 shows measured sense-voltage levels in the 3 breakdown measure-ment modes as a function of stress time under accelerated conditions. Thetimes at which an OBD occurs are marked with a flash on the x-axis. Theschematics in Fig. 7.5 show the effective circuit for the 4 operation modes,the measured OBD-paths during measure-modes are indicated with a resis-tor+flash. For the first 6 breakdown events in the segment a slightly degradedoutput voltage shape resulted, while after the 7th breakdown (at 20000s in Fig.7.5) the total PA fails to operate correctly. This is detected and the segmentis switched off.

The RF performance of 1 out of the 16 segments is shown in Fig. 7.6:the measured POUT , drain efficiency DE and PAE at 900MHz are shown as afunction of input power. Measurements were done on-wafer without harmonictuning (non Class-E operation), using an RF choke to bias the open drain froma 1.2V supply voltage. The reasonably good PAE of about 30% at 900MHzshows that the RF performance is not significantly degraded by the OBDdetection circuitry. The lack of harmonic tuning in our measurements prevents

91

Fig. 7.5: Measured breakdown-indicating sense-voltage as a function of stresstime, under accelerated conditions. For each of the 4 operation modes thecorresponding effective circuit configuration of the segment is shown

Fig. 7.6: Measured performance of 1 out of the 16 PA segments, at 900 MHzwithout harmonic tuning

92

waveshaping characteristics of high efficiency PAs (e.g., Class-E), resulting inthe difference between simulations (Class-E) and measurement results (non-Class-E). The die photo is shown in Fig. 7.7, including pads and control logicit occupies 3.0mm2.

Fig. 7.7: Micrograph of the demonstration vehicle in 90nm: the total PA issubdivided into 16 segments with their own OBD monitor circuitry. Digitalcontrol used for addressing each segments state. Total chip area is 3.0mm2

93

7.5 Conclusion

The lifetime of power systems can be increased significantly by segmenting apower system into many lower-power segments in parallel, all with their ownbreakdown detection circuitry, and switching off the segments with the mostoxide breakdowns. The implementation presented only has a minor effect onDE and PAE.

94

Chapter 8

Summary and Conclusions

In this chapter, the thesis is summarized, the main conclusions are listed andfinally the suggestions for future research are given.

8.1 Summary of the Thesis

In order to meet the demands from the market on cheaper, miniaturized mobilecommunications devices realization of RF power amplifiers in the mainstreamCMOS technology is essential. In general, CMOS Power Amplifiers (PAs)require high voltage to decrease the matching network losses and for highoutput power whereas the mainstream CMOS technology is optimized for lowvoltage operation. This calls for innovative solutions to enable the design ofreliable RF PAs in CMOS technology.

Chapter 1 summarized the three new approaches:

• Exploration of tuning methods of switching PAs for finding the optimumoperation of RF PAs under given reliability, output power and efficiencyconditions.

• Exploration of high voltage circuit techniques (e.g. cascode, extended-drain) to enable the RF CMOS PAs withstand high voltages.

• Exploration of degradation detection and elimination methods to in-crease the reliable life-time of RF CMOS PAs.

Chapter 2 discussed the degradation mechanisms that can significantlyaffect the performance of CMOS power amplifiers as well as an RF reliabilitysimulation methodology used to compare certain classes of RF PAs.

Chapter 3 presents the analytical design equations for the ideal single-ended Class-E Power Amplifier (PA) as a result of the exploration of tuningmethods. The obtained analysis results link all known Class-E PA designequations as well as presenting new design equations. Some of the new Class-

95

E PAs require higher load resistance (1.3 < q1 < 1.5.) for the same outputpower and reliability conditions which is advantages for low breakdown voltagetechnologies such as CMOS. By means of the analytical design equations thewaveform characteristics of Class-E PAs are investigated and it is found thatthe ”peak drain voltage” depends strongly on the duty-cycle information. Toenable easy Class-E design, a (non-iterative) design procedure is given thatenables optimization of the Class-E PA under e.g. boundary conditions oncircuit element values and operating conditions.

Chapter 4 advanced the solution in chapter 3 a step further by includingthe transistor on resistance and it is shown that-Class-E conditions (e.g zero voltage and zero slope) can be satisfied in thepresence of the switch-on resistance-Drain efficiency (η) for Class-E PAs is upper limited by the transistor tech-nology and the operation frequency-Using a finite dc-feed inductance instead of an RF-choke in Class-E PAs in-creases η. Depending on the transistor technology and the operation frequencythe increase in η can be as high as ≈ 30%.

In Chapter 5, important advantages of sub-optimum Class-E PAs for CMOStechnology are presented as a result of further study on the tuning meth-ods. Variable-slope operation of Class-E PAs can increase the tolerance to theswitch (transistor) output capacitance approximately 2.1 times which allowsusing larger switch (transistor) hence obtaining higher drain efficiency. More-over, certain modes of variable slope operation causing important reliabilityconcern by increasing the peak drain voltage2 can be prevented by properlyusing the analytical design equations.

In comparison to conventional Class-E PAs, variable-voltage Class-EV V

PAs can have lower peak switch voltage; which can be utilized either to in-crease the reliable life-time or to obtain high output power using low-voltagetransistor technologies (e.g. CMOS) without compromising reliability. A firstorder reliability simulation methodology shows that variable voltage operationmode can be a knob to significantly increase the life-time of the Class-E PAsfor a certain output power. Also it is shown that Class-EV V PAs can haveup to ≈ 200% more output power than conventional Class-E PAs under thesame drive, load and reliable peak voltage conditions, with only a modest PAEpenalty.

Chapter 6 presented the advantages of extended drain transistors in PAsin the context of exploration of high voltage circuit techniques. RF powerdevices achieved more than 70% PAE for 1, 2 and 3.4W output power at2GHz in standard 65nm CMOS technology. The power devices operate insub-optimum Class-E mode, taking the advantage of higher output power witha slight PAE penalty in comparison to the conventional Class-E under the

1The symbol q is defined as the tuning ratio between the drain inductance and outputcapacitance of the transistor

2such modes of variable slope operation, k > 0 may occur as a result of antenna mismatchor spread in the value of the components etc.

96

same input drive, load impedance and reliability conditions. A scalable layoutapproach in the design of power devices is introduced. The output power ofthe power devices scales with the device sizes without any degradation in thePAE, demonstrating that power efficiency can be preserved for high powerdevices in CMOS technology.

In chapter 7, an approach is introduced to extend the lifetime of high-voltage analog circuits in CMOS technologies based on redundancy, like thatknown for DRAMS in the context of exploration of degradation detection andelimination methods. A large power transistor is segmented into N smallerones in parallel. If a sub-transistor is broken, it is removed automatically fromthe compound transistor. It is shown experimentally that oxide breakdown canbe detected digitally. Moreover, it is shown theoretically that the degradationdetection and elimination can increase life-time of PAs in CMOS technology.

All these proposed approaches contribute to realization of reliable CMOSPAs in CMOS technology.

8.2 Conclusions

• The analytical design equations presented in this thesis show that fi-nite dc-feed inductance Class-E (1.3 < q < 1.5) has the advantage ofapproximately 2.4 times higher load resistance than RF-choke Class-E(0 < q < 0.5) under the same reliability and output power conditions.As a result, Class-E PAs with finite dc-feed decreases matching networklosses significantly thus increases the feasibility of implementation in inlow breakdown voltage technologies such as CMOS.

• The lower peak voltage of sub-optimum mode of operation of Class-E(Class-EV V ) PAs has important reliability advantages that can be tradedfor CMOS technology. The reliability advantages could be traded-off forextra life-time or higher output power. The derived analytical equationsindicate also the non-useful operation modes where the peak voltage ishigh. Such operation modes that can occur due to antenna mismatch,component spread etc. can be predicted by the derived design equations.

• CMOS switching PAs at watt level output power with high PAE (≥ 70%)are feasible with high voltage extended drain transistors and with sub-optimum Class-E operation.

• A new concept of ”degradation detection and elimination” through smartcircuit techniques in CMOS technology is demonstrated. By switching-off the broken segments in a transistor composed of many segments (elim-inating the weakest link in the chain) the life time of CMOS circuits canbe increased. The feasibility of detection of oxide breakdown is demon-strated and it has been theoretically shown that ”degradation detectionand elimination” can increase life time of CMOS PAs.

97

8.3 Original Contributions

• The analytical design equations for Class-E PAs with finite dc-feed in-ductance.

• The analytical design equations for Class-E PAs with finite dc-feed in-ductance and switch-on resistance, which showed that the theoreticalmaximum efficiency of Class-E is limited by the transistor technology(RonCout product) and operation frequency.

• The analytical design equations for variable slope Class-E (Class-EV S)which have the advantage of tolerating higher transistor output capaci-tance.

• The analytical design equations for variable voltage Class-E (Class-EV V )which have the advantage of lower peak switch voltage.

• Experimental proof of scalable power devices with 70% PAE and 1, 2 and3.4 Watt Output Power at 2GHz by using extended drain transistors instandard 65nm CMOS technology.

• The introduction of a new concept, degradation detection and elimina-tion which can be used to increase the life time of CMOS circuits.

8.4 Recommendations for Future Research

• The analysis presented in this thesis for Class-E PA can be further ad-vanced with the inclusion of a more realistic transistor model to includeboth linear and switching mode of operation. Such a model may revealimportant relations between linear and switching PAs.

• The significantly longer life-time of Class-EV V in comparison to conven-tional Class-E shown with the first-order reliability simulator demandfor further experimental work.

• The theoretical result of significant life-time extension approach of ”degra-dation detection and elimination” approach encourages for further exper-imental work. A large amount of samples are needed to run statisticalexperiments to demonstrate the benefit of ”degradation detection andelimination”.

• The ”degradation detection and elimination” concept can be very ad-vantageous for advanced phased array PAs where the system continuesto operate even though some of the PAs fail.

98

Samenvatting

Om aan de eisen van de markt voor goedkopere en geminiaturiseerde mobielecommunicatie apparatuur te kunnen voldoen, is het essentieel om RF poweramplifiers te integreren in de CMOS technologie. In het algemeen vragen deCMOS Power Amplifiers (PAs) hoge spanning om de ’matching’ netwerkver-liezen te verminderen en om een hoog uitgangsvermogen, terwijl de heersendeCMOS technologie geoptimaliseerd is voor een lage spanningswerking. Ditvraagt om innovatieve oplossingen die het mogelijk maken om betrouwbareRF PAs te ontwerpen in CMOS technologie.

Hoofdstuk 1 is een samenvatting van de volgende drie nieuwe benaderingen:

• Exploratie van de instelmethodes van het schakelen van PAs voor hetvinden van de optimale werking van de RF PAs onder bepaalde be-trouwbaarheid, uitgangsvermogen en de efficintie condities.

• De exploratie van de hoogspanning circuittechnieken (b.v. cascode,extended-drain) om de RF CMOS PAs in staat te stellen om weerstandte bieden tegen hoge spanning.

• Exploratie van de degradatie opsporing en verwijderingmethodes om debetrouwbare levensloop van de RF CMOS PAs te verhogen.

Hoofdstuk 2 bespreekt de degradatie mechanismen die de prestaties vanCMOS power amplifiers beduidend kan benvloeden evenals een RF betrouw-baarheidssimulatie methodologie, die wordt gebruikt om bepaalde klassen vande PAs te vergelijken.

Hoofdstuk 3 presenteert de analytische ontwerpvergelijkingen voor de ide-ale single-ended Class-E Power Amplifiers (PA), als resultaat van de exploratievan instelmethodes. De verkregen analyse resultaten verbinden alle bekendeClass-E PA ontwerpvergelijkingen met elkaar evenals de voorgestelde nieuweontwerpvergelijkingen. Enkele nieuwe Class-E PAs vereisen hogere ’load’ weer-stand (1.3 < q3 < 1.5.) voor hetzelfde uitgangsvermogen en betrouwbaarheidscondities welke voordelen zijn voor de lage ’breakdown voltage’ technologieenzoals CMOS. Door middel van de analytische ontwerpvergelijkingen zijn de

3Het symbool q is gedefinieerd als de instelverhouding tussen de drain inductie en deuitgangscapaciteit van de transistor

99

golfvormkenmerken van Class-E PAs onderzocht. Hieruit kwam naar vorendat de ”peak drain voltage” sterk afhangt van de ’duty-cycle’ informatie. Vooreen gemakkelijk Class-E ontwerp, wordt een (non-iterative) ontwerpproceduregegeven, die de optimalisering van de Class-E PA in staat stelt onder b.v.grensvoorwaarden op de circuit elementwaarden en werkingscondities.

Hoofdstuk 4 gaat verder in op de oplossing die in hoofdstuk 3 is bespro-ken, door de transistor ’on resistance’ toe te voegen en er wordt getoond dat -Class-E condities (b.v. nul spanning en nul helling) kunnen bevredigend zijnin aanwezigheid van de ’switch-on’ weerstand - De drain efficientie (η) voor deClass-E PAs is bovengrenst door de transistor technologie en de werkingsfre-quentie. - Het gebruiken van eindige dc-feed inductantie in plaats van een RFchoke in Class-E PAs verhoogt η. Afhankelijk van de transistor technologie ende werkingsfrequentie, de verhoging in η kan zo hoog als ≈ 30% zijn.

In hoofdstuk 5 worden de belangrijke voordelen van sub-optimale Class-E PAs voor CMOS technologie voorgesteld, als resultaat van verdere studieover de instel methodes. De variabele hellingswerking van Class-E PAs kan detolerantie tot de schakelaar (transistor) uitgangscapaciteit ongeveer 2.1 keerverhogen. Dit laat dan toe een grotere schakelaar (transistor) te gebruiken. Hi-erdoor wordt hogere drain efficientie verkregen. Voorts, bepaalde modes van devariabele hellingswerking veroorzaakt belangrijke betrouwbaarheidszorg doorde drain spanning te verhogen4 kan worden verhinderd door de analytischeontwerpvergelijkingen juist te gebruiken.

In vergelijking tot conventionele Class-E PAs, variabele-spanning Class-EV V PAs kunnen een lagere piekschakelaar spanning hebben; welke kan wordengebruikt of om de betrouwbare levensduur te verhogen of om hoog uitgangsver-mogen te verkrijgen, door gebruik te maken van lage - spanning transistortech-nologieen (b.v. CMOS) zonder de betrouwbaarheid te compromitteren. Eeneerste orde betrouwbaarheidssimulatie methodologie toont aan dat de vari-abele spanningwerking modus een knop kan zijn, om het levensduur van deClass-E PAs voor een bepaalde uitgangsvermogen beduidend te verhogen. Ookwordt er getoond dat Class-EV V PAs tot ong. 200% meer uitgangsvermogenkunnen hebben dan conventionele Class-E PAs in de zelfde stuursignaal, deload en de betrouwbare piek spanningscondities, met slechts een bescheidenstraf op PAE.

In hoofdstuk 6, worden de voordelen van uitgebreide drain transistors inPAs, in de context van exploratie van de hoog spanning circuit technieken,gepresenteerd. De RF vermogen apparaten bereikten meer dan 70% PAE voor1, 2 en 3.4W uitgangsvermogen bij 2GHz bij standaard 65nm CMOS tech-nologie. De vermogen apparaten werken in sub-optimale Class-E mode, doorhet voordeel van een hoger uitgangsvermogen met een lichte PAE correctie,in vergelijking met conventionele Class-E, onder dezelfde ingangsaansturing,load impedantie en betrouwbaarheidscondities te nemen. Een schaalbare lay-

4dergelijke wijzen van variabele hellingswerking, k > 0 kan als resultaat van antenne’mismatch’ voorkomen of in de waarde van de componenten enz.

100

out benadering in het ontwerp van vermogen apparaten wordt geintroduceerd.Het uitgangsvermogen van vermogen apparaten schalen mee met de afmetin-gen van de apparaten, zonder enige degradatie in PAE en tonen aan dat devermogensefficientie voor hoog vermogen apparaten in CMOS technologie kanworden bewaard.

In hoofdstuk 7, wordt een benadering gentroduceerd om de levensduur vanhoog-spanning analoge circuits in CMOS technologien die op overtolligheidis gebaseerd te verlengen, wat ook bekend is voor de DRAMS in de contextvan exploratie van de degradatie opsporing en verwijdering methodes. Eengrote vermogen transistor is gesegmenteerd in N kleinere parallelle stukken.Als een sub-transistor stuk gaat, dan wordt het automatisch verwijderd uitde samengestelde transistor. Het is experimenteel aangetoond dat de oxidebreakdown digitaal kan worden ontdekt. Voorts is het theoretisch aangetoonddat de degradatie opsporing en verwijdering het levensduur van PAs in CMOStechnologie kunnen verhogen.

Al deze voorgestelde benaderingen dragen bij tot totstandbrenging vanbetrouwbare CMOS PAs in CMOS technologie.

101

References

[1] K.F. Schuegraf and C. Hu, ”RF-CMOS perfomance trends”, IEEE Trans-actions on Electron Devices (T-ED), vol. 48, pp. 1776-1782, 2001.

[2] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G.Hatcher, D. McClymont and A. Hajimiri, ”A Fully-Integrated Quad-BandGSM/GPRS CMOS Power Amplifier”, IEEE Journal of Solid-State Cir-cuits (JSSC), vol. 43, pp. 2747-2758 December 2008.

[3] M. Acar, A. J. Annema and B. Nauta, ”Generalized Design Equationsfor Class-E Power Amplifiers with Finite DC Feed Inductance”, EuropeanMicrowave Conference (EuMC), pp. 1308-1311, September 2006.

[4] M. Acar, A. J. Annema and B. Nauta, ”Generalized Analytical DesignEquations for Variable Slope Class-E Power Amplifiers”, IEEE Interna-tional Conference on Electronics, Circuits and Systems (ICECS), pp. 431-434, December 2006.

[5] M. Acar, A. J. Annema and B. Nauta, ”Analytical Design Equations forClass-E Power Amplifiers with Finite DC Feed Inductance and Switch-on Resistance”, IEEE International Symposium on Circuits and Systems(ISCAS), pp. 2818-2821, May 2007.

[6] M. Acar, A. J. Annema and B. Nauta, ”Variable Voltage Class-E PowerAmplifiers”, IEEE International Microwave Symposium (IMS), pp. 1095-1098, June 2007.

[7] M. Acar, A. J. Annema and B. Nauta, ”Analytical Design Equations forClass-E Power Amplifiers”, IEEE Transactions on Circuits and SystemsI (TCAS-I), regular papers, vol. 54, pp. 2706-2717, December 2007.

[8] I. Aoki, S.D Kee, D.B. Rutledge and A. Hajimiri, ”Distributed ActiveTransformer A New Power-Combining and Impedance TransformationTechnique”, IEEE Transactions on Microwave Theory and Techniques(MTTS), vol. 50, pp. 316-331, January 2002.

[9] M. Acar, M. P. van der Heijden, I. Volkaline, M. Apostolidou, J. Sonskyand J. S. Vromans, ”Scalable CMOS Power Devices with 70% PAE and 1,

103

2 and 3.4 Watt Output Power at 2GHz”, IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, pp. 233-236, June 2009.

[10] B. Kaczer, R. Degraeve, M. Rasras, K. van de Mieroop,P.J Roussel andG. Groeseneken, ”Impact of MOSFET gate oxide breakdown on digitalcircuit operation and reliability”, IEEE Transactions on Electron Devices(T-ED), pp. 500-506, May 2002.

[11] L. Larcher, D. Sanzogni, R. Brama, A. Mazzanti and F. Svelto ”Ox-ide Breakdown After RF Stress: Experimental Analysis And Effects OnPower Amplifier Operation”, IEEE International Reliability Physics Sym-posium (IRPS), pp. 283-288, March 2006.

[12] M. Acar, A. J. Annema and B. Nauta, ”Digital Detection of Oxide Break-down and Life-Time Extension in deep Sub-micron CMOS Technology”,IEEE International Solid-State Circuits Conference (ISSCC), pp. 530-531, February 2008.

[13] C. Yoo and Q. Huang, ”A Common-Gate Switched 0.9-W Class-E PowerAmplifier with 41% PAE in 0.25µm CMOS”, IEEE Journal of Solid-StateCircuits (JSSC), vol. 36, pp. 823-830, May 2001.

[14] I.C. Chen, S.E. Holland and C.Hu, ”Electrical Breakdown in Thin Gateand Tunneling Oxides” IEEE Transactions on Electron Devices (T-ED),vol. 32, pp. 413-422, 1985.

[15] K.F. Schuegraf and C. Hu, ”Hole Injection SiO2 Breakdown Model forVery Low Voltage Lifetime Extrapolation”, IEEE Transactions on Elec-tron Devices (T-ED), vol. 41, NO. 5, pp. 761-767, March 2008.

[16] D.J. DiMaria and J.W. Stasiak, ”Trap Creation in Silicon Dioxide Pro-duced by Hot Electrons” Journal of Applied Physics (AIP), vol. 65, pp.2342-2356, March 1989.

[17] J.W. McPherson and H.C. Mogul, ”Underlying Physics of the Thermo-chemical E Model in Describing Low-Field Time-Dependent DielectricBreakdown In SiO2 Thin Films, Journal of Applied Physics (AIP), vol.84, pp. 1513-1523, August 1998.

[18] Guido T. Sasse, ”Reliability Engineering in RF CMOS”, PhD Thesis, pp.6, July 2008.

[19] M. Depas, T. Nigam and M.M. Heyns, ”Soft Breakdown of Ultra-ThinGate Oxide Layers”, IEEE Transactions on Electron Devices (T-ED), vol.43, pp. 1499-1504, August 1996.

[20] F. Monsieur, E. Vincent, D. Roy, S. Bruyere, J.C. Vildeuil, G.Pananakakis and G. Ghibaudo, ”A Thorough Investigation of Progressive

104

Breakdown in Ultra-thin Oxides. Physical Understanding and Applica-tion for Industrial Reliability Assessment”, IEEE International ReliabilityPhysics Symposium (RELPHY), pp. 45-54, August 2002.

[21] H. Abrishami, S. Hatami, B. Amelifard and M. Pedram, ”NBTI-AwareFlip-Flop Characterization and Design”, Great Lakes Symposium on VLSI(GLSVLSI), pp. 29-34, 2008.

[22] Y. Hong, W. Smith and J.S Yuan, ”Gate Oxide Breakdown on Low Noiseand Power Amplifier Performance”, IEEE Radio Frequency IntegratedCircuits (RFIC) Symposium, pp. 149-152, June 2003.

[23] Yu. Chuanzhao and J.S. Yuan ”MOS RF Reliability Subject to DynamicVoltage Stress-Modeling and Analysis”, IEEE Transactions on ElectronDevices (T-ED), vol. 52, pp. 1751-1758, August 2005.

[24] J.S. Yuan, J. Ma, ”Evaluation of RF-Stress Effect on Class-E MOS Power-Amplifier Efficiency”, IEEE Transactions on Electron Devices (T-ED),vol. 55, pp. 430-434, January 2008.

[25] G.T. Sasse, M. Acar, F.G. Kuper and J. Schmitz, ”RF CMOS Reliabil-ity Simulations”, Microelectronics Reliability, vol.48, pp. 1582-85, August2008.

[26] cadence white paper, ”Reliability simulation in integrated circuit design”,http://w2.cadence.com/whitepapers/5082

ReliabilitySim FNL WP.pdf

[27] M. Karam, W. Fikry, H. Haddara and H. Ragai, ”Implementation of hot-carrier reliability simulation in Eldo”, IEEE International Symposium onCircuits and Systems (ISCAS), pp. 515-518, May 2001.

[28] E. Rosenbaum, P.M. Lee, R. Moazzami, P.K. Ko and C. Hu, ”Circuit Re-liability Simulator-Oxide Breakdown Module”, IEEE International Elec-tron Devices Meeting (IEDM), pp. 331-334, December 1989.

[29] G.D. Ewing, ”High-Efficiency Radio-Frequency Power Amplifier” PhDthesis, Oregon State Unicersity, Corvallis, Oregon, June 1964.

[30] N.O.Sokal and A.D Sokal, ”Class E - A New Class of High-EfficiencyTuned Single-Ended Switching Power Amplifiers”, IEEE Journal of Solid-State Circuits (JSSC), vol. 10, pp. 168-176, June 1975.

[31] F. H. Raab, ”Idealized operation of the class E tuned power amplifier”,IEEE Transactions on Circuits and Systems (TCAS), vol. 24, pp. 725-735,December 1977.

[32] F.H. Raab, ”Effects of circuit variations on the class E tuned power ampli-fier”, IEEE Journal of Solid-State Circuits (JSSC), vol. 13, pp. 239-247,April 1978.

105

[33] S.T. Hung-Lung and C. Toumazou, ”Effect of the Loaded Quality Factoron Power Efficiency for CMOS Class-E RF Tuned Power Amplifiers”,IEEE Transactions on Circuits and Systems I (TCAS-I), vol. 46, pp.628-634, May 1999.

[34] M.K. Kazimierczuk and K. Puczko, ”Power-output capability of class Eamplifier at any loaded Q and switch duty cycle”, IEEE Transactions onCircuits and Systems (TCAS), vol. 36, pp. 1142-1143, August 1989.

[35] M. K. Kazimierczuk and K. Puczko, ”Exact Analysis of Class-E TunedPower Amplifier at any Q and Switch Duty Cycle” IEEE Transactions onCircuits and Systems (TCAS), vol. 34, pp. 149-158, February 1987.

[36] M. K. Kazimierczuk, ”Effects of the collector current fall time on the classE tuned power amplifier”, IEEE Journal of Solid-State Circuits (JSSC),vol. 18, pp. 181-193, April 1983.

[37] P. Alinikula, ”Optimum Component Values for a Lossy Class E PowerAmplifier”, IEEE International Microwave Symposium (IMS), vol. 3, pp.2145-2148, June 2003.

[38] J. A. Blanchard and J. S. Yuan, ”Effects of Collector Current Exponen-tial Decay on Power Efficiency for Class-E Tuned Power Amplifier, IEEETransactions on Circuits and Systems I (TCAS-I), regular papers, vol.41, pp. 69-72, January 1994.

[39] R. Zulinski and J. Steadman, ”Class E Power Amplifiers and FrequencyMultipliers with finite DC-Feed Inductance”, IEEE Transactions on Cir-cuits and Systems (TCAS), vol. 34, pp. 1074-1087, September 1987.

[40] C.H. Li and Y.O. Yam, ”Maximum Frequency and Optimum Performanceof Class E Power Amplifiers”, IEE Circuits, Devices and Systems, vol. 141,pp. 174-184, June 1994.

[41] D.K. Choi and S.I. Long, ”Finite DC Feed Inductor in Class-E Power Am-plifiers - A Simplified Approach”, IEEE International Microwave Sympo-sium (IMS), vol. 3, pp. 1643-1646, June 2002.

[42] H. Sekiya, I. Sasase and S. Mori, ”Computation of design values for ClassE amplifiers without using waveform equations”, IEEE Transactions onCircuits and Systems I (TCAS-I), regular papers, vol. 49, pp. 966-978,July 2002.

[43] P. Reynaert, K.L.R. Mertens and M.S.J. Steyaert, ”A state-space behav-ioral model for CMOS class E power amplifiers”, IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems (TCAD), pp.132-138 vol. 22, February 2003.

106

[44] C. Wang, L.E. Larson and P.M. Asbeck, ”Improved design technique ofa microwave Class-E power amplifier with finite switching-on resistance”,IEEE Radio and Wireless Conference (RAWCON), pp. 241-244, August2002.

[45] Y.B. Choi and K.K.M. Cheng, ”Generalised Frequency-Domain Analysisof Microwave Class-E Power Amplifiers”, IEE of Microwaves, Antennasand Propagation, vol. 148, pp. 403-409, December 2001.

[46] C.P. Avratoglou, N.C. Voulgaris and F.I. Ioannidou, ”Analysis and designof a generalized class E tuned power amplifier”, IEEE Transactions onCircuits and Systems (TCAS), vol. 36, pp. 1068-1079, August 1989.

[47] D. Milosevic, J. van der Tang and A. van Roermund, ”Explicit designequations for Class-E power amplifiers with small DC-feed inductance”,European Conference on Circuit Theory and Design on vol. 3, pp. 101-104,September 2005.

[48] A.V. Grebennikov, ”Load Network Design Techniques for Class-E RF andMicrowave Amplifiers”, High Frequency Electronics, July 2004.

[49] A.V. Grebennikov and H. Jaeger, ”Class E with Parallel Circuit - A NewChallenge for High-Efficiency RF and Microwave Power Amplifiers” IEEEInternational Microwave Symposium (IMS) vol. 3, pp. 1627-1630, June2002.

[50] M. Iwadare, S. Mori, and K. Ikeda, ”Even Harmonic Resonant Class-ETuned Power Amplifier without RF Choke”, Electronics and Communi-cations in Japan vol. 79, pp. 23-30, Jan. 1996.

[51] G.H. Smith and R.E. Zulinski, ”An Exact Analysis of Class-E Amplifierswith Finite DC-feed Inductance at any Output Q”, IEEE Transactionson Circuits and Systems (TCAS), vol. 37, pp. 530-534, April 1990.

[52] D.Y.C. Lie, P. Lee, J.D. Popp, J.F. Rowland, H.H. Ng and A.H. Yang,”The limitations in applying analytic design equations for optimal classE RF power amplifiers design”, IEEE International Symposium on VLSIDesign, Automation and Test (VLSI-TSA-DAT), pp. 161-164, April 2005.

[53] Y.H. Chee, J. Rabaey and A.M. Niknejad, ”A class A/B low power am-plifier for wireless sensor networks”, IEEE International Symposium onCircuits and Systems (ISCAS), pp. 409-412, May 2004.

[54] H.S. Oh, T. Song, E. Yoon and C.K. Kim, ”A power-efficient injection-locked Class-E power amplifier for wireless sensor network”, IEEE Mi-crowave and Wireless Components Letters (MWCL), vol. 16, pp. 173-175,April 2006.

107

[55] P. L. D. Abrie, ”Design of Impedance-Matching Networks for Radio-Frequency and Microwave Amplifiers”, Norwood, MA: Artech House,1985.

[56] D. K. Choi and S. I. Long, ”A Physically Based Analytic Model of FETClass E Power Amplifiers Designing for Maximum PAE”, IEEE Trans.on Microwave Theory and Techniques, vol. 47, pp. 1712-1720, September1999.

[57] D. K. Choi, ”High Eficiency Switched-Mode Power Amplifiers For Wire-less Communications”, PhD thesis, page 121.

[58] P. Alinikula, ”Optimum component values for a lossy Class E power am-plifier”, IEEE International Microwave Symposium (IMS), vol. 3, pp.2145-2148, June 2003.

[59] C.K. Ho, H. Wong and S.W. Ma, ”Approximation of Non-zero TransistorOn Resistance in Class-E Amplifiers”, IEEE International Caracas Con-ference on Devices, Circuits and Systems (ICCDCS), vol. 1, pp. 90-93,November 2004.

[60] H. Sekiya , I. Sasase and S. Mori, ”Computation of design values for ClassE amplifiers without using waveform equations”, IEEE Transactions onCircuits and Systems I (TCAS-I) vol. 49, pp. 966-978, July 2002.

[61] P. Reynaert, K.L.R. Mertens and M.S.J. Steyaert, ”A state-space behav-ioral model for CMOS class E power amplifiers”, IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems (TCAD), vol.22, pp. 132-138, February 2003.

[62] J.C. Mandojana, K.J. Herman and R.E. Zulinski, ”A Discrete-ContinuousTime-Domain Analysis of a Generalized Class E Amplifier”, IEEE Trans-actions on Circuits and Systems (TCAS), vol. 37, pp. 1057-1060, August1990.

[63] Y.B. Choi and K.K.M. Cheng ”Generalised Frequency-Domain Analysisof Microwave Class-E Power Amplifiers”, IEE of Microwaves, Antennasand Propagation, vol. 148, pp. 403-409, December 2001.

[64] M.M. Tabrizi and N. Masoumi, ”High efficiency Class-E switched modepower amplifier design and optimization with random search algorithm”,International Conference on Microelectronics (ICM), pp. 283-286, Decem-ber 2004.

[65] J.K. Jau, Y.A. Chen, T.S. Horng, and T.L. Wu ”Optimum AnalyticalDesign Solution to Integrated Class-E Amplifiers” Proceeding of WirelessNetworks and Emerging Technologies, 2005

108

[66] T. Mury and V.F. Fusco, ”Analysis and Synthesis of pHEMT Class-EAmplifiers with Shunt Inductor Including ON-state Active-Device Resis-tance Effects”, IEEE Transactions on Circuits and Systems I (TCAS-I),regular papers, vol. 53, pp. 1556-1564, July 2006.

[67] M. Albulet and R.E. Zulinski, ”Effect of switch duty ratio on the perfor-mance of Class E circuits”, Midwest Symposium (MWSCAS), pp. 99-105,Aug. 1997.

[68] M. Apostolidou, M.P. van der Heijden, D.M.W Leenaerts, J. Sonsky, A.Heringa and I. Volokhine, ”A 65nm CMOS 30dBm Class-E RF PowerAmplifier with 60% Power Added Efficiency”, IEEE Radio Frequency In-tegrated Circuits (RFIC) Symposium, pp. 141-144, June 2008.

[69] R. Brama, L. Larcher, A. Mazzanti and F. Svelto, ”A 1.7 GHz 31 dBmdifferential CMOS differential CMOS Class-E Power Amplifier with 58%PAE”, IEEE Custom Integrated Circuits Conference (CICC), pp. 551-554,September 2007.

[70] W. Zhang, E. Khoo and T. Tear, ”A Low Voltage Fully-Integrated 0.18umCMOS Power Amplifier for 5GHz WLAN”, European Solid-State CircuitsConference (ESSCIRC), pp. 215-218, September 2002.

[71] J. Sonsky, A. Heringa, J. Perez-Gonzalez, J. Benson, P.Y. Chiang, S.Bardy and I. Volokhine, ”Innovative High Voltage Transistors for Com-plex HV/RF SoCs in Baseline CMOS”, International Symposium on VLSITechnology, Systems and Applications (VLSI-TSA), pp. 563-566, June2008.

[72] D.E. Kelly, K. Mekechuk and T. Miller, ”Switch-Mode Power AmplifierLinearization”, IEEE Radio Frequency Integrated Circuits (RFIC) Sym-posium, pp. 153-156, June 2008.

[73] T. Cooper and R. Farrell, ”Value-Chain Engineering of a Tower-Top Cellu-lar Base Station System”, IEEE Vehicular Technology Conference (VTC),pp. 3184-3188, April 2007.

[74] I. Volokhine, ”An Extension of Existing Real-Time Load Pull Systemsto Perform Voltage/Current Waveform Reconstruction” , Automatic RFTechniques Group (ARFTG) Microwave Measurement Symposium, pp.80-83, June 2008.

[75] C. Weyers, D. Kehrer, J. Kunze, P. Mayr, D. Siprak, M. Tiebout, J. Haus-ner and U. Langmann, ”Improved RF-Performance of Sub-Micron CMOSTransistors by Asymmetrically Fingered Device Layout”, IEEE RadioFrequency Integrated Circuits (RFIC) Symposium, pp.563-566, June 2008.

109

[76] S.D. Kee, I. Aoki, A. Hajimiri and D. Rutledge ”The Class-E/F family ofZVS switching amplifiers”, IEEE Transactions on Microwave Theory andTechniques (MTT), vol. 51, pp. 1677-1690, June 2003.

[77] T. Suetsugu and M.K. Kazimierczuk, ”Analysis of Sub-Optimum Oper-ation of Class E Amplifier”, IEEE International Symposium on Micro-NanoMechatronics and Human Science, vol. 3, pp. 1071-1074, December2003.

[78] A. Mediano and P. Molina, ”Frequency Limitation of a High EfficiencyClass-E Tuned RF Power Amplifier Due to a Shunt Capacitance”, IEEEInternational Microwave Symposium (IMS), pp. 363-366, June 1999.

[79] B. Molnar, ”Basic Limitations on Waveforms Achievable in Single-EndedSwitching-Mode Tuned (Class E) Power Amplifiers”, IEEE Journal ofSolid-State Circuits, vol.19, pp. 144-146, February 1984

[80] A. Mazzanti, L. Larcher, R. Brama and F. Svelto ”Analysis of Reliabilityand Power Efficiency in Cascode Class-E PAs” IEEE Journal of Solid-State Circuits (JSSC), vol.24, pp. 1222-1229, May 2006.

[81] S. M. R. Hasan, ”A High Efficiency 3GHz 24-dBm CMOS Linear PowerAmplifier for RF Application”, International Workshop on System-on-Chip for Real-Time Applications (IWSOC), pp. 503-507, July 2005.

[82] N. Cressie, ”A Finely Tuned Continuity Correction”, Annals of the Insti-tute of Statistical Mathematics (AISM), vol. 30, pp. 435-442, May 1978.

[83] http://en.wikipedia.org/wiki/Weibull distribution

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Appendix-A: PhysicalMeanings of the Elementsof the Design Set K

In this appendix, a rough description of the physical meanings of the elementsof the design set K = KL, KC , KX , KP and the variables d, q, p are given.

(b)

tuned at w0

C

L

VC

IC

IR

IS

C0

R

VDD

IL

XL0

(a)

R

VDD

IDC

P =V /RDC DD

2

P = K V /ROUT DD

2

P

Fig. 8.1: (a) Supply Voltage-Resistive Load (b) Idealized Class-E PA

8.4.1 Physical Meaning of the Design Set K

The design set (K) elements KL = ωLR , KC = ωCR, KX = X

R are defined asthe impedance of the passive elements at the operation frequency to the loadR. The physical meaning of the term KP can be explained by using Fig. 8.1.

An ideal Class-E power amplifier can convert DC power to AC power with100% drain efficiency. The DC power that can be obtained from a DC source

(VDD) for a resistive load of R is PDC =V 2

DD

R , Fig. 8.1a. For the Class-E PAin Fig. 8.1b the output power is KP times higher than the power in Fig. 8.1a.Therefore, the term KP can be named as ”power scaling factor”.

8.4.2 Physical Meaning of the variables d, q and p

The variable d directly determines the switch duty-cycle= (50d)%. For exam-ple, d = 1 corresponds to 50% switch duty-cycle.

111

The variable q =ωp

ω . Here ωp = 1/√

LC is the angular frequency to whichL − C parallel network is tuned. Therefore, physically q can be seen as theratio of the parallel tuned frequency (ωp) to operation frequency (ω).

By using IR =√

2 I0VDD

R from 3.13, p can expressed as:

p =ωLVDD

IR

=√

2ωL√

R · RDC

=√

2ωL

Rgeom(8.1)

where, Rgeom =√

R · RDC . RDC = VDD/I0 is the resistance that the amplifiershows to the power supply and Rgeom is the geometrical mean of RDC and R.

From a physical point of view, the variable p corresponds to the ratio ofthe impedance of L at the operation frequency (ω) to the resistance Rgeom.

In this appendix, the analytical solution for the variables p and ϕ are givenas well as the analytical solution for the design set (K) element KX .

8.4.3 Analytical Solution for the Set of Equations

For proper Class-E operation two equations, (8.3)-(8.4), were derived. In thisappendix, the analytical solution for this set of equations is given, leading tothe generalized design equation continuum for Class-E PAs.

p1(q, d) =

√ppa + ppb

ppc(8.2)

where, ppa =

(

b2 (q, d)2 + a2(q, d)2)(

c1(q, d)2 + c2(q, d)2)

,

ppb = −2

(

a1(q, d)a2(q, d) + b2(q, d)b1(q, d)

)

c2(q, d)c1(q, d)

and ppc = −a1(q, d)b2(q, d) + b1(q, d)a2(q, d)

f1(p, ϕ, q, d) = p(

a1(q, d) sin(ϕ) − (8.3)

b1(q, d) cos(ϕ))

− c1(q, d) = 0

f2(p, ϕ, q, d) = p(

a2(q, d) sin(ϕ) − (8.4)

b2(q, d) cos(ϕ))

− c2(q, d) = 0

112

Two out of the four variables can be expressed in terms of q and d using (8.3)-

(8.4). The solution set is(

p1(q, d), ϕ1(q, d))

,(

p2(q, d), ϕ2(q, d))

where the

elements are given by (8.2)-(8.7).

p2(q, d) = −p1(q, d) (8.5)

ϕ1(q, d) = arctan(

− b2 (q, d)c1 (q, d) + c2 (q, d)b1 (q, d),

−a1 (q, d)c2 (q, d) + c1 (q, d)a2 (q, d))

(8.6)

ϕ2(q, d) = arctan(

b2 (q, d)c1 (q, d) − c2 (q, d)b1 (q, d),

a1 (q, d)c2 (q, d) − c1 (q, d)a2 (q, d))

(8.7)

The definition for arctan(y, x): the angle in radians between the positive x-axisand the line from (0,0) to (x,y).

a1(q, d) = −1 − 1

q− sin (2 qπ) q sin (qdπ)

1 − q2+

q cos (dπ)

1 − q2−

q cos (2 qπ) cos (qdπ)

1 − q2 + cos (dπ)

b1(q, d) = −1

q−q2 cos (2 qπ) sin (qdπ)

1 − q2+

q sin (dπ)

1 − q2+

sin (2 qπ) q2 cos (qdπ)

1 − q2 + sin (dπ)

c1(q, d) = dπ − cos (2 qπ) sin (qdπ) − sin (2 qπ) cos (qdπ)

q

a2(q, d) = −q cos (2 qπ) sin (qdπ)

1 − q2 +

sin (2 qπ) q cos (qdπ)

1 − q2+

q2 sin (dπ)

1 − q2

b2(q, d) = −q2 cos (dπ)

1 − q2+

sin (2 qπ) q2 sin (qdπ)

1 − q2+

q2 cos (2 qπ) cos (qdπ)

1 − q2

c2(q, d) = − sin (2 qπ) sin (qdπ) − cos (2 qπ) cos (qdπ) + 1

8.4.4 Analytical Expression for KX(q, d)

The design set KX(q, d) can be obtained in terms of q and d. In order to obtainthe analytical expression for KX(q, d) two fundamental quadrature Fouriercomponents of VC(t) can be used.

113

VR =1

π

∫ 2π/ω

0

(VC(t) sin(ωt + ϕ)) dt

VX =1

π

∫ 2π/ω

0

(VC(t) cos(ωt + ϕ)) dt

KX(q, d) =VX

VR=

x1 + x2 + x3 + x4

y1 + y2 + y3 + y4

where

y1(q, d) = −(

− (cos (dπ))2

+ 1)

q2 (cos (ϕ))2pVDD

y2(q, d) = −

q2 sin (dπ) cos (dπ) sin (ϕ) p −

q2 cos (dπ) + q2 − 1 + cos (dπ)VDD +

cos (dπ) sin (qdπ) − q sin (dπ) cos (qdπ) −2 sin (qπ) cos (qπ)C2 + cos (dπ) cos (qdπ)

+1 + q sin (dπ) sin (qdπ)

−2 (cos (qπ))2C1

cos (ϕ)

y3(q, d) = −

(

−1 + q2)

sin (dπ)VDD +

(

−1 + 2 (cos (qπ))2 − cos (dπ) cos (qdπ)

)

q

− sin (dπ) sin (qdπ)C2 + cos (dπ) sin (qdπ)

−2 sin (qπ) cos (qπ)q− sin (dπ) cos (qdπ)C1

sin (ϕ)

y4(q, d) = −

(

−1 + (cos (dπ))2)

q2pVDD

2

x1(q, d) = q2pVDD sin (dπ) cos (dπ) (cos (ϕ))2

x2(q, d) =

(

−1 + q2)

sin (dπ) VDD +

−1 + 2 (cos (qπ))2 − cos (dπ) cos (qdπ)q− sin (dπ) sin (qdπ)C2

+(cos (dπ) sin (qdπ) − sin (2 qπ)) q −sin (dπ) cos (qdπ)C1

cos (ϕ)

114

x3(q, d) =

((−2 p + 2 p (cos (dπ))2) cos (ϕ) − 2 +

2 cos (dπ))q2 + 2 − 2 cos (dπ)

sin (ϕ) VDD +

− 2 cos (dπ) sin (qdπ) + 2 q sin (dπ) cos (qdπ)

+4 sin (qπ) cos (qπ)

sin (ϕ)C2 +

− 2 q sin (dπ) sin (qdπ) − 2 cos (dπ) cos (qdπ)

−2 + 4 (cos (qπ))2

sin (ϕ)C1

x4(q, d) =

(

q2pdπ − q2p sin (dπ) cos (dπ) − 2 q2pπ)

VDD

2

115

Appendix-B: Solution forp and ϕ in terms of q andm

In this section the solution for p and ϕ in terms of q and m are given5.

p =

√

(g1h3 − g3h1)2

+ (h2g3 − h3g2)2

−g1h2 + g2h1

ϕ = arctan (h2g3 − h3g2, g1h3 − g3h1)

g1 =−eaπ

(

A + bmq2)

+ ebπ(

A + amq2)

B (−b + a)− q sin (qπ)

q2 − 1+

mq2

B

g2 = − (cos (qπ) + 1) q2

q2 − 1+

m2q2 (q − 1) (q + 1)

B+

−eaπ(

Ab − mq2)

+ ebπ(

Aa − mq2)

B (−b + a)

g3 =ebπ(−α + (1 − α)ma) − eaπ(−α + (1 − α)mb)

−b + a−

cos (qπ) (1 − α)

h1 =m3q2 (q − 1) (q + 1)

B− q (m cos (qπ) q + sin (qπ) + mq)

q2 − 1

+m(aeaπ

(

A + bmq2)

B (−b + a)− bebπ

(

A + mq2a)

B (−b + a)

)

(8.8)

5Two roots exist for p and ϕ. The second root is p′=-p and ϕ′ =arctan (−h2g3 + h3g2,−g1h3 + g3h1). Both roots result in the same K.

117

h2 = −m2q2

B+

q2 (m sin (qπ) q − cos (qπ) − 1)

q2 − 1

+m(aeaπ

(

Ab − mq2)

B (−b + a)− bebπ

(

Aa − mq2)

B (−b + a)

)

h3 =(

1 − α)(

− cos (qπ) + m sin (qπ) q)

+ 1 +(

aeaπ(

− α + (1 − α)mb)

−b + a− bebπ

(

− α + (1 − α)ma)

−b + a

)

A =(

q4 − q2)

m2andB = 1 + m2q4 − 2 m2q2 + m2

118

Appendix-C: Theory ofBreakdown Detectionand Elimination Method

8.5 Defect distribution

Assuming no defects of weak spots in the (power) transistors, the individualbreakdown events spread uniformly across the N-sections of the transistor,resulting in a binomial distribution in each section with a probability massfunction (pmf):

p(n) =

(

events

n

)

1

Nn(1 − 1

N)(events−n) (8.9)

where,n is the number of breakdown event in a sectionevents is the total number of breakdown events for the N sections

The mean and variance of this distribution are:µ = events

N

σ =√

eventsN−1N2 .

The cumulative distribution function (cdf) P (n) =∫ n

−∞ p(x)dx representsthe probability that the random variable is smaller than or equal to n. Thiscan be used to estimate the distribution of the number of events in e.g. thetransistor section containing the most breakdown events. Note that the num-ber of events in the section with the most breakdown events must satisfy:

Nmax−sections ≥ µNmax−sections ≤ events

The exact derivation of the pmf of the number of breakdown events in thefullest section is at the least complex because both of the discrete nature of thebinomial distribution and because of the conditional origin of it. Therefore,

119

we estimate the pmf of the breakdown in the fullest section using a continuouspmf: the normal distribution function.

For not-small numbers of events in each section, it is well known that thebinomial distribution function can be approximated by the normal distribu-tion. Usually a small continuity correction factor in the variances of both isrequired to make the distributions fit nicely [82]. Later in this supplementarymaterial the alternative case — just a small number of breakdown events ineach section — will be discussed briefly. For a normal-like pmf the tail of thedistribution corresponds to the pmf of the events in the fullest (or emptiest)section(s): this distribution is clearly very asymmetric. It appears that a rea-sonable fit of the distribution in the fullest sections can be obtained using aWeibull-distribution:

p(x) = (k

λ)(

x − θ

λ)(k−1)e−( x−θ

λ)k

(8.10)

For which suitable fitting parameters are listed below. The parameter kdetermines the shape of the pmf; a suitable value is:

k = 3 (shape parameter)The parameter θ corresponds to a shift of the pmf across the x-axis. For x <

θ the pmf is zero and positive elsewhere. A pessimistic estimate on the lowerbound of the pmf in the fullest section (hence on θ) is then equal to the meanof the number of events in each transistor section, µ. This pessimistic estimatecorresponds to a worst-case estimate on the lifetime-gain in this section.

θ = µ (location parameter)The scale parameter λ determines the width of the probability density

function, and can be estimated from the distributions of events of the sections.The easiest way to get a fair estimation is to estimate the median of the distri-bution of the section containing the most breakdown events, and calculatingfrom the median the λ. This results in [83]:

λ =median − µ

ln(2)1/k(8.11)

median ≈ F−1(1 − 1

N) + µ (8.12)

Approximating the F (cumulative distribution function) of the binomialfunction with that of a normal distribution — including the typical correctionfactor — yields:

λ ≈ (√

2 · erf−1(1 − 2N ) + 0.4)σ

ln(2)1/k(8.13)

In this relation, the inverse error function originates from the (approxi-mating) cumulative normal distribution function, the 0.4 is the typical excessfactor [82] for mapping a binomial distribution onto a normal distribution and

120

the σ corresponds to the standard deviation of the number of breakdown eventsin each section.

A number of numerical simulations were done to verify the results of thepresented fit-estimations. The distribution data – with the same event densi-ties — for both figures are:

Fig. 8.2a Fig. 8.2b

number of sections 16 6number of breakdown events 107 40Median per section:-total 6.69 6.66-fullest section 11.3 9.72

Variance per section:-total 6.27 5.55-fullest section 2.3 2.1

The smooth (Gaussian-like) curve is the Weibull curve, with parametersextracted directly from the breakdown event distribution as derived above (i.e.not fitted to simulated data). These results illustrate that the above presentedestimation gives a good approximation of the distribution of the events in thefullest sections.

number of breakdowns in one section

pro

bab

ilit

y

(a)

pro

bab

ilit

y

number of breakdowns in one section(b)

Fig. 8.2: Probability mass functions over all sections, and of the fullest twosections; For both figures the same defect density but different number ofsections

121

8.6 Discussion

In the figures above, the 16 section situation corresponds to the system im-plemented by us, while the 6 section situation was used for the simulationsfor illustration purposes. From e.g. the median of events in each section inthe table, it follows that this 6 section situation performs not as good as the16 section situation. This can also be seen from the ratio between the aver-age number of breakdown events in the fullest section and the average in allsections, as a function of the number of sections (at constant total breakdownevents):

1

1,5

2

2,5

3

3,5

4

4,5

5

0 10 20 30 40 50

Into

tal 30 Bre

akdown Events

In total 107 Breakdown Events

number of sections

nu

mb

er

of

bre

ak

do

wn

ra

tio

(fu

lle

st/

av

era

ge

)

Fig. 8.3: The ratio between the number of breakdowns in the fullest sectionand the average number of breakdowns, as a function of the number of sectionfor 2 total number of events

With an increasing number of sections, the relative number of breakdownevents in the fullest bins (with respect to the average over all sections) in-creases. Therefore, eliminating the sections with the most breakdown eventsis more efficient for low average numbers of breakdown events per section. Inour system, we employed 16 sections which is effective to increase lifetime forup to (in total) a few hundreds of breakdown events. For a low number of ac-ceptable breakdown events, the effectiveness is even much higher, see Fig. 8.4for the ratio between the number of breakdown in the fullest and the numberof breakdown (average) in any section.

122

0

2

4

6

8

10

12

14

16

0 25 50 75 100 125 150

number of breakdown

nu

mb

er

of

bre

ak

do

wn

ra

tio

(fu

lle

st/

av

era

ge

)

Fig. 8.4: The ratio between the number of breakdowns in the fullest section andthe average number of breakdowns, as a function of the number of breakdownsfor 16 sections

123

List of Publications

1. M. P. van der Heijden, M. Acar, J. Vromans and D. Calvillo, ”A 19WHigh-Efficiency Wide-Band CMOS-GaN Class-E Chireix RF Outphas-ing Power Amplifier”, IEEE International Microwave Symposium (IMS),June 2011 (submitted).

2. R. Zhang, M. Acar, M. P. van der Heijden, L. C. N. de Vreede and D.Leenaerts, ”A 550-1050MHz +30dBm Class-E Power Amplifier in 65nmCMOS”, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,June 2011 (submitted).

3. David A. Calvillo-Corts, M. Acar, M. P. van der Heijden, M. Apostoli-dou, L. C.N. de Vreede, D. Leenaerts and J. Sonsky, ”A 65nm CMOSPulse Width Controlled Driver with 8Vpp Output Voltage for Switch-Mode RF PAs up to 3.6GHz”, IEEE International Solid-State CircuitsConference (ISSCC), February 2011 (accepted).

4. M. C. A. van Schie, M. P. van der Heijden, M. Acar, A. J. M. deGraauw, and L. C. N. de Vreede, ”Analysis and Design of a Wide-BandPower Combining Network for an Efficient Outphasing Power Amplifier”,IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 399-402, May 2010.

5. M. Acar, M. P. van der Heijden, I. Volkaline, M. Apostolidou, J. Son-sky and J. S. Vromans, ”Scalable CMOS Power Devices with 70% PAEand 1, 2 and 3.4 Watt Output Power at 2GHz”, IEEE Radio FrequencyIntegrated Circuits (RFIC) Symposium, pp. 233-236, June 2009.

6. M. P. van der Heijden, M. Acar and J. S. Vromans, ”A Compact 12-Watt High-Efficiency 2.1-2.7 GHz Class-E GaN HEMT Power Amplifierfor Base Stations”, IEEE International Microwave Symposium (IMS),pp. 657-660, June 2009.

125

7. G. T. Sasse, M. Acar, F. G. Kuper and J. Schmitz, ”RF CMOS relia-bility simulations”, Microelectronics Reliability, vol. 48, pp. 1581-1585,August 2008.

8. M. Acar, A. J. Annema and B. Nauta, ”Digital Detection of OxideBreakdown and Life-Time Extension in deep Sub-micron CMOS Tech-nology”, IEEE International Solid-State Circuits Conference (ISSCC),pp. 530-531, February 2008.

9. M. Acar, A. J. Annema and B. Nauta, ”Analytical Design Equationsfor Class-E Power Amplifiers”, IEEE Transactions on Circuits and Sys-tems I (TCAS-I), regular papers, vol. 54, pp. 2706-2717, December 2007.

10. M. Acar, A. J. Annema and B. Nauta, ”Variable Voltage Class-EPower Amplifiers”, IEEE International Microwave Symposium (IMS),pp. 1095-1098, June 2007.

11. M. Acar, A. J. Annema and B. Nauta, ”Analytical Design Equations forClass-E Power Amplifiers with Finite DC Feed Inductance and Switch-on Resistance”, IEEE International Symposium on Circuits and Systems(ISCAS), pp. 2818-2821, May 2007.

12. M. Acar, A. J. Annema and B. Nauta, ”Generalized Analytical DesignEquations for Variable Slope Class-E Power Amplifiers”, IEEE Inter-national Conference on Electronics, Circuits and Systems (ICECS), pp.431-434, December 2006.

13. M. Acar, A. J. Annema and B. Nauta, ”Generalized Design Equationsfor Class-E Power Amplifiers with Finite DC Feed Inductance”, Euro-pean Microwave Conference (EuMC), pp. 1308-1311, September 2006.

126

List of Patents

1. M. P. van der Heijden, M. Acar and J. S. Vromans ”ReconfigurableIntegrated Chireix Out-phasing PA”, ID 81394068, 26 November 2009.

2. M. P. van der Heijden, M. Acar and J. S. Vromans ”Chireix compen-sation in Quad (Switch) LINC concept”, ID 81363020, 03 April 2008.

3. M. P. van der Heijden, M. Acar, J. S. Vromans and M. Apostolidou”Method of increasing efficiency in a switching-mode RF amplifier”, ID81362495, 30 March 2008.

4. M. Acar and K. Nowak ”Differential driving of HV power inverters us-ing triple-well option” ID 81362043, 25 March 2008.

5. M. Acar, M. P. van der Heijden, M. Apostolidou and J. S. Vromans”Switch Power Lossless and High Voltage Driver”, ID 81359474, 21February 2008.

6. M. Apostolidou, M. P. van der Heijden and M. Acar ”Accurate dutycycle and phase generation”, ID 81349845, 08 November 2007.

7. M. Acar, M. P. van der Heijden and M. Apostolidou ”Digital Protectionof Power Amplifier”, ID 81349923, 31 October 2007.

127

Acknowledgement

No research is done alone. Many people contributed to this research work inmany different ways.

First of all, I would like to thank my promoter Bram Nauta, for giving methe chance to conduct research in his group. His encouragement after everymeeting was very motivating in my progress. Every group uitje with Bramwas another cheerful activity.

I would like to deeply thank Anne Johan Annema for his encouragement,support and thoughtful discussions at difficult problems. His friendly person-ality, ability to listen patiently even the most wild ideas proved an essentialfactor in the success of my research. His keenness to understand the essenceof a problem aided my ability in developing a problem solving approach. Hispatience to bare with my broken Dutch is greatly appreciated. Working withyou Anne Johan was really fun. Many thanks for all your efforts!

I finished my master thesis also in the IC Design group, which left withme many nice memories of the people from this group. Being my first su-pervisor and witnessing my difficult times in a new country, the support ofEric Klumperink is much appreciated. Eric, I still regret not having stayed inHawaii (IMS conference) for two more days.

I would like to thank my paranimf Guido Sasse for his friendship as well asall the nice discussions and brainstorming sessions on the same project. Ourdiscussions were often very useful, and it is during one such discussion, whilsthaving dinner at your house, that the segmented power device concept wasborn.

I would like to thank those people whom I have had the opportunity tosupervise: Talitha Faber, Bram Verhoef, Wei Cheng, Egbert Bouwmeester,Gurhan Vural, David Calvillo, Ronghui Zhang, Mark van Schie. Your contri-butions to my research is very much appreciated.

I would like to thank Henk de Vries for supporting me during the measure-ment activities of this project. My special thanks also to Gerard de Wienk,for helping me overcome an esd issue during one of the measurements. Yourhelp was so essential and is warmly appreciated.

I would also like to thank Gerdien and Annemiek for their secretarial sup-port. Gerdien, I still remember with a smile, when you timely reminded methat I was leaving for Schiphol a day earlier than the departure date for my

129

first ever conference trip abroad.I would like to acknowledge my colleagues with whom I enjoyed having

lunch/brain storming sessions: Stephan Blaakmeer, Firrao Lorenzo, DanielSchinkel, Eisse Mensink, Dlovan Mahrof, Kasra Garakoui, Fabian Houwelin-gen, Salma Hamdi, Muhammed Bolatkale.

The support of Domine Leenaerts during the user committee meetings inthe form of critical feedback and his help in the production of chips at NXP isacknowledged. As my supervisor during my masters’ thesis work at Integratedthe Transceivers Group of Philips and as a colleague at NXP, I am very gratefulfor all the encouragement and support that I have enjoyed from you over sucha long time.

I address my acknowledgement also to my colleagues Mark van der Hei-jden and Melina Apostolidou at NXP. Our discussions and work experienceundoubtedly aided and enhanced the formulation of this thesis. Moreover, Iwould like to thank to Iouri Volokhine for conducting measurements on hisactive load-pull test system.

I would like to express my appreciation to Frank van Fliet for his extensivecomments on the thesis.

My family, being another challenge during my PhD work each of them withtheir own specific peculiar issues also deserves to be mentioned. No matterhow big we are as a family, 3 brothers and 3 sisters, I love each of you. Myspecial thanks to my mother and father for sacrificing many things in theirown life and happiness to bring up and educate the 6 of us.

And last but not least, I would like to express my gratitude to my girlfriendSandy. Your sacrifice and understanding was a big help during the formulationof this thesis.

130

Dankwoord

Geen enkel onderzoek wordt alleen gedaan. Aan dit onderzoek hebben veelmensen hun bijdrage geleverd op uiteenlopende manieren.

Als eerste wil ik mijn promotor, Bram Nauta, bedanken voor het geven vande mogelijkheid om onderzoek te verrichten in zijn groep. Zijn aanmoedigingna elke vergadering was erg motiverend in de voortgang van mijn onderzoek.Daarnaast was elk groepsuitje ook altijd een vrolijke gebeurtenis.

Ik wil Anne Johan Annema ook zeer hartelijk danken voor zijn aanmoedig-ing, ondersteuning en het meedenken zelfs tijdens moeilijke momenten. Zijnvriendelijke persoonlijkheid en zijn vermogen te luisteren naar de meest wildeideeen hebben gezorgd voor een succesfactor in mijn onderzoek. Zijn scherpeinzicht om tot de essentie van het probleem te komen heeft me erg veel geholpenin het oplossen van het probleem. Hij was zelfs zo geduldig dat hij tegen mijngebroken Nederlandse zinnen kon. Met jou werken Anne Johan, was echt heelplezierig. Heel hartelijk bedankt voor alles.

Vele mooie herinneringen heb ik aan de mensen uit de groep van mijnmaster thesis, die ik heb afgerond in IC Design Group. De steun van EricKlumperink, die tijdens die periode mijn eerste supervisor was en de tijdenheeft meegemaakt dat ik net in een nieuw land aankwam waardeer ik zeer.Eric, ik heb nog steeds spijt dat ik niet die twee dagen extra in Hawaı (IMSConference) ben gebleven.

Ook wil ik mijn paranimf Guido Sasse bedanken voor zowel zijn vriend-schap als zijn bijdrage aan alle fijne discussies en brainstorm sessies gedurendeverschillende projecten. Onze discussies waren zeer nuttig; het concept voorde gesepareerde power device is geboren tijdens een diner bij jou thuis.

Ik wil ook de mensen bedanken die ik heb mogen begeleiden: TalithaFaber, Bram Verhoef, Wei Cheng, Egbert Bouwmeester, Gurhan Vural, DavidCalvillo, Ronghui Zhang en Mark van Schie. Jullie bijdrage aan mijn onder-zoek waardeer ik enorm.

Ik wil Henk de Vries bedanken voor de steun tijdens de metingen. Mijnspeciale dank gaat uit naar Gerard de Wienk, die me heeft geholpen om een esdprobleem op te lossen in een van mijn metingen. Jouw hulp was zeer essentieelen wordt zeer gewaardeerd.

Dan wil ik natuurlijk Gerdien en Annemiek bedanken voor alle secretarieleondersteuning. Gerdien, ik moet elke keer weer glimlachen als ik terugdenk

131

aan mijn eerste reis naar een buitenlandse conferentie. Als jij me niet hadhelpen herinneren was ik op de verkeerde dag naar Schiphol gegaan.

Verder wil ik graag mijn collega’s bedanken met wie ik lunch- en brain-storm sessies heb mogen volgen: Stephan Blaakmeer, Firrao Lorenzo, DanielSchinkel, Eisse Mensink, Dlovan Mahrof, Kasra Garakoui, Fabian Houwelin-gen, Salma Hamdi, Muhammed Bolatkale.

De steun van Domine Leenaerts gedurende de comite vergaderingen, in devorm van eerlijke en kritische terugkoppeling en zijn hulp bij de productie vanchips bij NXP zijn ook zeer welkom geweest. Als mijn supervisor tijdens mijnmaster thesis opdracht bij Integrated Transceivers Group van Philips en alscollega bij NXP ben ik dankbaar voor alle ondersteuning en aanmoediging dieik lange tijd van je heb mogen ontvangen.

Ook wil ik mijn dankbaarheid uitspreken naar mijn directe collega’s Markvan der Heijden en Melina Apostolidou. Zonder twijfel kan ik zeggen datde discussies en de werkervaring hebben bijgedragen aan de totstandkomingvan dit proefschrift. Ook wil ik Iouri Volokhine hartelijk bedanken voor hetuitvoeren van metingen met zijn actieve load-pull systeem.

Ik wil mijn waardering uitspreken en Frank van Fliet hierbij bedanken voorhet uitgebreid beoordelen van dit proefschrift.

Tijdens mijn PhD werk heb ik verschillende uitdaging gekregen vanuit mijnfamilie, ieder persoon weer een ander individu. Ik wil ze graag vermelden enbedanken. Het maakt niet uit hoe groot ons gezin is, met 3 broers en 3 zussen,ik houd van ieder van jullie. Mijn dank gaat uit naar mijn moeder en vaderdie veel offers hebben gebracht om te zorgen dat al hun kinderen gelukkigopgroeien en kunnen studeren.

En als laatst en zeker niet als minste, wil ik mijn dankbaarheid uitsprekennaar mijn vriendin Sandy. Jouw steun en begrip hebben me enorm geholpentijdens het schrijven van dit proefschrift.

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Biography

Mustafa Acar was born in Gaziantep, Turkey in 1979. He received his B.Sdegree (honor) from Middle East Technical University and M.S degree (highhonor) in microelectronics from University of Twente in 2001 and 2003 re-spectively. During 2003, he visited Integrated Transceivers Group of Natlab,Philips Research Labs., Eindhoven, The Netherlands to carry out his masterthesis assignment on high speed, low power frequency dividers in submicronCMOS technologies. He worked on his PhD research project on CMOS poweramplifiers at IC Design group of University of Twente between 2003 and 2007.He has been working at RF Advanced Design Group of NXP Semiconductorssince 2007. He has finished his dissertation titled ”Power Amplifiers in CMOSTechnology: A contribution to Power Amplifier Theory and Techniques” inFebruary 2011.

His current research interests are on CMOS drivers and power amplifiersfor RF applications. Mr. Acar is the recipient of the Philips Funding forMicroelectronics Master Program in University of Twente.

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Documents

Power Amplifiers in CMOS Technology