Presented By:

Under the guidance of

Prof. DEBAPRASAD DAS

Department of Electronics and Communication Engineering

TSSOT, Assam University

May 15, 2017

Design Of a CMOS Operational Amplifier Using Cadence

Roll No. Name of Students

31330153 Anamika Chakraborty

31320230 Nandi Vashishth

31360060 Pinku Das

31360110 Nirupom Das

Contents

CMOS Amplifier

Current Mirror

CMOS Differential Amplifier

Single Stage Operational Amplifier

Two Stage Operational Amplifier

Conclusion

References

CMOS AMPLIFIER

Requirement of Amplifiers

o Amplifiers are essential building blocks of both analog and digital systems.

o An amplifier is an electronic device that increases the voltage, current, or power of a

signal.

o The amount of amplification provided by an amplifier is measured by its gain: the

ratio of output to input.

o Amplifiers are needed for variety of reasons including:

-To amplify a weak analog signals for further processing.

-To reduce the effect of noise of next stage.

-To provide a proper logical levels(in digital circuits).

CMOS Amplifier SCHEMATIC DESIGN

This is a table of components for building the CMOS Amplifier schematic.

Library name Cell name Properties/Comments

gpdk180 nmos Model name = nmos1(NM0)

W=2u; L=1u

Analoglib Idc DC current= 5uA

Analoglib VDD, Gnd VDD = 1.8V

CMOS Amplifier Schematic (using CADENCE)

This current 𝐼𝐷 is a function of gate voltage 𝑉𝐺𝑆 and drain

voltage 𝑉𝐷𝑆.. hence, we can write the change in 𝐼𝐷 as

d𝐼𝐷=𝜕𝐼𝐷

𝜕𝑉𝐺𝑆d𝑉𝐺𝑆 +

𝜕𝐼𝐷

𝜕𝑉𝐷𝑆𝑑𝑉𝐷𝑆 (1)

Working of CMOS Amplifier

As the drain current is driven by a current source, it is constant and hence dI𝐷=0.Then Eqn (1) can be written as

𝜕𝐼𝐷

𝜕𝑉𝐺𝑆𝑑𝑉𝐺𝑆 +

𝜕𝐼𝐷𝑆

𝜕𝑉𝐷𝑆d𝑉𝐷𝑆 = 0 (2)

With the application of the input AC signal, the change in gate to source voltage is the input voltage (vin = 𝑑𝑉𝐺𝑆) , and the change

in drain to source voltage is the output voltage (vout = d𝑉𝐷𝑆 ). Hence we can write Eqn (2) as

𝑔𝑚𝑣𝑖𝑛 + 1

𝑟𝑑𝑠𝑣𝑜𝑢𝑡 = 0 (3)

where

Transconductance 𝑔𝑚 = 𝜕𝐼𝐷

𝜕𝑉𝐺𝑆with 𝑉𝐷𝑆 = constant.

Output resistance 𝑟𝑑𝑠 = 𝜕𝑉𝐷𝑆

𝜕𝐼𝐷with 𝑉𝐺𝑆 = constant.

Hence, from Eqn (3) the voltage gain can be written as

𝐴𝑣 = 𝑣𝑜𝑢𝑡

𝑣𝑖𝑛= -𝑔𝑚𝑟𝑑𝑠

Simulation Results

AC Analysis: It is used to sweep the frequency of an AC source. AC analysis is mainly used to obtain the frequency

response of the circuit. In AC- Analysis we determine Phase margin, Gain and GB of the amplifier. Both Gain and Phase margin

are calculated using DC operating point and AC analysis. The values given to implement AC Analysis are:

• Start frequency = 100 Hz

• Stop frequency = 100 GHz

CMOS Amplifier Gain Bandwidth from AC AnalysisCMOS Amplifier Gain from AC Analysis

AC Analysis………………contd.

Parameter Value

Gain 69.37dB

Gain Bandwidth (GB) 33.305 GHz

Phase Margin 134.95 degree

CMOS Amplifier AC Analysis Output

CMOS Amplifier Phase Margin from AC Analysis

Simulation Results…..contd.

Transient Analysis

Transient analysis is used to sweep the time. Transient analysis is used to find out the transient response of the circuit. The values

given to implement Transient Analysis are:

Parameter Value

Input Amplitude(Peak to Peak) 19.946uV

Frequency 1KHz

Start Time 0

Stop Time 5ms

CMOS Amplifier Transient Analysis Output Amplitude (Peak to Peak) = 58.6856mV

Gain = 2.942K

Simulation Results……….contd.

DC Analysis

DC analysis is used to sweep the voltage value of DC source or a parameter value. DC analysis is

important to know the required power supply and its limits, the current consumption and to be

sure that all the devices in the circuit are working in the safe region without exceeding their

normal ratings.

• Power Dissipation = 9 uW

Current Mirror

• A current mirror is a circuit designed to copy a current through one active device by controlling the current in

another active device of a circuit, keeping the output current constant regardless of loading.

• The current mirror circuit copies current from a reference.

• It finds application in analog circuits such as differential amplifiers, digital-to-analog (D/A) converters, etc.

• A current mirror has very high internal resistance and can act as active current source.

• Here, currents in the two transistors are mirrored, hence the name current mirror.

Current Mirror Working

MOS current mirror

In this circuit, M1 is always operating in the saturation region as its

drain and gate terminals are shorted. As M1 and M2 have a common

gate, their gate-source VDD voltages are identical, and thus the current

through M1 and M2 must be equal if their dimensions are identical. The

currents in two transistors are mirrored, hence the name current mirror.

M1 and M2 are fabricated in the same integrated circuit under identical

process conditions, so their threshold voltage must be same, i.e., Vt1 =

Vt2. Thus, we can write

𝐼𝑜𝑢𝑡𝐼𝑟𝑒𝑓

= 𝑊2 𝐿2 𝑊1 𝐿1

Hence, ratio of the output and reference current is a function of the

aspect ratios of the devices which can be controlled by the designer.

CMOS Differential Amplifier

Differential amplifiers are used to amplify analog as well as digital signals, and can

be used in various implementations to provide an output from the amplifier in

response to differential inputs.

The differential amplifier is one of the most versatile circuits used in analog circuit

design.

Why it is used?

Better common-mode noise rejection

Reduced harmonic distortion

Increased output voltage swing.

CMOS Differential Amplifier Schematic Design

Library name Cell name Properties/Comments

gpdk180 Nmos Model Name = nmos1 (NM0, NM1) ;

W= 3u ; L= 1u

gpdk180 Nmos Model Name =nmos1 (NM2, NM3) ;

W= 4.5u ; L= 1u

gpdk180 Pmos Model Name =pmos1 (PM0, PM1); W=

15u ; L= 1u

analoglib Idc DC current = 20u

analoglib VDD, Gnd, VSS VDD = 1.8V, VSS = -1.8V

CMOS Differential Amplifier Schematic building components

Differential Amplifier Schematic using CADENCE

Simulation Results

AC Analysis

The values given to implement AC Analysis are:

• Start frequency = 1Hz

• Stop frequency = 100 GHz

CMOS Differential Amplifier AC Analysis

Simulation Results…………. contd

CMRR: The main goal of the differential amplifier is to amplify the differential mode input signal. Hence, the differential

amplifier is characterized by a parameter called common mode rejection ratio (CMRR), which is defined by

CMRR= 20𝑙𝑜𝑔𝐴𝐷

𝐴𝐶in dB

A good differential amplifier must have a large differential mode

voltage gain and small common mode voltage gain,

and must have high CMRR.

Figure: Differential Configuration to determine Differential

mode gain (AD)

CMRR……………………contd.

Figure: Common Mode Gain

Figure: Common Mode Configuration to

determine common mode gain (AC)

CMRR…………………………..contd.

AD (dB) = 29.98dB

AC (dB) = -31.57dB

CMRR = AD - (-AC) in dB = 61.55dB

Parameter Value

Gain 29.98 dB

Gain Bandwidth (GB) 742.43 MHz

CMRR 61.55 dB

CMOS Differential Amplifier AC Analysis Output

Simulation Results………..contd.

Transient Analysis

1. Non-inverting differential amplifier (V1>V2)

Parameter Value

V1(Peak to Peak) 40uV

V2(Peak to Peak) 20uV

Frequency 1KHz

Start Time 0

Stop Time 5ms

Figure: CMOS Differential Amplifier Transient Analysis

(non-inverting configuration)

Output Amplitude (Peak to Peak) = 631.42uV

Gain = 31.55

Simulation Results………contd.

2. Inverting differential amplifier (V1>V2)

Parameter Value

V1(Peak to Peak) 20uV

V2(Peak to Peak) 40uV

Frequency 1KHz

Start Time 0

Stop Time 5ms

CMOS Differential Amplifier Transient Analysis (inverting

configuration)

Output Amplitude (Peak to Peak) = 631.42uV

Gain = 31.55

DC Analysis

Current (I) = 44.64uA

VDD = 1.8V

Power Dissipation = 80.35uW

SINGLE STAGE OPERATIONAL AMPLIFIERS

Performance Parameters

Let us first explain the design parameters that are used to design a CMOS OPAMP circuit.

• Gain The open-loop gain of the OPAMP must be very high, so that when it is used in negative feedback, the closed-loopgain must be independent of open-loop gain.

• Small signal bandwidth (BW) The open-loop gain decreases as the frequency of the operation increases. Hence, the designmust consider the BW of the OPAMP.

• Large signal bandwidth The OPAMP is used in large signal transients. Hence, it must respond to the transient signals thatchange very fast in time.

• Slew rate The OPAMP must have a high slew rate.

• Linearity The OPAMP characteristics must be linear.

• Noise and offset The noise and offset must be insignificant.

• Power supply rejection The power supply rejection must be high.

• Input Common Mode Range (ICMR) For an op amp, ICMR is the range of common mode signal for which the amplifier'soperation remains linear.

• Common Mode Rejection Ratio (CMRR) Common-mode rejection ratio, CMRR, is defined as the ratio of the differentialvoltage amplification to the common-mode voltage amplification. Ideally this ratio would be infinite with common modevoltages being totally rejected.

Single stage Op amp Schematic Design

To design single stage op amp schematic following boundary conditions are required:

1. Process specifications (VT, K’, etc.)

2. Supply voltage and range

3. Supply current and range

4. Operating temperature and range

Sl. No. Specifications Value

1. Technology gpdk180

2. Power Supply (VDD) 1.8 V

3. Load Capacitance (CL) 10 pF

4. Gain >= 40 dB

5. Gain Bandwidth >= 5 MHz

6. Slew rate (SR) 5 V/usec

7. ICMR (+) 1.6 V

8. ICMR (-) 0.8 V

9. Power Dissipation <= 2mW

Design Specifications

Model or Device

Parameters

Value

Vtp -0.46 V

Vtn 0.49 V

K’p 63 uA/V2

K’n 325 uA/V2

Required Device Parameters for

designing single stage op amp

Single stage opamp design procedure

Figure: Single stage Op amp

1. Pick 𝐼𝑜 to satisfy the slew rate knowing 𝐶𝐿 and minimum

power dissipation

2. Design W1/L1 (W2/L2) to satisfy

the gain

3. Design W3/L3 (W4/L4) to satisfy

the upper ICMR

4. Design W5/L5 to satisfy the

lower ICMR

– Iterate where necessary

Design Procedure………….contd.

Step1:- To meet the slew rate, and maximum Power Dissipation

I5 = SR.CL

𝑃𝑑𝑖𝑠𝑠 = 𝑉𝐷𝐷 + 𝑉𝑆𝑆 . 𝐼5

Step2:- Design for M1 and M2 to achieve desired GB.

𝑔𝑚1,2 = 𝐺𝐵 × 𝐶𝐿

(𝑊

𝐿)1,2=

𝑔𝑚2

2𝐼𝐷𝐾𝑛′

Step3:- Design for M3 and M4 from the maximum input voltage [ICMR(+)] specification.

(𝑊

𝐿)3,4=

2𝐼3𝐾𝑝′ {𝑉𝐷𝐷 − 𝐼𝐶𝑀𝑅 + − 𝑉𝑇3𝑚𝑎𝑥 + 𝑉𝑇1𝑚𝑖𝑛}

2

Design Procedure……………contd.

Step4:- Design for M5 and M6 from the minimum input voltage [ICMR(-)]. First we have calculated VDS5(sat) and then we have find M5 and M6.

𝑉𝐷𝑆5(𝑠𝑎𝑡) = 𝐼𝐶𝑀𝑅 − −𝐼5𝛽1

12

+ 𝑉𝑇1𝑚𝑎𝑥

(𝑊

𝐿)5,6=

2𝐼5𝐾𝑛′ [𝑉𝐷𝑆𝑠𝑎𝑡]

2

MOSFETS (W/L)

M1 7

M2 7

M3 15

M4 15

M5 13.67

M6 13.67

Aspect Ratios for different transistors

Single Stage opamp Schematic

Simulation Results

AC Analysis

AC analysis is used to sweep the frequency of an AC source. AC analysis is mainly used to obtain the frequency

response of the circuit. In AC- Analysis we determine Phase margin, Gain GB, CMRR and PSRR of the amplifier.

The values to implement AC Analysis are:

Start Frequency = 1 Hz

Stop Frequecny = 10 MHz

Figure: AC analysis showing Gain and

Gain Bandwidth of Single stage op amp

AC Analysis…………………..contd.

Figure: Phase Margin of single stage op amp

Phase Margin=180-90.5

= 89.5 degree

AC Analysis……………..contd.

• CMRR = 20log10𝐴𝐷

𝐴𝐶, where AD is the differential mode gain and AC is the common mode gain of single stage op amp.

Differential mode configuration of single

stage op amp

Differential mode gain of single stage op amp

CMRR………………………….contd.

Common mode configuration of single

stage op amp

Common mode gain of single stage op amp

Therefore, CMRR = AD - (-AC) in dB

AD = 40.8002 dB and AC = -47.3012 dB

So, CMRR = 88.10 dB

AC Analysis…………………..contd.

Power Supply Rejection Ratio(PSRR)- the ability of a circuit to eliminate any ripple in the circuit power supplies.

PSRR = 20log10 𝐴𝑉,𝐷𝐼𝐹𝐹

𝐴𝑉,𝑃𝑆

PSRR simulation result

Therefore, PSRR = AV, DIFF – (-AV, PS)

AV, DIFF = 40.8002 dB and AV, PS = -44.325 dB

So, PSRR = 85.152 dB

PSRR test bench

AC Analysis……………………contd.

Parameter Value

Gain 40.8 dB

Gain Bandwidth 4.69 MHz

Phase Margin 89.5 degree

CMRR 88.10 dB

PSRR 85.152 dB

AC Analysis Result

Transient Analysis

The values given to implement Transient Analysis are:

Parameter Value

Input Amplitude(Peak to Peak) 19.9463 uV

Common Mode Voltage (VCM) 1.6 V

Frequency 1 KHz

Start Time 0

Stop Time 5 ms

Single stage op amp as inverting amplifier

Transient Analysis………………contd.

Output Amplitude (Peak to Peak) = 2.18 mV

Gain = 109.436

Single stage op amp wave (non-inverting amplifier)

Single stage op amp as non-

inverting amplifier

Transient Analysis………………contd.

Slew Rate : Slew rate, SR, is the rate of change in the output voltage caused by a step input.

Slew rate (SR) = 𝑉2−𝑉1𝑇2−𝑇1

Parameter Value

Rise Time 1 ns

Fall Time 1 ns

Pulse Width 384.61 us

Pulse Period 769.23 us

Parameters of Input Pulse to

calculate Slew Rate

Slew Rate Test bench

Simulation Results…………….contd.

Slew rate result

Using simulator calculator the value of Slew rate = 5.32 V/us

DC Analysis

DC analysis is done to check whether all the

transistors are operating in saturation region and

to calculate the value of Power dissipation.

Current (I) = 103.572uA

VDD = 1.8V

Power Dissipated = 186.43 uW

Single Stage op amp Layout

A layout of an integrated circuit is the footprint of

the entire circuit consisting of millions of

polygons. Each of the polygons represents some

physical component of the devices or circuits.

Connection Contact type

For Metal1- Poly Connection Metal1-Poly

For Metal1- Psubstrate

Connection

Metal1-Psub

For Metal1- Nwell Connection Metal1-Nwell

Different Via to be used

Single Stage op amp Layout…..contd.

RCX Run

LVS Check

DRC Check

Two Stage Operational Amplifier

The circuit consists of an input differential trans-

conductance stage that forms the input of the op-amp

followed by common-source second stage.

Input differential amplifier provides very high input

impedance, a large CMRR and PSRR, a low offset

voltage, low noise and high gain.

The second stage performs Level shifting, added gain and

differential to single ended converter.

A general two stage CMOS Op-amp Bias circuit is provided to establish the operating point for

each transistor in its quiescent stage.

Compensation is required to achieve stable closed loop

performance.

Miller Compensation

Each stage of the OPAMP is considered as a gain stage with a single-

pole frequency response.

.Notice that the phase of the output of each stage will undergo a phase

change of 90 around its pole frequency. Hence, the OPAMP must be

compensated.

The lower frequency pole is brought to a low enough frequency, so that

the gain diminishes to below 1 by the time the second pole is reached.

One way of doing this is to use a Miller capacitor.

Miller Compensation In this technique, a capacitor (CC) is connected

between the input differential stage and the output stage.

Two Stage opamp Schematic Design

Sl.

No.

Specifications Value

1. Technology gpdk180

2. Power Supply (VDD) 1.8 V

3. Load Capacitance (CL) 2 pF

4. Gain 60 dB

5. Phase Margin >=45 degree

6. Gain Bandwidth 30 MHz

7. Slew rate (SR) >=42 V/usec

8. ICMR (+) 1.6 V

9. ICMR (-) 0.8 V

10. Power Dissipation <= 300uW

Required Specifications for designing two stage op amp

Model or Device

Parameters

Value

Vtp -0.46 V

Vtn 0.49 V

K’p 66 uA/V2

K’n 330 uA/V2

Required Device Parameters for designing

two stage op amp

Two Stage opamp Design Procedure

Before actually beginning with the designing part, let us discuss some important relationships describing performance of an op-amp.

• Slew rate, SR = 𝐼5

𝐶𝑐

• First-stage gain, 𝐴𝑣1 = −𝑔𝑚1

𝑔𝑑𝑠2+𝑔𝑑𝑠4

• Second-stage gain, 𝐴𝑣2 = −𝑔𝑚6

𝑔𝑑𝑠6+𝑔𝑑𝑠7

• Gain bandwidth, 𝐺𝐵 =𝑔𝑚1

𝐶𝑐

• Output pole, 𝑝𝑧 = −𝑔𝑚1

𝐶𝐿

• RHP zero, 𝑧1 =𝑔𝑚6

𝐶𝑐

• ICMR(+)= 𝑉𝐷𝐷 −𝐼5

𝛽3− 𝑉𝑇3𝑚𝑎𝑥 +𝑉𝑇1𝑚𝑖𝑛

• ICMR(-) = 𝑉𝑆𝑆 +𝐼3

𝛽1+ 𝑉𝑇1𝑚𝑎𝑥 + 𝑉𝐷𝑆5𝑠𝑎𝑡

• Saturation voltage, 𝑉𝐷𝑆𝑠𝑎𝑡 =2𝐼𝐷𝑆

𝛽

Design Procedure…………..contd.

1. From the desired phase margin, the minimum value for Cc is chosen. We have used the following relationship. This assumes

that z ≥ 10GB.

For 450 phase margin CC ≥ 0.122CL

For 600 phase margin CC ≥ 0.22CL

2. Finding of bias current from the slew rate and compensation capacitor

I5 = SR .Cc

3. Design for transistor M1 and M2 to achieve desired GB.

𝑔𝑚1 = 𝐺𝐵 × 𝐶𝑐

𝑊

𝐿1,2=

𝑔𝑚12

𝐾𝑛′ 𝐼5

4. Design for M3 and M4 from the maximum input voltage [ICMR(+)] specification.𝑊

𝐿 3,4=

2𝐼3𝐾𝑝′ 𝑉𝐷𝐷 − 𝐼𝐶𝑀𝑅 + − 𝑉𝑇3𝑚𝑎𝑥 + 𝑉𝑇1𝑚𝑖𝑛

2

Design Procedure………………contd.

5. Design for M5 from the minimum input voltage [ICMR(-)]. First we have calculated VDS5(sat) and then we have find M5.

𝑉𝐷𝑆5(𝑠𝑎𝑡) = 𝐼𝐶𝑀𝑅 − − 𝑉𝑆𝑆 −𝐼5𝛽1

12

− 𝑉𝑇1𝑚𝑎𝑥

(𝑊

𝐿)5,6=

2𝐼5𝐾𝑛′ [𝑉𝐷𝑆𝑠𝑎𝑡]

2

6. Find M6 and I6 by letting the second pole (p2) be equal to 2.2 times GB.

𝑔𝑚6 = 2.2𝑔𝑚2

𝐶𝐿𝐶𝐶

Let VGS4 = VGS6, which gives 𝑀6 = 𝑀4𝑔𝑚6

𝑔𝑚4

Knowing 𝑔𝑚6 and M6 allows us to solve for I6 as 𝐼6 =𝑔𝑚62

2𝐾𝑝′𝑀6

7. Calculating of M7 from the M5 , 𝐼6 and 𝐼5

𝑀7 =𝐼5

𝐼6M6

Two Stage opamp Schematic

MOSFETS (W/L)

M1 6

M2 6

M3 8

M4 8

M5 124.56

M6 31.14

M7 4

M8 4Aspect Ratios for different transistors

Simulation Results

AC Analysis

AC analysis is mainly used to obtain the frequency response of the circuit. In AC Analysis we determine Phase margin, Gain GB,

CMRR and PSRR of the amplifier.

The values to implement AC Analysis are:

Start Frequency = 1 Hz

Stop Frequency = 100 MHz

AC analysis representing Gain and Gain Bandwidth of two stage op amp

AC Analysis…………….contd.

Gain Margin of two stage op amp

Phase Margin of two stage op amp

Phase Margin = 180-132.747

= 47.253 degree Gain Margin = 0 – (-16.8)

= 16.8 dB

AC Analysis………………….contd.

CMRR = 20log10𝐴𝐷

𝐴𝐶, where AD is the differential mode gain and AC is the common mode gain of two stage op amp.

Differential mode configuration of two

stage op amp

Differential mode gain of two stage op amp

CMRR…………………………contd.

Therefore, CMRR = AD - (-AC) in dB

AD = 59.8456 dB and AC = -36.7967 dB

So, CMRR = 96.6423 dB

Common mode gain of two stage op ampCommon mode configuration of two stage

op amp

AC Analysis……………….contd.

• PSRR = ∆𝑉𝐷𝐷∆𝑉𝑂𝑈𝑇

𝐴𝑉 =

𝑉𝑂𝑉𝐼𝑁

𝑉𝐷𝐷=0

𝑉𝑂

𝑉𝐷𝐷𝑉𝐼𝑁=0

= 20log10 𝐴𝑉,𝐷𝐼𝐹𝐹

𝐴𝑉,𝑃𝑆

PSRR test bench

PSRR simulation result

Therefore, PSRR = AV, DIFF – (-AV, PS)

AV, DIFF = 59.8456 dB and AV, PS = -93.4176 dB

So, PSRR = 153.2632 dB

AC Analysis……………………………contd.

Parameter Value

Gain 59.8456 dB

Gain Bandwidth 30.29 MHz

Phase Margin 47.253 degree

Gain Margin 16.809 dB

CMRR 96.64 dB

PSRR 153.26 dB

AC Analysis Result

Simulation Result

Transient Analysis

The values given to implement Transient Analysis are:

Parameter Value

Input Amplitude(Peak to

Peak)

19.9463 uV

Common Mode Voltage

(VCM)

1.6 V

Frequency 1 KHz

Start Time 0

Stop Time 5 ms

Two stage op amp as inverting amplifier

Transient Analysis…………….contd.

Two stage op amp as non-inverting amplifier Two stage op amp wave (non-inverting amplifier)

Output Amplitude (Peak to Peak) = 20.9567mV

Gain = 1.05K

Transient Analysis…………..contd.Slew Rate: Slew rate, SR, is the rate of change in the output voltage caused by a step input.

Slew rate (SR) = 𝑉2−𝑉1𝑇2−𝑇1

Parameter Value

Rise Time 1 ns

Fall Time 1 ns

Pulse Width 384.61 us

Pulse Period 769.23 us

Parameters of Input Pulse to calculate Slew

Rate

Slew Rate Test bench

Simulation Results……………contd.

Using simulator calculator the value of Slew rate = 42.5 V/us

Slew rate result

DC Analysis

Current (I) = 133.039uA

VDD = 1.8V

Power Dissipated = 239.47 uW

Layout of Two Stage op amp

Connection Contact type

For Metal1- Poly

Connection

Metal1-Poly

For Metal1- Psubstrate

Connection

Metal1-Psub

For Metal1- Nwell

Connection

Metal1-Nwell

Different Via used

Layout of Two Stage opamp………….contd.

RCX run

LVS CheckDRC Check

Performance Comparison of single stage and two stage opamp

Parameter Single Stage Op amp Two Stage Op amp

Gain 40.8 dB 59.85 dB

Gain Bandwidth 4.69 MHz 30.3 MHz

Phase Margin 89.5 degree 47.253 degree

CMRR 88.10 dB 96.64 dB

PSRR 85.13 dB 153.26 dB

Slew Rate 5.32 V/us 42.5 V/us

Power Dissipation 186.43 uW 239.47 uW

APPLICATIONS OF OPAMP

• It is used in summer, subtractor circuits

• It is used in integrator, differentiator circuits.

• It is used for various filter design like low pass, high pass, butterworth etc

• It is used in Instrumentation amplifiers.

• It is used in voltage-to-current converter circuit.

Conclusion

• The main task of this project is to design the single stage and two stage CMOS operational

amplifier using 180nm technology in Cadence Tools. Firstly we studied the basic characteristics of

nMOS and pMOS transistors, their operating region. We designed basic analog building blocks like

MOSFET switch, MOSFET diode, and current mirror. Then we designed CMOS amplifier and

common source amplifier. Finally, with the help of these building blocks we designed single stage

and two stage CMOS operational amplifier. The design consists of two parts i.e. the schematic

design and the layout design. Simulation on the operational amplifier circuit and its layout is done

to analyze the results of design circuit and its layout. The notable performance areas were the gain,

gain bandwidth, slew rate, CMRR and PSRR.

References

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.

[2] P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition,

2001.

[3] R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.

[4]R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International

Edition, 1990.

[5]D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.

[6]Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999.

[7]K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.

[8] Debaprasad Das, VLSI Design, 2nd edition, , OXFORD University Press, 2011

[9] Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", JSSC, vol. 34, no. 3, March 1999, p. 268.

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