PROJECT REPORT

ON

CCII based Pipelined ADC

Submitted for partial fulfillment of award of

BACHELOR OF TECHNOLOGY

Degree

In

Electronics and Communication Engineering

By

VIDHI GOSWAMI (0061352807)

NEHA (0111352807)

GARIMA PRABHAKAR (0151352807)

KRITIKA CHOUDHARY (0121352807)

Under the guidance of

Mrs. Veepsa Bhatia

INDIRA GANDHI INSTITUTE OF TECHNOLOGY, DELHI, INDIA

JANUARY-MAY, 2011

1

CERTIFICATECertified that Vidhi (0061352807), Neha (0111352807), Garima (0151352807), and Kritika (0121352807) have carried out the simulation and implementation work presented in this thesis entitled “CCII based pipelined ADC” for the award of Bachelor of Technology from Indira Gandhi Institute Of Technology, Delhi, India under my supervision and guidance. The thesis embodies result of original work and studies carried out by students themselves and the contents of the thesis do not form the basis for the award of any other degree to the candidate or to anybody else.

To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other university/institute for the award of any Degree or Diploma.

Mrs. Veepsa Bhatia(SUPERVISOR)

Designation: Asst. ProfessorDepartment: Electronics & Communication

Indira Gandhi Institute of Technology

Date:

2

ACKNOWLEDGEMENT

We would like to take this opportunity to thank everybody who has contributed in the successful completion of our project. First and foremost, we would like to express our deep sense of respect and gratitude towards our advisor and guide, Mrs. Veepsa Bhatia for her invaluable guidance and encouragement. This project would not have been possible without her personal attention. We want to thank her for giving us the opportunity to work under her. We consider it our good fortune to have got an opportunity to work with such a wonderful person.

We would also like to thank the head of our electronics and communication department, Dr. Shail Bala Jain for motivating and guiding us.

VIDHI GOSWAMI (0061352807)

NEHA (0111352807)

GARIMA PRABHAKAR (0151352807)

KRITIKA CHOUDHARY (0121352807)

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INDEX

S.No. Contents Page No.1. Certificate 2

2. Acknowledgement 33. Chapter-1

Introduction and working6

3.1 Introduction 7

3.2 Architecure of pipelined ADC 8

4. Chapter-2Orcad (p-spice)

9

5. Chapter-3Current conveyors CCII

13

5.1 Introduction 145.2 CC description 155.3 CC generations 155.4 CMOS implementation 175.5 Advantages of CCs 175.6 Applications of CCs 185.7 Coding for CCII 195.8 Simulation output 23

6. Chapter-4Sample and Hold circuit (S/H)

24

6.1 General explanation 256.2 Working 256.3 CMOS implementation using CCII 266.4 Coding for S/H 286.5 Simulation output 32

7. Chapter-5Multiplying DAC (MDAC)

33

7.1 Introduction 347.2 Explanation 347.3 CMOS implementation using CCII 35

7.4 Comparison of settling time for the MDAC 36

7.5 Coding for MDAC 37

7.6 Simulation output 418. Chapter-6

Comparator42

4

8.1 Introduction 438.2 CMOS implementation 438.3 Coding for comparator 458.4 Simulation output 49

9. Chapter-7Clock generator and delay circuit

50

9.1 Introduction 509.2 Implementation 519.3 VHDL code 52

10. Conclusion 5311. References 54

List of FiguresFigure 1 1.5-bit/stage pipelined ADC architecture 8Figure 2 Current conveyor general block diagram 15Figure 3 The CMOS CCII circuit 17Figure 4 Simulation output for CCII 23Figure 5 Typical sample and hold circuit 25Figure 6 CCII based S/H 26Figure 7 Simulation output for S/H 32Figure 8 CCII based MDAC circuit 35Figure 9 Comparison of settling time for the MDAC 36Figure 10 Simulation output for MDAC 41Figure 11 CMOS based comparator circuit 43Figure 12 Simulation output for comparator 49Figure 13 Non-overlap clock generator 51Figure 14 Overall delay circuit 52

5

Chapter-1Introduction and Working

Introduction

6

In this project, we have implemented a new CCII based pipelined ADC which is proposed by Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen (Department of Electronic Engineering, National Taipei University of Technology ,Taipei, Taiwan).

Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCIIs instead of operational amplifiers (OAs). Simulation results show that the proposed CCII-based pipelined ADC can work at 10MHz with an 8-bit resolution.

It has been proven that the digital signal processing (DSP) shows better accuracy than analog signal processing. The ADC is the main link between the analog input and DSP part. The ADC based on pipelined architectures can offer both high resolution and high speed instead of large size and power consumption which make the architectures well suited for many applications. The switched-capacitor (SC) circuits are usually used in pipelined ADCs not only they can construct the S/H circuit but also for the MDAC. The SC circuit is usually made by OAs, for this reason, the efficacy of the OA always determines the SC circuit performance. Compared with traditional OAs, CCIIs have higher accuracy and wider frequency ranges, hence the CCII-based circuits are popularly used in many applications. But no paper discussed the CCII-based ADC. This paper presents a new CCII-based pipelined ADC instead of using traditional OA-based SC techniques which can employ the advantages of CCII. The digital error correction technique is also applied to increase the performance of our pipelined ADC.

Technology used:Here, we have used 0.18 μm CMOS technology.

Simulation tool used:ORCAD 9.1/p-spice

Architecture of Pipelined ADC

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The ADC is realized with the 1.5-bit/stage pipelined architecture where the 0.5-bit redundancy in each stage is used for digital correction to relax the requirement for the comparators. The block diagram of the 8-bit pipelined ADC is shown in Fig. . It is composed of one S/H stage and eight sub-ADC stages. Each pipelined stage performs a low resolution sub-ADC with 1.5-bit output and a MDAC.

The operation of the pipelined ADC consists of two phases. The even stages and odd stages operate in opposite, thus the conversion of a sample traverses two stages in a clock cycle. In the first phase, the S/H stage samples the input signal while the MDAC of even stages sample the output of odd stages and the sub-ADC dose the analog-to-digital conversion. In the second phase, the MDAC even stages generate and amplify the residue yielding the input signals for the even stages.

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Fig.1: 1.5-bit/stage pipelined ADC architecture

Chapter-2ORCAD(p-spice)

Introduction:

9

SPICE is a powerful general purpose analog and mixed-mode circuit simulator that is used to verify circuit designs and to predict the circuit behavior. This is of particular importance for integrated circuits. It was for this reason that SPICE was originally developed at the Electronics Research Laboratory of the University of California, Berkeley (1975), as its name implies:

Simulation Program for Integrated Circuits Emphasis.

PSpice is a PC version of SPICE (which is currently available from OrCAD Corp. of Cadence Design Systems, Inc.). A student version (with limited capabilities) comes with various textbooks. The OrCAD student edition is called PSpice AD Lite. Information about Pspice AD is available from the OrCAD website: http://www.orcad.com/pspicead.aspx

The PSpice Light version has the following limitations:

circuits have a maximum of 64 nodes, 10 transistors and 2 operational amplifiers.

SPICE can do several types of circuit analyses. Here are the most important ones:

• Non-linear DC analysis: calculates the DC transfer curve.

• Non-linear transient and Fourier analysis: calculates the voltage and current as a function of time when a large signal is applied; Fourier analysis gives the frequency spectrum.

• Linear AC Analysis: calculates the output as a function of frequency. A bode plot is generated.

• Noise analysis

• Parametric analysis

• Monte Carlo Analysis

In addition, PSpice has analog and digital libraries of standard components (such as NAND, NOR, flip-flops, MUXes, FPGA, PLDs and many more digital components, ). This makes it a useful tool for a wide range of analog and digital applications.

All analyses can be done at different temperatures. The default temperature is 300K.

The circuit can contain the following components:

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• Independent and dependent voltage and current sources

• Resistors

• Capacitors

• Inductors

• Mutual inductors

• Transmission lines

• Operational amplifiers

• Switches

• Diodes

• Bipolar transistors

• MOS transistors

• JFET

• MESFET

• Digital gates

• and other components.

PSpice is a SPICE analog circuit and digital logic simulation software that runs on personal computers, hence the first letter "P" in its name. It was developed by MicroSim and is used in electronic design automation. MicroSim was bought by OrCAD which was subsequently purchased by Cadence Design Systems. The name is an acronym for Personal Simulation Program with Integrated Circuit Emphasis. Today it has evolved into an analog mixed signal simulator.

PSpice was the first version of UC Berkeley SPICE available on a PC, having been released in January 1984 to run on the original IBM PC. This initial version ran from two 360 KB floppy disks and later included a waveform viewer and analyser program called Probe. Subsequent versions improved in performance and moved to DEC/VAX minicomputers, Sun workstations, the Apple Macintosh, and the Microsoft Windows platform.

PSpice, now developed towards more complex industry requirements, is integrated in the complete systems design flow from OrCAD and Cadence

11

Allegro. It also supports many additional features, which were not available in the original Berkeley code like Advanced Analysis with automatic optimization of a circuit, encryption, a Model Editor, support of parametrized models, has several internal solvers, auto-convergence and checkpoint restart, magnetic part editor and Tabrizi core model for non-linear cores.

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Chapter-3Second generation Current Conveyor

(CCII)

Introduction

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A current conveyor is a four (possibly five) terminal device which when arranged with other electronic elements in specific circuit configurations can perform many useful analog signal processing functions such as filter , oscillator and impedance function synthesis , etc. In recent years, current conveyor based current-mode circuits get lots of attention in analog signal processing applications. Current conveyors (CCs) are being increasingly employed to replace operational amplifiers in almost all analog signal-processing applications because their current mode architectures are particularly suitable for today’s low-voltage high frequency applications. CCs’ unique architectures can easily transform into other current mode structures.CCs’ advanced circuit and device applications are presented in this tutorial article. All these structures can be implemented in CMOS.

Analog VLSI can address almost all real world problems and finds exciting new information processing applications in variety of areas such as integrated sensors, image processing, speech recognition, hand writing recognition etc . All conventional analog circuits viz., op amps, voltage to frequency converters, voltage comparators etc. are voltage mode circuits (VMCs), which suffer from low bandwidths arising due to the stray and circuit capacitances and are not suitable in high frequency applications. The need for low-voltage low-power circuits is immense in portable electronic equipments like laptop computers, pace makers, cellphones etc. VMCs are rarely used in low-voltage circuits as the minimum bias voltages depend on the threshold voltages of the MOSFETs. However, in current mode circuits (CMCs), the currents decide the circuit operation and enable the design of the systems that can operate over wide dynamic range. The low end of the circuit operating range is limited by the leakage currents and noise floor level while the high end is decided by degradation of the trans-conductance per unit current available above the threshold voltage. These circuits can give large bandwidths and are suitable for low-voltage applications. Current feedback amplifiers (CFAs), Operational floating Conveyors (OFCs) Current Conveyors (CCs) etc. are the popular CMC structures and most widely used structure among them is the CCII structure.

CC descripition

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A CC is a three or more port (X, Y , Z) network. The commonly used block representation of a CC is shown in Figure 1,

whose input-output relationship is given by

where A, B, C assume a value either 1, 0 or −1 and RX is the intrinsic resistance offered by the port X to the input currents. For an ideal CC, VX = VY and the input resistance (RX ) at port X is zero .

CC GenerationsThere are many generations of current conveyors. Here, we will explain only two generations, i.e. 1st and 2nd.

First generation current conveyors:

It is a three port device. The operation of this device is such that if a voltage is applied to input terminal Y, an equal potential will appear on input X. Similarly, an input current being forced into X, will result in an equal

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Fig 2. Current conveyor general block diagram

amount of current in terminal Y. As well , the current I will be conveyed to output terminal Z.The characteristic equation is given by:

Second generation current conveyors:To increase the versatility of the current conveyor, a second version in which no current flows in terminal Y, was introduced. This version has proven to be more useful than CC1. The characteristic equation is given by:

The terminal Y exhibit an infinite input impedence. The voltage at X follows that applied to Y, thus X exhibit a zero input impedence.

CMOS implementation of CCII:

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The CMOS CCII circuit is designed as shown in Fig. and the supply voltage is 3.3V. Transistors M1~M7 are composed as a voltage buffer and the current through M8 and M9 is as same as that through M6 and M7. M10 and Cc are used for frequency compensation and Vb is the bias voltage. Among all the other realizations, this realization of CCII exhibits good performance in terms of noise, linearity and voltage tracking error between terminals X and Y which can achieve the requirement in the S/H and MDAC design.

Advantages of using CCII instead of Operational amplifiers

1. The proposed CCs are suitable for high frequency LV analog and mixed signal systems.

2. CCs are capable of operating at low voltage of ±1.0 V and consume 0.6 mW power.

3. These CCs have bandwidths of 100 MHz with input current range of −500 to 500 μA when operated in class AB mode. However, in class A CCII has the bandwidth of about 200 MHz.

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Fig.3: The CMOS CCII circuit

4. The structure can be modified to function as CCI, CCII or CCIII. This flexibility can be utilized in future current mode circuits.

Applications of circuits using CCs

1. A current conveyor when arranged with other electronic elements in specific circuit configurations can perform many useful analog signal processing functions such as filter , oscillator and impedance function synthesis , etc.

2. In generation of mathematical functions such as square rooting and current squaring i.e. even for complicated mathematical computing.

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Coding for CCII:

*rise time = 6.58*10-11 fal time = 1.04*10-11.MODEL NMOS NMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3750766+K1 = 0.5842025 K2 = 1.245202E-3 K3 = 1E-3+K3B = 0.0295587 W0 = 1E-7 NLX = 1.597846E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.3022984 DVT1 = 0.4021873 DVT2 = 7.631374E-3+U0 = 296.8451012 UA = -1.179955E-9 UB = 2.32616E-18+UC = 7.593301E-11 VSAT = 1.747147E5 A0 = 2+AGS = 0.452647 B0 = 5.506962E-8 B1 = 2.640458E-6+KETA = -6.860244E-3 A1 = 7.885522E-4 A2 = 0.3119338+RDSW = 105 PRWG = 0.4826 PRWB = -0.2+WR = 1 WINT = 4.410779E-9 LINT = 2.045919E-8+XL = 0 XW = -1E-8 DWG = -2.610453E-9+DWB = -4.344942E-9 VOFF = -0.0948017 NFACTOR = 2.1860065+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 1.991317E-3 ETAB = 6.028975E-5+DSUB = 0.0217897 PCLM = 1.7062594 PDIBLC1 = 0.2320546+PDIBLC2 = 1.670588E-3 PDIBLCB = -0.1 DROUT = 0.8388608+PSCBE1 = 1.904263E10 PSCBE2 = 1.546939E-8 PVAG = 0+DELTA = 0.01 RSH = 7.1 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 6.7E-10 CGSO = 6.7E-10 CGBO = 1E-12+CJ = 9.550345E-4 PB = 0.8 MJ = 0.3762949+CJSW = 2.083251E-10 PBSW = 0.8 MJSW = 0.1269477+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1269477+CF = 0 PVTH0 = -2.369258E-3 PRDSW = -1.2091688

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+PK2 = 1.845281E-3 WKETA = -2.040084E-3 LKETA = -1.266704E-3+PU0 = 1.0932981 PUA = -2.56934E-11 PUB = 0+PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.350276E-3 )*.MODEL PMOS PMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3936726+K1 = 0.5750728 K2 = 0.0235926 K3 = 0.1590089+K3B = 4.2687016 W0 = 1E-6 NLX = 1.033999E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.5560978 DVT1 = 0.2490116 DVT2 = 0.1+U0 = 112.5106786 UA = 1.45072E-9 UB = 1.195045E-21+UC = -1E-10 VSAT = 1.168535E5 A0 = 1.7211984+AGS = 0.3806925 B0 = 4.296252E-7 B1 = 1.288698E-6+KETA = 0.0201833 A1 = 0.2328472 A2 = 0.3+RDSW = 198.7483291 PRWG = 0.5 PRWB = -0.4971827+WR = 1 WINT = 0 LINT = 2.943206E-8+XL = 0 XW = -1E-8 DWG = -1.949253E-8+DWB = -2.824041E-9 VOFF = -0.0979832 NFACTOR = 1.9624066+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 7.282772E-4 ETAB = -3.818572E-4+DSUB = 1.518344E-3 PCLM = 1.4728931 PDIBLC1 = 2.138043E-3+PDIBLC2 = -9.966066E-6 PDIBLCB = -1E-3 DROUT = 4.276128E-4+PSCBE1 = 4.850167E10 PSCBE2 = 5E-10 PVAG = 0+DELTA = 0.01 RSH = 8.2 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.47E-10 CGSO = 7.47E-10 CGBO = 1E-12+CJ = 1.180017E-3 PB = 0.8560642 MJ = 0.4146818+CJSW = 2.046463E-10 PBSW = 0.9123142 MJSW = 0.316175+CJSWG = 4.22E-10 PBSWG = 0.9123142 MJSWG = 0.316175

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+CF = 0 PVTH0 = 8.456598E-4 PRDSW = 8.4838247+PK2 = 1.338191E-3 WKETA = 0.0246885 LKETA = -2.016897E-3+PU0 = -1.5089586 PUA = -5.51646E-11 PUB = 1E-21+PVSAT = 50 PETA0 = 1E-4 PKETA = -3.316832E-3 )*

MN1 N7 N3 N1 N1 PMOS l= .18u W= .3u MN2 N6 N8 N1 N1 PMOS l= .18u W= .3u MN3 N7 N7 0 0 NMOS l= .18u W= .6u MN4 N6 N7 0 0 NMOS l= .18u W= .6u MN5 N1 N9 N2 N2 PMOS l= .18u W= .3u MN6 N3 N9 N2 N2 PMOS l= .18u W= .3u MN7 N3 N6 0 0 NMOS l= .18u W= .6u MN8 N5 N9 N2 N2 PMOS l= .18u W= .3u MN9 N5 N6 0 0 NMOS l= .18u W= .6u MN10 N10 N2 N6 N6 NMOS l= .18u W= .6u MN11 N11 N12 N8 N8 NMOS l= .18u W= .6u C3 N10 N3 1PF

VY N11 0 0.7VVX N12 0 PULSE (0 0.9 0.01n 0.001n 0.001n 5n 10n)

VDD N2 0 1.8VVb N9 0 0.9V

C2 N3 N5 1ffC1 N8 0 1ff

.tran 0.01ns 20ns*.param width = 1u*.step lin param width 0.18u .3u 0.02u

*V31 N31 0 0V*.dc V31 0 1.8 0.01*V4 N31 0 0V*.dc iref 20ua 100ua 2ua

*iss N4 0 1mA

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*VIN N31 0 PULSE (3.3 2.9 0.01n 0.001n 0.001n 0.025n .05n) *VINbar N32 0 PULSE (2.9 3.3 0.01n 0.001n 0.001n 0.025n .05n)

*.DC V_IND 0 3.8 0.1*.PRINT ID(MN1)*.ac dec 100 1khz 1000Ghz* .PRINT ac VDB(R2) VP(R2).op*.TRAN .1nS 20ns*.dc v2 0 2 0.1 *.plot tran V(vin).probe.end

22

Simulation output for CCII:

23

Fig.4: Simulation output for CCII

Chapter-4Sample and Hold circuit

(S/H)

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Definition:A circuit that measures an input signal at a series of definite times, and whose output remains constant at a value corresponding to the most recent measurement until the next measurement is made.

General explanation:

In electronics, a sample and hold circuit is an analog device that samples (captures, grabs) the voltage of a continuously varying analog signal and holds (locks, freezes) its value at a constant level for a specified minimal period of time. Sample and hold circuits and related peak detectors are the elementary analog memory devices. They are typically used in analog-to-digital converters to eliminate variations in input signal that can corrupt the conversion process.

Working:

A typical sample and hold circuit stores electric charge in a capacitor and contains at least one fast FET switch and at least one operational amplifier.To sample the input signal the switch connects the capacitor to the output of a buffer amplifier. The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is practically equal, or proportional to, input voltage. In hold mode the switch disconnects the capacitor from the buffer. The capacitor is invariably discharged by its own leakage currents and useful load currents, which makes the circuit inherently

25

Fig.5: Typical sample and hold circuit

volatile, but the loss of voltage (voltage drop) within a specified hold time remains within an acceptable error margin.

Purpose

The reasons for using such a circuit are varied. In some kinds of analog-to-digital converters, the input is often compared to a voltage generated internally from a digital-to-analog converter. The circuit tries a series of values and stops converting once the voltages are "the same" within some defined error margin. If the input value was permitted to change during this comparison process, the resulting conversion would be inaccurate and possibly completely unrelated to the true input value. Such successive approximation converters will often incorporate internal sample and hold circuitry. In addition, sample and hold circuits are often used when multiple samples need to be measured at the same time. Each value is sampled and held, using a common sample clock.

Implementation

In order that the input voltage is held constant for all practical purposes, it is essential that the capacitor have very low leakage, and that it not be loaded to any significant degree which calls for a very high input impedance.

A true sample and hold circuit is connected to the buffer for a short period of time; a track and hold circuit is designed to track input continuously.

CCII based CMOS impementation of S/H circuit

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Fig.5 is the S/H circuit, when φ1=1, the S/H is in the sample mode and the input signal is sampled on the capacitor C1. When φ1=0, the S/H is in the hold mode and the output Vout will be copied from the voltage sampled in C1. The output voltage can be expressed as

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Fig.6: CCII based S/H

Coding for simulation of sample and hold circuit (S/H):Taking:VN11=VinVN5=VOUT

*rise time = 6.58*10-11 fal time = 1.04*10-11.MODEL NMOS NMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3750766+K1 = 0.5842025 K2 = 1.245202E-3 K3 = 1E-3+K3B = 0.0295587 W0 = 1E-7 NLX = 1.597846E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.3022984 DVT1 = 0.4021873 DVT2 = 7.631374E-3+U0 = 296.8451012 UA = -1.179955E-9 UB = 2.32616E-18+UC = 7.593301E-11 VSAT = 1.747147E5 A0 = 2+AGS = 0.452647 B0 = 5.506962E-8 B1 = 2.640458E-6+KETA = -6.860244E-3 A1 = 7.885522E-4 A2 = 0.3119338+RDSW = 105 PRWG = 0.4826 PRWB = -0.2+WR = 1 WINT = 4.410779E-9 LINT = 2.045919E-8+XL = 0 XW = -1E-8 DWG = -2.610453E-9+DWB = -4.344942E-9 VOFF = -0.0948017 NFACTOR = 2.1860065+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 1.991317E-3 ETAB = 6.028975E-5+DSUB = 0.0217897 PCLM = 1.7062594 PDIBLC1 = 0.2320546+PDIBLC2 = 1.670588E-3 PDIBLCB = -0.1 DROUT = 0.8388608+PSCBE1 = 1.904263E10 PSCBE2 = 1.546939E-8 PVAG = 0+DELTA = 0.01 RSH = 7.1 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5

28

+CGDO = 6.7E-10 CGSO = 6.7E-10 CGBO = 1E-12+CJ = 9.550345E-4 PB = 0.8 MJ = 0.3762949+CJSW = 2.083251E-10 PBSW = 0.8 MJSW = 0.1269477+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1269477+CF = 0 PVTH0 = -2.369258E-3 PRDSW = -1.2091688+PK2 = 1.845281E-3 WKETA = -2.040084E-3 LKETA = -1.266704E-3+PU0 = 1.0932981 PUA = -2.56934E-11 PUB = 0+PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.350276E-3 )*.MODEL PMOS PMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3936726+K1 = 0.5750728 K2 = 0.0235926 K3 = 0.1590089+K3B = 4.2687016 W0 = 1E-6 NLX = 1.033999E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.5560978 DVT1 = 0.2490116 DVT2 = 0.1+U0 = 112.5106786 UA = 1.45072E-9 UB = 1.195045E-21+UC = -1E-10 VSAT = 1.168535E5 A0 = 1.7211984+AGS = 0.3806925 B0 = 4.296252E-7 B1 = 1.288698E-6+KETA = 0.0201833 A1 = 0.2328472 A2 = 0.3+RDSW = 198.7483291 PRWG = 0.5 PRWB = -0.4971827+WR = 1 WINT = 0 LINT = 2.943206E-8+XL = 0 XW = -1E-8 DWG = -1.949253E-8+DWB = -2.824041E-9 VOFF = -0.0979832 NFACTOR = 1.9624066+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 7.282772E-4 ETAB = -3.818572E-4+DSUB = 1.518344E-3 PCLM = 1.4728931 PDIBLC1 = 2.138043E-3+PDIBLC2 = -9.966066E-6 PDIBLCB = -1E-3 DROUT = 4.276128E-4+PSCBE1 = 4.850167E10 PSCBE2 = 5E-10 PVAG = 0+DELTA = 0.01 RSH = 8.2 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1

29

+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.47E-10 CGSO = 7.47E-10 CGBO = 1E-12+CJ = 1.180017E-3 PB = 0.8560642 MJ = 0.4146818+CJSW = 2.046463E-10 PBSW = 0.9123142 MJSW = 0.316175+CJSWG = 4.22E-10 PBSWG = 0.9123142 MJSWG = 0.316175+CF = 0 PVTH0 = 8.456598E-4 PRDSW = 8.4838247+PK2 = 1.338191E-3 WKETA = 0.0246885 LKETA = -2.016897E-3+PU0 = -1.5089586 PUA = -5.51646E-11 PUB = 1E-21+PVSAT = 50 PETA0 = 1E-4 PKETA = -3.316832E-3 )*

MN1 N7 N3 N1 N1 PMOS l= .18u W= .3uMN2 N6 N8 N1 N1 PMOS l= .18u W= .3uMN3 N7 N7 N4 N4 NMOS l= .18u W= .6uMN4 N6 N7 N4 N4 NMOS l= .18u W= .6uMN5 N1 N9 N2 N2 PMOS l= .18u W= .3uMN6 N3 N9 N2 N2 PMOS l= .18u W= .3uMN7 N3 N6 N4 N4 NMOS l= .18u W= .6uMN8 N5 N9 N9 N2 PMOS l= .18u W= .3uMN9 N5 N6 N4 N4 NMOS l= .18u W= .6uMN10 N10 N2 N6 N6 NMOS l= .18u W= .6uMN11 N11 N12 N8 N8 NMOS l= .18u W= .6u

C1 N8 0 1ffC2 N3 N5 1ffC3 N10 N3 1ffV1 N2 0 1.8VV2 N9 0 0.9VV3 N11 0 0.7VV4 N12 0 PULSE ( 0 1.8 1n 1n 1n 0.1n 20n)

.tran 0.01ns 20ns*.param width = 1u*.step lin param width 0.18u .3u 0.02u

*V31 N31 0 0V*.dc V31 0 1.8 0.01*V4 N31 0 0V

30

*.dc iref 20ua 100ua 2ua

*iss N4 0 1mA*VIN N31 0 PULSE (3.3 2.9 0.01n 0.001n 0.001n 0.025n .05n) *VINbar N32 0 PULSE (2.9 3.3 0.01n 0.001n 0.001n 0.025n .05n)

*.DC V_IND 0 3.8 0.1*.PRINT ID(MN1)*.ac dec 100 1khz 1000Ghz* .PRINT ac VDB(R2) VP(R2).op*.TRAN .1nS 20ns*.dc v2 0 2 0.1 *.plot tran V(vin).probe.end

31

Simulation output for S/H circuit:

Here:VN11=VinVN5=VOUT

32

Fig.7: Simulation output for S/H

Chapter-5

Multiplying Digital to analog converter(MDAC)

33

Introduction:The output voltage Vo of a DAC is proportional to reference voltage Vref. The conventional DAC’s have an internal Vref , whereas a multiplying DAC has an external Vref. Vref can be a time varying signal.

Standard DAC have constant voltage reference or narrow range of voltage reference. Multiplying DAC have wide range of voltage reference. So multiplying DAC may multiply input voltage reference and digital code,that is output voltage of DAC equals product of input voltage reference and digital code Vout = Vin * N.

Explanation:

The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a physical quantity, usually an electrical voltage. Normally the output voltage is a linear function of the input number. Usually these numbers are updated at uniform sampling intervals and can be thought of as numbers obtained from a sampling process. These numbers are written to the DAC, sometimes along with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant output. This is equivalently a zero-order hold operation and has an effect on the frequency response of the reconstructed signal.

Multiplying DAC allows o/p voltage to be varied i\p with input reference voltage.

34

CCII based CMOS implementation of MDAC:

The MDAC circuit shown in Fig. 4(b) operates similar to the S/H circuit. When φ1=1, the input is sampled on both capacitors C1 and C2, and the two capacitors are series together in the next phase φ2 and the bottom plate of capacitor C2 connects to VR (VR = ±V ref or 0). The output voltage Vout is

To correspond 1.5-bit/stage architecture for the pipelined ADC, the Vout can be expressed as below by simplifying αv =1

The output Vout is determined by two terminals X and Z with the same current which makes the output voltage settling faster. The feedback capacitor C3 between terminals X and Z plays the major role to determine the output voltage simultaneously.

The settling time ts of the MDAC circuit can be derived as

35

Fig.8: CCII based MDAC circuit

Where ξ is the factor that effects the settling time and CL is the loading capacitance. Fig. 5 shows the simulation result of settling time for the MDAC circuit. The circuit with the Z-terminal capacitor feedback can decrease the settling time. With the Z-terminal capacitor feedback, the circuit is up to 38% in settling time faster than that of without the Z-terminal capacitor feedback.

Comparison of settling time for the MDAC circuit

36

Fig.9: Comparison of settling time for the MDAC circuit

Coding for MDAC:Taking:VN3=VoutVN13=Vin

*rise time = 6.58*10-11 fal time = 1.04*10-11.MODEL NMOS NMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3750766+K1 = 0.5842025 K2 = 1.245202E-3 K3 = 1E-3+K3B = 0.0295587 W0 = 1E-7 NLX = 1.597846E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.3022984 DVT1 = 0.4021873 DVT2 = 7.631374E-3+U0 = 296.8451012 UA = -1.179955E-9 UB = 2.32616E-18+UC = 7.593301E-11 VSAT = 1.747147E5 A0 = 2+AGS = 0.452647 B0 = 5.506962E-8 B1 = 2.640458E-6+KETA = -6.860244E-3 A1 = 7.885522E-4 A2 = 0.3119338+RDSW = 105 PRWG = 0.4826 PRWB = -0.2+WR = 1 WINT = 4.410779E-9 LINT = 2.045919E-8+XL = 0 XW = -1E-8 DWG = -2.610453E-9+DWB = -4.344942E-9 VOFF = -0.0948017 NFACTOR = 2.1860065+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 1.991317E-3 ETAB = 6.028975E-5+DSUB = 0.0217897 PCLM = 1.7062594 PDIBLC1 = 0.2320546+PDIBLC2 = 1.670588E-3 PDIBLCB = -0.1 DROUT = 0.8388608+PSCBE1 = 1.904263E10 PSCBE2 = 1.546939E-8 PVAG = 0+DELTA = 0.01 RSH = 7.1 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0

37

+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 6.7E-10 CGSO = 6.7E-10 CGBO = 1E-12+CJ = 9.550345E-4 PB = 0.8 MJ = 0.3762949+CJSW = 2.083251E-10 PBSW = 0.8 MJSW = 0.1269477+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1269477+CF = 0 PVTH0 = -2.369258E-3 PRDSW = -1.2091688+PK2 = 1.845281E-3 WKETA = -2.040084E-3 LKETA = -1.266704E-3+PU0 = 1.0932981 PUA = -2.56934E-11 PUB = 0+PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.350276E-3 )*.MODEL PMOS PMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3936726+K1 = 0.5750728 K2 = 0.0235926 K3 = 0.1590089+K3B = 4.2687016 W0 = 1E-6 NLX = 1.033999E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.5560978 DVT1 = 0.2490116 DVT2 = 0.1+U0 = 112.5106786 UA = 1.45072E-9 UB = 1.195045E-21+UC = -1E-10 VSAT = 1.168535E5 A0 = 1.7211984+AGS = 0.3806925 B0 = 4.296252E-7 B1 = 1.288698E-6+KETA = 0.0201833 A1 = 0.2328472 A2 = 0.3+RDSW = 198.7483291 PRWG = 0.5 PRWB = -0.4971827+WR = 1 WINT = 0 LINT = 2.943206E-8+XL = 0 XW = -1E-8 DWG = -1.949253E-8+DWB = -2.824041E-9 VOFF = -0.0979832 NFACTOR = 1.9624066+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 7.282772E-4 ETAB = -3.818572E-4+DSUB = 1.518344E-3 PCLM = 1.4728931 PDIBLC1 = 2.138043E-3+PDIBLC2 = -9.966066E-6 PDIBLCB = -1E-3 DROUT = 4.276128E-4+PSCBE1 = 4.850167E10 PSCBE2 = 5E-10 PVAG = 0+DELTA = 0.01 RSH = 8.2 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0

38

+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.47E-10 CGSO = 7.47E-10 CGBO = 1E-12+CJ = 1.180017E-3 PB = 0.8560642 MJ = 0.4146818+CJSW = 2.046463E-10 PBSW = 0.9123142 MJSW = 0.316175+CJSWG = 4.22E-10 PBSWG = 0.9123142 MJSWG = 0.316175+CF = 0 PVTH0 = 8.456598E-4 PRDSW = 8.4838247+PK2 = 1.338191E-3 WKETA = 0.0246885 LKETA = -2.016897E-3+PU0 = -1.5089586 PUA = -5.51646E-11 PUB = 1E-21+PVSAT = 50 PETA0 = 1E-4 PKETA = -3.316832E-3 )*

MN1 N7 N3 N1 N1 PMOS l= .18u W= .3uMN2 N6 N8 N1 N1 PMOS l= .18u W= .3uMN3 N7 N7 N4 N4 NMOS l= .18u W= .6uMN4 N6 N7 N4 N4 NMOS l= .18u W= .6uMN5 N1 N9 N2 N2 PMOS l= .18u W= .3uMN6 N3 N9 N2 N2 PMOS l= .18u W= .3uMN7 N3 N6 N4 N4 NMOS l= .18u W= .6uMN8 N5 N9 N9 N2 PMOS l= .18u W= .3uMN9 N5 N6 N4 N4 NMOS l= .18u W= .6uMN10 N10 N2 N6 N6 NMOS l= .18u W= .6uMN11 N8 N11 N12 N12 NMOS l= .18u W= .6uMN12 N12 N19 N13 N13 NMOS l= .18u W= .6uMN13 N8 N19 N14 N14 NMOS l= .18u W= .6uMN14 N15 N11 N14 N14 NMOS l= .18u W= .6uMN15 N13 N19 N15 N15 NMOS l= .18u W= .6uMN16 N14 N19 N16 N16 NMOS l= .18u W= .6uMN17 N17 N19 0 0 NMOS l= .18u W= .6uMN18 N18 N11 N17 N17 NMOS l= .18u W= .6u

C1 N12 N14 1ffC2 N15 N16 1ffC3 N3 N5 1ffC4 N10 N3 1ffV1 N2 0 1.8VV2 N9 0 0.9V

39

V3 N13 0 0.9VV4 N18 0 0VV5 N19 0 PULSE ( 0 1.8 1n 1n 1n 0.1n 20n)V6 N11 0 PULSE ( 1.8 0 1n 1n 1n 0.1n 20n)

.tran 0.01ns 20ns*.param width = 1u*.step lin param width 0.18u .3u 0.02u

*V31 N31 0 0V*.dc V31 0 1.8 0.01*V4 N31 0 0V*.dc iref 20ua 100ua 2ua

*iss N4 0 1mA*VIN N31 0 PULSE (3.3 2.9 0.01n 0.001n 0.001n 0.025n .05n) *VINbar N32 0 PULSE (2.9 3.3 0.01n 0.001n 0.001n 0.025n .05n)

*.DC V_IND 0 3.8 0.1*.PRINT ID(MN1)*.ac dec 100 1khz 1000Ghz* .PRINT ac VDB(R2) VP(R2).op*.TRAN .1nS 20ns*.dc v2 0 2 0.1 *.plot tran V(vin).probe.end

40

Simulation output for MDAC:

Here,VN3=VoutVN13=Vin

41

Fig.10: simulation output for MDAC

Chapter-6Comparator

42

Introduction:

In electronics, a comparator is a device that compares two voltages or currents and switches its output to indicate which is larger. They are commonly used in devices such as Analog-to-digital converters (ADCs).

Comparing to the CCII, another important circuit in the pipelined ADC is the comparator which can be composed with resistors for use as the flash ADC (i.e. sub-ADC) in every stage. Since there are error correction circuits in the proposed pipelined ADC, the required accuracy of the comparator can be tolerated. Therefore, it can employ the lower accuracy comparators rather than the pre-amplifier ones, ± 1/4Vref still can be achieved.

CCII based CMOS implementation of comparator:

43

Fig.11: CMOS based comparator circuit

A low power transconductance latched comparator is employed in the pipelined ADC design and the circuit is shown in Fig. This comparator is constructed of a power switch (M15), reset transistors (M13, M14), input transistors (M9, M11), a feedback latch circuit (M1~M4), and the cutting transistors (M10, M12) with feedback inverters (M5~M6, M7~M8). When the CLK is high, the comparator is in a reset period. At this period, the power switch M15 is turned off and the reset transistors are turn on which make the terminals Vout+ and Vout- at the GND level. When the CLK is low, the comparator is in the operation period. At this period, the power switch is turn on and reset transistors are turned off. The feedback latch circuit (M1~M4) amplifies the voltage gap at terminal Vout+ and Vout- to the full range which due to the difference in the input transconductance. When the voltage at terminal Vout+ or Vout- achieves to the voltage level of VDD, the cutting transistors (M10, M12) are turned off by the feedback inverter. Because the feedback inverter cut off the DC current path, the power consumption is very low.

44

Coding for comparatorTaking:VN4=Vout+VN5=Vout-VN3=Vref

*rise time = 6.58*10-11 fal time = 1.04*10-11.MODEL NMOS NMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3750766+K1 = 0.5842025 K2 = 1.245202E-3 K3 = 1E-3+K3B = 0.0295587 W0 = 1E-7 NLX = 1.597846E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 1.3022984 DVT1 = 0.4021873 DVT2 = 7.631374E-3+U0 = 296.8451012 UA = -1.179955E-9 UB = 2.32616E-18+UC = 7.593301E-11 VSAT = 1.747147E5 A0 = 2+AGS = 0.452647 B0 = 5.506962E-8 B1 = 2.640458E-6+KETA = -6.860244E-3 A1 = 7.885522E-4 A2 = 0.3119338+RDSW = 105 PRWG = 0.4826 PRWB = -0.2+WR = 1 WINT = 4.410779E-9 LINT = 2.045919E-8+XL = 0 XW = -1E-8 DWG = -2.610453E-9+DWB = -4.344942E-9 VOFF = -0.0948017 NFACTOR = 2.1860065+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 1.991317E-3 ETAB = 6.028975E-5+DSUB = 0.0217897 PCLM = 1.7062594 PDIBLC1 = 0.2320546+PDIBLC2 = 1.670588E-3 PDIBLCB = -0.1 DROUT = 0.8388608+PSCBE1 = 1.904263E10 PSCBE2 = 1.546939E-8 PVAG = 0+DELTA = 0.01 RSH = 7.1 MOBMOD = 1

45

+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 6.7E-10 CGSO = 6.7E-10 CGBO = 1E-12+CJ = 9.550345E-4 PB = 0.8 MJ = 0.3762949+CJSW = 2.083251E-10 PBSW = 0.8 MJSW = 0.1269477+CJSWG = 3.3E-10 PBSWG = 0.8 MJSWG = 0.1269477+CF = 0 PVTH0 = -2.369258E-3 PRDSW = -1.2091688+PK2 = 1.845281E-3 WKETA = -2.040084E-3 LKETA = -1.266704E-3+PU0 = 1.0932981 PUA = -2.56934E-11 PUB = 0+PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.350276E-3 )*.MODEL PMOS PMOS ( LEVEL = 7+ TNOM = 27 TOX = 4.1E-9+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3936726+K1 = 0.5750728 K2 = 0.0235926 K3 = 0.1590089+K3B = 4.2687016 W0 = 1E-6 NLX = 1.033999E-7+DVT0W = 0 DVT1W = 0 DVT2W = 0+DVT0 = 0.5560978 DVT1 = 0.2490116 DVT2 = 0.1+U0 = 112.5106786 UA = 1.45072E-9 UB = 1.195045E-21+UC = -1E-10 VSAT = 1.168535E5 A0 = 1.7211984+AGS = 0.3806925 B0 = 4.296252E-7 B1 = 1.288698E-6+KETA = 0.0201833 A1 = 0.2328472 A2 = 0.3+RDSW = 198.7483291 PRWG = 0.5 PRWB = -0.4971827+WR = 1 WINT = 0 LINT = 2.943206E-8+XL = 0 XW = -1E-8 DWG = -1.949253E-8+DWB = -2.824041E-9 VOFF = -0.0979832 NFACTOR = 1.9624066+CIT = 0 CDSC = 2.4E-4 CDSCD = 0+CDSCB = 0 ETA0 = 7.282772E-4 ETAB = -3.818572E-4+DSUB = 1.518344E-3 PCLM = 1.4728931 PDIBLC1 = 2.138043E-3+PDIBLC2 = -9.966066E-6 PDIBLCB = -1E-3 DROUT = 4.276128E-4

46

+PSCBE1 = 4.850167E10 PSCBE2 = 5E-10 PVAG = 0+DELTA = 0.01 RSH = 8.2 MOBMOD = 1+PRT = 0 UTE = -1.5 KT1 = -0.11+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4+WL = 0 WLN = 1 WW = 0+WWN = 1 WWL = 0 LL = 0+LLN = 1 LW = 0 LWN = 1+LWL = 0 CAPMOD = 2 XPART = 0.5+CGDO = 7.47E-10 CGSO = 7.47E-10 CGBO = 1E-12+CJ = 1.180017E-3 PB = 0.8560642 MJ = 0.4146818+CJSW = 2.046463E-10 PBSW = 0.9123142 MJSW = 0.316175+CJSWG = 4.22E-10 PBSWG = 0.9123142 MJSWG = 0.316175+CF = 0 PVTH0 = 8.456598E-4 PRDSW = 8.4838247+PK2 = 1.338191E-3 WKETA = 0.0246885 LKETA = -2.016897E-3+PU0 = -1.5089586 PUA = -5.51646E-11 PUB = 1E-21+PVSAT = 50 PETA0 = 1E-4 PKETA = -3.316832E-3 )*

MN1 N10 N9 N8 N8 NMOS l= .18u W= .3u MN2 N9 N10 N8 N8 NMOS l= .18u W= .3u MN3 N10 N9 0 0 NMOS l= .18u W= .6u MN4 N9 N10 0 0 NMOS l= .18u W= .6u MN5 N1 N5 N2 N2 NMOS l= .18u W= .3u MN6 N1 N5 0 0 NMOS l= .18u W= .3u MN7 N3 N4 N2 N2 PMOS l= .18u W= .6u MN8 N3 N4 0 0 NMOS l= .18u W= .3u MN9 N5 N1 N10 N10 NMOS l= .18u W= .6u MN10 N10 N1 0 0 NMOS l= .18u W= .6u MN11 N4 N3 N11 N11 NMOS l= .18u W= .6u MN12 N11 N3 N0 N0 NMOS l= .18u W= .6uMN13 N5 N6 N0 N0 NMOS l= .18u W= .6uMN14 N4 N6 N0 N0 NMOS l= .18u W= .6uMN15 N8 N6 N2 N2 NMOS l= .18u W= .6u

VREF N3 0 0.7V

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VOUT N5 0 0.7VVOUT+ N4 0 0.7VVX N6 0 PULSE ( 0 1.8 1n 1n 1n 0.1n 20n)

VDD N2 0 1.8VVIN N1 0 0.9V

.tran 0.01ns 20ns*.param width = 1u*.step lin param width 0.18u .3u 0.02u

*V31 N31 0 0V*.dc V31 0 1.8 0.01*V4 N31 0 0V*.dc iref 20ua 100ua 2ua

*iss N4 0 1mA*VIN N31 0 PULSE (3.3 2.9 0.01n 0.001n 0.001n 0.025n .05n) *VINbar N32 0 PULSE (2.9 3.3 0.01n 0.001n 0.001n 0.025n .05n)

*.DC V_IND 0 3.8 0.1*.PRINT ID(MN1)*.ac dec 100 1khz 1000Ghz* .PRINT ac VDB(R2) VP(R2).op*.TRAN .1nS 20ns*.dc v2 0 2 0.1 *.plot tran V(vin).probe.end

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Simulation output for comparator

Here:VN4=Vout+VN5=Vout-VN3=Vref

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Fig.12: simulation output for comparator

Chapter-7Clock generator and delay circuit

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Clock generator and delay circuit:

Introduction:A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's operation. The signal can range from a simple symmetrical square wave to more complex arrangements.

Dealy circuit:An electronic simulation device for reproduction of a signal with a delay equal to a predetermined time interval τ.

Implementation: There are many switches in the entire design. The circuit of the

control signal generator is shown in Fig. It generates two control signals, CLK1 and CLK2. Under the 10 MHz

operation frequency, the time interval between these two clocks is 1ns.

The overall delay circuit used in proposed pipelined ADC is shown in Fig. 8.

Here, we employ D-type flip-flops to complete the delay function. The digital error correction circuit is also realized in our design.

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Fig.13: Non-overlap clock generator

The overall delay circuit is:

VHDL coding for the delay circuit:Library ieee;Use ieee.std_logic_1164.all;

entity d_not isport (a,clk:in std_logic;b:out std_logic);end d_not;

architecture d_not11 of d_not isbeginprocess(clk)

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Fig.14: Overall delay circuit

beginif(clk=’1’)b<=not a;end if;end process;end d_not11;

Conclusion:A new CCII-based pipelined ADC is implemented in this project. Two main building blocks of the pipelined ADC, S/H and MDAC circuits are constructed of CCIIs instead of OAs. The Z-terminal capacitor feedback in CCIIs can shorten the settling time. Because of the 1.5 bit/stage architecture with error correction circuits in the pipelined ADC, the required accuracy of the comparator can be tolerated. The CCII-based pipelined ADC is realized in a 0.18μm CMOS technology and consumes 29mW under a 3.3V power supply.

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References:1. A New CCII-Based Pipelined Analog to Digital Converter

Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen Department of Electronic Engineering National Taipei University of Technology Taipei, Taiwan, R.O.C.

2. OrCAD website for PSpice (http://www.orcad.com/pspicead.aspx), has application notes, download, examples and interesting links.

3. OrCAD website for CAPTURE. (http://www.orcad.com/orcadcapture.aspx)

4. PSpice User’s manual , OrCAD Corp. (Cadence Design Systems, Inc.) 5. Low Voltage, Low Power and High Performance Current Conveyors for Low Voltage

Analog and Mixed Mode Signal Processing Applications∗

S.S. RAJPUT1,† AND S.S. JAMUAR21Thin Film Technology Group, National Physical Laboratory, Dr. K.S. Krishnan Marg, New Delhi 110012, India 2Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi 110016, India

6. Current conveyor theory and practiceAdel S. Sedra and Gordon W Roberts

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