Final Thesis - ADC

HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

SCHOOL OF ELECTRONICS AND TELECOMMUNICATIONS

A GRADUATION THESIS FOR

BACHELOR OF ENGINEERING

Topic:

DESIGN OF LOW POWER HIGH LINEARITY SAR

ADC WITH REDUNDANCY AND DIGITAL

BACKGROUND CALIBRATION

Student: NGUYEN VIET TAN 20092354

Class: Microelectronics Advance Program K54

Supervisor: Dr. NGUYEN VU THANG

Committee member:

Hanoi, 6-2014

MINISTRY OF EDUCATION AND TRAINING

HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

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SOCIALIST REPUBLIC OF VIETNAM

Independence-Freedom-Happiness

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Abstract

Smart devices such as smart phone, smart watch, tablet are booming over

the last few years. One of the most important things that make these devices become

so popular is that they use different way from traditional ones to interface with user:

the touchscreen. With the touchscreen, the user can interact directly with what is

displayed, rather than using a mouse, touchpad, or any other intermediate device.

Every time, to know command from user, the analog signal from the touch panel (a

part of touch screen) will always be converted to digital signal by Analog to Digital

Converters (ADCs) and then sent to the CPU. Therefore, the ADC here plays a key

role in the sensitivity and energy-saving of the touch panel.

All smart devices are handheld device so the problem of saving power is one

of the most important one. So, up to now, Successive Approximation Register

(SAR) ADC is always chosen in the touch panel because of its low power

consumption. However, the resolution of SAR ADC is medium compare to other

kinds of ADC, this makes it become not suitable for the demand of high sensitivity

and accuracy touch panel. In order to solve the problem, this thesis describes the

design of a high linearity low power 12-bit synchronous successive approximation

register (SAR) ADC for touch panel.

The prototype has been implemented in TSMC 0.18m Mixed-Signal CMOS

technology, the simulated effective number of bits (ENOB) at near Nyquist

frequency is 12.3-bit. The total power consumption of 15.7W is achieved at

100ksps results in figure of merit (FoM) of only 30.9fJ/conversion-step.

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Acknowledgment

Five years studying in Hanoi University of Science and Technology is a

wonderful time in my life that I will never forget. It is not a long time, but not a

short time either. Throughout this time, I have been so happy and lucky to be

surrounded by family, friends, professors and classmates who have provided cheers

and support. I am indebted to all of them. Without their constant and unconditional

support, this would have never been accomplished.

I would like to express my sincere gratitude to my advisor Dr. Nguyen Vu

Thang for the continuous support of my Bachelor study and research, for his

patience, motivation, enthusiasm, and immense knowledge. There are a lot of thing

that I have learned from him: how to do research, to write a paper, give a coherent

talk, work in a group He gave me smart and valuable advises for problems in my

research as well as in my life whenever I needed.

I would like to thank my labmates in IC Design Lab: Nguyen Minh Duc, Dao

Ba Anh, Mai Tuan Anh, Do Minh Phu, Nguyen Tien Dat and my friends in Hanoi

University of Science and Technology for the stimulating discussions, for the

sleepless nights we were working together before deadlines, and for all the fun we

have had in the last five years.

I would like to thank Duong Viet Duc, Teaching Assistant and Research

Assistant at IC Design Lab, National Tsing Hua University, Hsinchu, Taiwan for his

valuable advises, support and experiment sharing through my Bachelor.

Last but not least, I would to thank my family who always has faith in me,

for their tremendous encouragement and unconditional support throughout my life.

Contents

Chapter 1 Introduction .............................................................................................. 1

1.1. Structure of Projected Capacitive Touch technology with mutual capacitive

approach ....................................................................................................................... 1

1.2. Architecture Selection ........................................................................................ 2

1.3. Performance Metrics of SAR ADCs .................................................................. 3

1.3.1. Resolution ................................................................................................. 4

1.3.2. Quantization Noise ................................................................................... 4

1.3.3. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) .......... 4

1.3.4. Signal-to-Noise Ratio (SNR).................................................................... 4

1.3.5. Effective Resolution ................................................................................. 5

1.3.6. Figure of Merit (FoM) .............................................................................. 5

1.4. Motivation .......................................................................................................... 5

1.5. Target Specifications .......................................................................................... 6

1.6. Thesis contributions ............................................................................................ 6

Chapter 2 Overview of Traditional SAR ADCs ...................................................... 9

2.1. Binary Successive Approximation Algorithm.................................................... 9

2.2. The SAR Architecture ...................................................................................... 11

2.3. Static Error Sources in SAR ADCs .................................................................. 15

2.3.1. Capacitor Mismatches ............................................................................ 15

2.3.2. Offset Errors ........................................................................................... 17

2.4. Dynamic Error Sources in SAR ADCs ............................................................ 18

Chapter 3 Redundancy SAR ADCs ......................................................................... 21

3.1. Redundancy Overview ..................................................................................... 21

3.1.1. Error tolerance windows for redundancy ............................................... 25

3.1.2. Dynamic Threshold Comparison............................................................ 26

3.2. Digital calibratability ........................................................................................ 27

3.2.1. Condition of digital calibratability ......................................................... 27

3.1.2.2. Amount of redundancy........................................................................ 28

3.1.2.3. Radix and number of steps .................................................................. 29

Chapter 4 Digital Background Calibration of SAR ADCs ................................... 32

4.2. Overview of digital calibration in SAR ADC .................................................. 32

4.1. Superposition Principle..................................................................................... 34

4.2. Perturbation-Based Calibration Algorithm ....................................................... 35

Chapter 5 Design and Implementation of a Redundancy SAR ADCs with

Digital Background Calibration ................................................................................. 40

5.1. Architecture ...................................................................................................... 40

5.1.1. SAR ADC architecture ........................................................................... 41

5.1.2. Calibration architecture .......................................................................... 42

5.2. Key circuit building block ................................................................................ 43

5.2.1. Capacitive DAC Design ......................................................................... 43

5.2.1.1. Monotonic Capacitor DAC Switching Operation ............................... 43

5.2.1.2. Main DAC design ............................................................................... 47

5.2.2. Sampling Network Design ..................................................................... 49

5.2.3. Dynamic comparator design ................................................................... 50

5.2.4. Preamplifier design ................................................................................. 51

5.2.5. Control logic design ............................................................................... 52

5.2.5.1. Flip flop design ................................................................................... 52

5.2.5.2. Clock generator ................................................................................... 53

5.2.5.3. Comparator control logic .................................................................... 53

5.2.5.4. Switch control logic ............................................................................ 55

5.2.5.5. Dynamic threshold comparison .......................................................... 56

5.2.5.6. Digital calibration circuits ................................................................... 57

Chapter 6 Simulation results ................................................................................... 60

6.1. Prototype Performance ..................................................................................... 60

6.1.1. Dynamic performance ............................................................................ 60

6.1.2. Static performance .................................................................................. 61

6.1.3. Performance summary and comparison ................................................. 61

Chapter 7 Conclusion and future work .................................................................. 64

7.1. Conclusion ........................................................................................................ 64

7.2. Future work ....................................................................................................... 65

Bibliography ................................................................................................................. 66

List of figure

Figure 1-1. Basic construction of a projected capacitive touch panel [1] ........................ 2

Figure 1-2. Block diagram of touch panel ....................................................................... 2

Figure 1-3. FoM versus sampling frequency of state-of-the-art ADCs published at

ISSCC and VLSI Symposium [3] .................................................................................... 3

Figure 1-4. A plot of the resolution versus the input sampling frequency for recent

published analog-to-digital converters in ISSCC and VLSI [3] ...................................... 3

Figure 2-1. An example of 5-bit quantization using a binary search algorithm [3]....... 10

Figure 2-2. Basic block diagram of a SAR ADC [3] ..................................................... 12

Figure 2-3. Schematics of the charge redistribution SAR implementation [3].............. 12

Figure 2-4. Switching scheme of a conventional SAR ADC [3] ................................... 13

Figure 2-5. An example ADC transfer function for SAR ADCs with/without

capacitor mismatches [3] ................................................................................................ 16

Figure 2-6. Effective number of bits (ENOB) versus normalized capacitor mismatch

in a 12-bit binary weighted SAR ADC [3]...................................................... 17

Figure 2-7. Schematic of a SAR ADC with offset errors [3] ......................................... 18

Figure 3-1: Binary search algorithm without redundancy. The search step sizes in

this example are binary weighted with values equal to 8, 4, 2 and 1 [3] ....................... 22

Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4-step)

and a sub-binary search algorithm (4-bit 6-step) [3]...................................................... 24

Figure 3-3: Digital error correction using redundancy in SAR ADCs [3] ..................... 24

Figure 3-4: Highlighted error tolerance windows ( ) for a sub-binary search SAR

ADC [3] .......................................................................................................................... 26

Figure 3-5: Transfer functions for SAR designs with step sizes that are binary,

subradix-2 and super-radix-2 weighted [3] .................................................................... 25

Figure 3-6: Illustration of Dynamic Threshold Comparison technique ......................... 26

Figure 3-7: Effective number of bits (N) versus number of steps (M) for different

radices () [3] ................................................................................................................. 28

Figure 3-8: The maximum radix and the minimum number of conversion steps [3] . 30

Figure 4-1. The superposition property of linear system [27] ....................................... 34

Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights). [27] ... 36

Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit weight

only). [27] ....................................................................................................................... 36

Figure 5-1: The architecture of overall ADC ................................................................. 41

Figure 5-2: SAR ADC architecture ................................................................................ 42

Figure 5-3: The block diagram of the perturbation-based background digital

calibration. ...................................................................................................................... 42

Figure 5-4: Conventional SAR switching algorithm, showing energy consumption

related to capacitor switching transitions [3] ................................................................. 44

Figure 5-5: The top-plate waveform when using the conventional switching

algorithm [3] ................................................................................................................... 44

Figure 5-6: The top-plate waveform when using the monotonic switching algorithm

[3] ................................................................................................................................... 46

Figure 5-7: Monotonic switching algorithm [3] ............................................................ 47

Figure 5-8: Comparing energy consumption of different switching algorithms [3] ...... 48

Figure 5-9: Bootstrap switch in [38] .............................................................................. 50

Figure 5-10: Dynamic comparator with a current source. ............................................. 51

Figure 5-11: The schematic of the preamplifier ............................................................. 52

Figure 5-12: Split-output True Single Phase Clock (TSPC) Flip Flop .......................... 53

Figure 5-13: Clock generator a) Schematic. b) Timing diagram ................................... 54

Figure 5-14: Comparator control circuit a) Schematic. b) Timing diagram .................. 55

Figure 5-15: DAC Control Logic ................................................................................... 56

Figure 5-16: Dynamic threshold comparison circuit ..................................................... 57

Figure 5-17: Block diagram of the inner product block................................................. 58

Figure 5-18: Block diagram of LMS bloc ...................................................................... 58

Figure 6-1: The measured output spectra of the SAR ADC .......................................... 61

Figure 6-2: The measured DNL and INL of the SAR ADC .......................................... 62

List of table

Table 1-1. Current state-of-the-art SAR ADCs ............................................................... 7

Table 5-1: Comparison of different switching schemes in terms of various figures of

merit [3] .......................................................................................................................... 48

Table 5-2: DAC capacitors value ................................................................................... 49

Table 6-1: Comparison of the state-of-the-art works ..................................................... 62

1

1 Introduction

Chapter 1

Introduction

In this chapter, the structure of touch panel and all the metrics of an ADC

will be discussed. After studying carefully about these things, the design target will

be created. The chapter is organized as follow. In section 1.1, the structure and

operation of a most common capacitive touchscreen will be described. Section 1.2

will discuss the reason why the SAR architecture is selected. Section 1.3 describes

the fundamentals and performance metrics. The motivation of the proposed ADC

will be explained in section 1.4, and finally, the target specifications will be

described in section 1.5.

1.1. Structure of Projected Capacitive Touch technology with

mutual capacitive approach

Projected Capacitive Touch (PCT; also PCAP) technology is a variant of

capacitive touch technology. All PCT touch screens are made up of a matrix of rows

and columns of conductive material as in Figure 1-1.

There is a capacitor at every intersection of each row and each column. A

voltage is applied to the rows (or columns) periodically. Bringing a finger or

conductive stylus close to the surface of the touch panel changes the local

electrostatic field which reduces the mutual capacitance. This will result in the

decrease of the voltage of the column. The capacitance change at every individual

point on the grid can be measured by measuring the voltage in the other axis. This

voltage will be digitalized by an ADC and the output code will be sent to processor

to accurately determine the touch location. Mutual capacitance allows multi-touch

operation where multiple fingers, palms or styli can be accurately tracked at the

same time. [2]

2

2 Introduction

Figure 1-1. Basic construction of a projected capacitive touch panel [1]

Processor

TX Drive

ADC RX Sense

Grid

Figure 1-2. Block diagram of touch panel

1.2. Architecture Selection

At very first step of the design process, a survey on performance of various

types of ADC is necessary for determining the most suitable type of ADC for the

target application. The typical requirements of an ADC in touch panel applications

in resolution, speed and power consumptions are 10-12 bits, few hundred kS/s and

few microwatts, respectively. A widely survey of recent published analog-to-digital

converters in ISSCC and VLSI [3] is used to compare the resolution, energy

efficiency and sampling frequency range among various types of ADC. From

Figure 1-3 and Figure 1-4, with high energy efficiency, medium to high resolution

and low to medium sampling frequency, successive approximation register (SAR)

ADC is the best candidate for the target application.

3

3 Introduction

Figure 1-3. FoM versus sampling frequency of state-of-the-art ADCs published

at ISSCC and VLSI Symposium [3]

Figure 1-4. A plot of the resolution versus the input sampling frequency for

recent published analog-to-digital converters in ISSCC and VLSI [3]

1.3. Performance Metrics of SAR ADCs

After ADC architecture is selected, to determine the target specification, it is

important to understand the fundamentals of the technical terms that define the

performance of a SAR ADC.

4

4 Introduction

1.3.1. Resolution

The resolution represents the number of digital output code, N, of the ADC.

Resolution determines the step size of the least significant bit as in Equation 1.1,

where N is the resolution of the ADC, and represents reference voltage.

(1.1)

1.3.2. Quantization Noise

In a SAR ADC, the full scaled analog input is quantized by a total of

steps, each step is equal to 1 LSB. Due to rounding error, the difference between the

actual analog input and the quantized digital output is defined as the quantization

noise (error) which is derived as Equation 1.2.

( )

(1.2)

1.3.3. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL)

In SAR ADC, the magnitude of each analog output step of the DAC is equal

to one LSB. The differential nonlinearity (DNL) expressed in Equation 1.3 is the

deviation of each analog step away from one LSB. Integral nonlinearity (INL)

represents the linearity of the ADC by measuring the distance of the code centers in

the A/D converter characteristic from the ideal line (drawn from zero point to full

scale point of the transfer function). INL can be calculated as the cumulative sum of

DNL from code ( ) to ( ) code ( ), as shown in Equation 1.4.

(( ) ) (1.3)

( ( )

) (1.4)

1.3.4. Signal-to-Noise Ratio (SNR)

Signal-to-noise ratio (SNR) is the ratio of rms value of the full scaled

sinusoid input signal to the rms value of quantization noise. It is calculated by

Equation 1.5, where N is the resolution. For an ideal 12-bit ADC, the maximum

SNR is 74dB.

5

5 Introduction

(

) (1.5)

1.3.5. Effective Resolution

Not only quantization noise, other non-idealities and practical errors also

degrade the SNR which is represented by the term of effective number of bits

(ENOB), as defined in Equation 1.6.

( )

(1.6)

1.3.6. Figure of Merit (FoM)

The Figure of Merit (FoM) defined as Equation 1.7 is the widely adopted

term to evaluate the overall performance of different types of ADC by normalizing

power consumption ( ) with input frequency ( ) and ENOB.

(1.7)

1.4. Motivation

As describe in section 1.1., the change in mutual capacitance at every

individual point can be measured by determining the voltage change at the other

axis. To make this voltage change large enough about several millivolts, the voltage

that is apply in one axis must be quite large, about 18 volts. This make the power

consumption of the touch panel become very large. To deal with this problem, there

is one way that if the resolution of the ADC becomes large enough, the voltage

change that we need can be reduced and the applied voltage will be not so high as a

result.

The biggest challenge in designing a high linearity is the DAC capacitors

mismatch error, which is the typical dominant factor that limits static linearity in a

switched-capacitor SAR ADC. To overcome this problem, the implementation

utilizes sub-radix-2 redundant architecture combined with digital background

calibration engine. The redundancy gives chances to reduce area of the DAC circuit

as well as improve the performance of switched-capacitor SAR ADC. It does not

only guarantee digitally correctable static nonlinearities of the converter but also

6

6 Introduction

offer means to combat dynamic errors in the conversion process. A perturbation-

based digital calibration technique is also applied to accomplish simultaneous

identification of multiple capacitor mismatch errors of the ADC, enabling the

downsizing of all sampling capacitors to save power and silicon area.

1.5. Target Specifications

Before defining the target specifications, it is worthwhile to visit some of

other state-of-the-art SAR ADCs (shown in Table 1.1), which have quite the same

typical specification requirements of an ADC in touch panel applications (operate

with sampling frequency range of several hundred kS/s, resolution around 10 bits or

larger and power consumption in the range of few microwatts to few tens of

microwatts).

The target specifications for the SAR ADC are to operate with a voltage

supply of 1.8V at sampling rate of 100kS/s, the ENOB needs to be greater than 11

bit while total power consumption less than 60 W. This leads to a FoM of

293fJ/Conversion step.

1.6. Thesis contributions

This work focuses on design of high precision and power efficient SAR

ADC. The materials in chapter 2, chapter 3 and chapter 4 are mainly taken form [3]

and [4]. The main contributions are the proposed calibration circuit to save

hardware resource and power, the reuse of main DAC to implement Dynamic

Threshold Comparison (DTC) to save the area and increase the error tolerance of

the circuit.

This thesis is organized as follows. In chapter 2, the overview of traditional

SAR ADC will be presented. Chapter 3 and chapter 4 will introduce about

redundancy SAR ADC and perturbation based calibration algorithm respectively.

The design implementation will be discussed in details in Chapter 5. Chapter 6 will

demonstrate the simulation results. Finally, the conclusion, and future work will be

drawn in Chapter 7.

7

7 Introduction

Ref [4] [5] [6] [7] This work

Year 2011 2013 2007 2013 --

Source JSSC TCAS2 JSSC JSSC --

Technology 0.13m 0.35m 0.18m 65nm 0.18m

Supply (V) 1.2V 2.3V 1V 1.2V 1.8V

Resolution (bit) 12 12 12 14 12

Fs (MS/s) 22.5 0.25 0.1 80 0.1

ENOB (bit) 11.3 11 10.5 11.9 11

Total Power (mW) 3 0.107 0.025 31.1 0.06

FOM (fJ/C-S) 51.3 209 165 164.7 293

Table 1-1. Current state-of-the-art SAR ADCs

8


9

9 Overview of Traditional SAR ADCs

Chapter 2

Overview of Traditional SAR ADCs

In previous chapter, the structure of projected capacitive touch technology was

introduced. Depend on the requirement (high resolution but low power

consumption) of the ADC for touch panel, the SAR architecture was selected

among various types of ADC due to its energy-efficient switching and digital

scalability with technology. After presenting about performance metrics of SAR

ADC, the motivation of this work and studying some of other state-of-the-art SAR

ADCs performance, the target specification was determined.

In this chapter, the operation of a traditional SAR ADC will be analyzed.

First, the Binary Successive Approximation Algorithm search algorithm for

Nyquist-rate ADCs is introduced. The implementation and operation of a SAR

ADC will be discussed in the second part of this chapter. Due to the non-idealities

of the circuit components, errors will occur during the conversion process; these

errors limit the achievable speed and accuracy of a SAR ADC. The final part of this

chapter focuses on analyzing these errors. Based on the sources of these errors, they

are broken down into static and dynamic parts.

2.1. Binary Successive Approximation Algorithm

In binary successive approximation algorithm, one bit is resolved at a

time. The first bit is generated by comparing the input to the mid-full-scale-level of

the current search range. Depend on the comparison result, half of the search range

is eliminated and the same process continues until the entire conversion is

completed. Instead of using one clock cycle per conversion, this algorithm requires

N clock cycles and thus, N comparisons to complete a conversion.

10


An example of a 5-bit quantization of input 6.2 using binary successive

approximation search is shown in Figure 2-1. The mid decision level of the current

search range is represented by the solid black lines while the solid red line indicates

the location of the input level. At the beginning of the process, the search range is

full scale from 0 to 31. During the first comparison, (equal to 6.2) is compared

with the mid-full-scale level of the initial search range. Since 6.2 is less than 16, the

first output bit of ADC is '0' and the upper half of previous search range is

eliminated. The searching process continues until the final binary output 00110 is

produced after five clock cycles. In the last search, the range of uncertainty is

reduced to one LSB, resulting in quantization error within .

Figure 2-1. An example of 5-bit quantization using a binary search algorithm

[3]

Binary conversion is quite sensitive to errors made during the conversion

process. In an ideal binary implementation, none of the search ranges overlap.

Therefore, once a search range is eliminated from the search process, it can never be

reentered, so if an error is made, the correct search range cannot be recovered or

returned and thus the digital output can never be corrected. As a result, to produce

correct digital outputs, each conversion step need to be accurate and correct, this is

so difficult to accomplish in practice. Traditional SAR ADCs use the binary search

11


algorithm; however, in a later chapter, it will be shown that digital error correction

(or redundancy) can be used to greatly alleviate this problem.

2.2. The SAR Architecture

The SAR architecture performs the A-to-D conversions over multiple clock

cycles by using the value of the previous determined bit to assist in finding the next

significant bit. A typical block diagram of a SAR ADC is shown in Figure 2-2. It

involves four basic building blocks: sample and hold (S&H), DAC, SAR control

and comparator. In the conversion process, each block plays a different role: the

S&H samples one instance of the continuous analog input signal during the first

clock period and holds this value for the remaining conversion process, the

comparator generates each bit by comparing with and depend on the

output bits of the comparator, the SAR control reconfigures and updates the DAC.

An effective implementation of the DAC is the so-called charge

redistribution or capacitor array scheme [8, 9]. In this implementation, the

capacitive DAC performs both sample/hold function and subtractions in the charge

domain using capacitors. At the end of the conversion process, the charge is

properly re-distributed such that the top plate voltage on the DAC is approximately

the same as the voltage on the other input of the comparator ,which is zero in case

depicted in Figure 2-3. The SAR consists of an N-bit binary-weighted capacitive

DAC, a SAR control logic block and a comparator. Each capacitor within the DAC

can be re-configured by connecting it to either the input or the plus/minus reference

voltages. The total capacitance sums up to , where

(2.1)

During the sample and hold phase, the input signal is sampled at the bottom

plates of the DAC array by connecting them to the input and the top plate of the

array to ground (Figure 2-4(a)). The total charge stored in the array is

( ) (2.2)

12


Figure 2-2. Basic block diagram of a SAR ADC [3]

Figure 2-3. Schematics of the charge redistribution SAR implementation [3]

The conversion phase is begun after the sampling phase. During the first

step, the most-significant-bit (MSB) capacitor is connected to while the

remaining capacitors are connected to (Figure 2-4(b)). For simplicity, in this

example, it is assumed that and . Using the charge

conservation principle, the voltage on the top plate of the array, , becomes

(2.3)

In Equation 2.3, the first input sampling contributes to the first term and the the

MSB capacitor contributes to the second term. By comparing directly to ground,

the first output bit can be determined and the configuration is set for the

next bit calculation. stays connected with only if and it

will be switched to ground for the remaining cycles if . After that,

is switched to . Figure 2-4(c) and Figure 2-4(d) show two different

configurations, respectively. The top plate voltages of the two configurations can be

13


Figure 2-4. Switching scheme of a conventional SAR ADC [3]

calculated by Equations 2.4 and 2.5. The process of comparing and reconfiguring

continues until the last bit is obtained.

( )

(2.4)

14


(2.5)

At the end of the conversion, the input is converted into binary-weighted bit

sequences, [ ], and the final voltage on is

(2.6)

This voltage represents the quantization error of the entire conversion

process. Note that both the top and bottom plates of the DAC can have parasitic

capacitances contributed from non-ideal layout/wiring, gate capacitance of

comparators... The parasitic capacitances on the bottom plate are driven by low

impedance reference voltage supplies, and . Therefore, these will not

affect the conversion process if the reference voltages are completely settled. On the

other hand, the parasitic capacitance on the top plate decreases the amplitude of

sampled input. The attenuation factor can be calculated as

(2.7)

where is the total parasitic capacitance on the top plate. This attenuation reduces

the effective signal power, but does not change the polarity of the comparison

result, thus will not affect the correct output bits. The bottom-plate sampling

essentially enables this feature. In the sampling phase, the top plate is connected to

ground before the node becomes floating until the end of the conversion phase.

During the conversion, the voltage on the top plate changes but returns to a voltage

that is near zero at the end of the process. As a result, the total charge on at the

beginning and at the end of the process is the same and therefore, from the

perspective of charge, capacitor does not cause any charge error. Thus, it will not

affect the overall accuracy of the conversion process.

In summary, using a charge redistribution scheme in a SAR ADC has a lot of

advantages. It is energy efficient and only has dynamic but no DC power

consumption, if no pre-amplifier is used in the comparator design. The ADC is

robust against circuit non-idealities, such as parasitic capacitances. The architecture

is less limited by technology and supply voltage scaling compared to other

15


architectures since most parts of the ADC are digital, not analog. It also has the

potential to take full advantage of improved energy efficiency and speed in deeply-

scaled CMOS. A correctly implemented SAR ADC typically supports full rail-to-

rail input range, which can be advantageous for high-resolution designs. Lastly,

since the sampling capacitors are shared with the configurable DAC, SAR ADCs

can save significant areas and result in small chip area.

2.3. Static Error Sources in SAR ADCs

Even with all the architectural benefits discussed in the previous section, the

static performance of converter (measured by metrics: differential nonlinearity

(DNL), integral nonlinearity (INL), offset error and gain error) is still limited by the

matching of analog components by many ways, for example, mismatches in the

capacitive DAC can lead to incorrect charge distribution during the conversion

phase; mismatches in transistors can lead to offset errors in the comparator

2.3.1. Capacitor Mismatches

Good capacitor matching is the key for high accuracy ADCs. It is controlled

and influenced by manufacturing processes and physical design. The variation

sources can be divided into random statistical fluctuation and systematic

mismatches. Random mismatches include the difference in device dimensions, wire

sizing, doping, oxide thickness ... of practical value from desired value. These types

of mismatches cannot be completely eliminated. Typically, the solution for this is to

increase the overall dimension or to use special layout technique to improve

matching. Systematic mismatches results from temperature gradients, diffusion

interactions, mechanical stresses, biases in the processing steps... Even though some

of these mismatches sources can be combated by using careful design and layout, it

is still difficult to attain more than 10 bits of resolution.

When capacitors within the DAC are perfectly matched in a SAR ADC, the

input/output transfer function resembles a straight dotted line in Figure 2-5. This

implies linear mapping between the inputs and the outputs. Since all the steps have

equal size and they are evenly spaced over the full range, this 12-bit example is free

of any DNL and INL errors.

16


Figure 2-5. An example ADC transfer function for SAR ADCs with/without

capacitor mismatches [3]

On the other hand, when mismatch errors are present, the transfer function

deviates from the straight line as shown by the solid blue curve in Figure 2-5.

Misalignments occur in both the vertical and horizontal directions. Misalignment in

the vertical direction creates missing codes, which makes the DNL exceeds -1.

Misalignment in the horizontal direction creates missing levels, which implies that

some part of the original analog information is lost. Typically, missing codes are

digitally correctable while missing levels are not. As a result, ADCs should be

designed to avoid missing levels. More details on digital calibration, one effective

way to deal with capacitor mismatches, will be discussed in Chapter 3 and 4. Figure

2-6 shows the plot of ENOB versus the standard deviation of the unit capacitor [3].

It can be seen that even at 1% standard deviation in , the ENOB can be degraded

by more than 1 bit without taking into consideration other non-idealities in the

design. Therefore, control and calibration for the mismatches in capacitors play a

key role in high-resolution design.

17


Figure 2-6. Effective number of bits (ENOB) versus normalized capacitor

mismatch in a 12-bit binary weighted SAR ADC [3]

2.3.2. Offset Errors

The offset error in a SAR ADC only causes a linear shift in the transfer

function, but does not cause linearity problems since the error is signal-independent.

There are two sources of offset. The first offset comes from charge injection of the

sampling switches. At the sampling instance, the switch turns off and the charge

stored in the gate-to-channel capacitors is injected onto the top plate of the DAC.

By employing bottom-plate sampling, the amount of charge injected onto the plate

is mostly constant and independent of the input signal, at least to the first-order

estimation. The second source of offset errors in a SAR ADC is the offset of the

comparator, which is also signal-independent for two reasons. First, different from

some other architectures (the flash ADC), only one comparator is used repeatedly

during the conversion phase. Hence, only the offset of that comparator affects the

operation. Second, independent of input voltages, the top plate always returns to

zero at the end of the conversion phase. Therefore, the input common mode voltage

of the comparator at the end of the conversion phase is the same regardless of the

input signal, and thus, the offset voltage is always the same.

18


The residue at the end of the conversion given by Equation 2.8 shows that

the additional terms introduced by offset voltages do not depend on the input

voltage, .

(2.8)

Figure 2-7. Schematic of a SAR ADC with offset errors [3]

2.4. Dynamic Error Sources in SAR ADCs

When analyzing the static error sources, it is assumed that during the SAR

operations, each conversion is given enough time for to completely settle within

the necessary resolution. In reality, conversion errors can occur because the

comparator makes its decision before settles adequately. Since traditional SAR

ADCs uses binary search in which each analog input always maps to one distinct

digital output code, errors made during the conversion process cannot be recovered

at the end of the search process. As a result, it is essential that each comparison is

made correctly during the conversion process to ensure correct operation. The RC

settling of the DAC determines the minimal time that needs to be allocated for each

conversion step and therefore also determines the maximum operation speed of the

ADC. The required time for an N -bit ADC to settle within is given in

Equation 2.12, where is the total resistance of the switches and

is the total capacitance of the DAC. To improve speed of SAR ADCs, small

and should be used in the design.

19


(2.9)

( ) (2.10)

As in defined specification in chapter 1, the sampling rate of SAR ADC in

this work is very low, only 200ks/s, therefore the dynamic error will not affect the

performance of target SAR ADC.

20


21

21 Redundancy SAR ADCs

Chapter 3

Redundancy SAR ADCs

In chapter 2, the operation as well as the structure of a traditional binary weighted

SAR ADC is discussed. Even though it has many architectural advantages, such as

its efficiency in terms of conversion steps, energy efficiency, small chip size,

amenability to digital scaling, and ease of implementation, its resolution and speed

are still limited by a few key design challenges that need to be resolved. Since the

target designed SAR ADC has the sampling frequency very low, only 100ksps, only

capacitor mismatches but not the incomplete reference voltage settling due to high

switching activities is the main linearity and performance limiting factors.

In this chapter, we introduce and analyze the redundancy algorithm in SAR

ADCs and background digital calibration to see how it can help mitigate the

limitation discussed previously. The chapter is begin by giving a conceptual

overview of SAR redundancy and discussed its benefits in terms of achievable

resolution over the traditional binary search algorithm. It will be shown that having

redundant bits provides the extra leverage during the search process so that

conversion errors in the earlier steps can be corrected later and redundancy can

provide the necessary digital calibratability to calibrate out the mismatches in the

capacitor array. The expected random mismatches within the capacitors determine

the amount of redundancy that is necessary to cover this variation. The relationship

between the two parameters is analyzed.

3.1. Redundancy Overview

As described in Chapter 2, in a binary search process, no conversion errors

can be tolerated because for every analog input value, there is a unique

corresponding digital output code. Once a decision error is made, due to its one-to-

22


one mapping property, the ADC cannot recover and produce the correct output

codes. This is shown clearer in Figure 3-1. In the plot, the decision levels, search

range, and search sequence for a 4-bit binary-weighted SAR ADC are highlighted.

The x-axis indicates the sequences of binary search and the y -axis shows the full

search range. In the plot, since none of the ranges within the same search cycle

overlaps, once a range is eliminated during the searching process, the range is

dropped from the search procedure and it will never be reconsidered again. This

confirms the previous conclusion that errors made during the conversion process

cannot be corrected in a binary search.

Figure 3-1: Binary search algorithm without redundancy. The search step sizes

in this example are binary weighted with values equal to 8, 4, 2 and 1 [3]

Although the binary search presented in Figure 3-1 has no error tolerance

capability, it suggests that if the search ranges within the same cycle do overlap, the

already dropped search range can potentially be recovered to produce the correct

digital output. To create overlapped search ranges, a less than radix-2 (sub-radix-2)

search is needed. Essentially, a sub-radix-2 search needs more than N steps to

convert an analog input into a N-bit digital output. Even though this search

23


algorithm is less efficient in terms of the number of steps required to reach a certain

resolution, it provides room for the necessary error tolerances to boost the

robustness of the overall operation. The two search algorithms is compared in

Figure 3-2. Here, s(i)'s represent the step sizes during the search process. In an N-bit

binary weighted algorithm, there are N steps s(i)'s with binary weighted values

, where i is between 0 and . On the other hand, a redundancy SAR ADC

requires M steps to realize N-bit digital output, where M > N. For example, in

Figure 3-2, the binary case only requires four steps with binary weighted s = [8; 4;

2; 1], while the sub-binary case requires six steps with s = [8; 2; 2; 1; 1; 1] to

achieve the same resolution. The total steps s is 15 in both cases, implying that the

two algorithms have identical search range. The final digital output for an N -bit M

-step ADC can be calculated using Equation 3.1.

( ) , ( ) - ( ) , ( ) -

(3.1)

where is the final digital output expressed in decimals, b[n] is the digital

output bit, N is the effective resolution and M is the total number of steps. In this

example, the extra two steps is added to the original binary search to provide error

tolerance. An example demonstrating this error resilience is given in Figure 3-3.

The left-most plot shows an ideal example where all decisions are made correctly;

the middle plot shows an example where a decision error is made in the rst step and

finally, the right-most plot shows an example in which a decision error is made in

the second step. For = 6.2, each of these above cases gives different digital

output bit sequences: [010010], [100010] and [100010], respectively. Their digital

outputs is calculated by using Equation 3.1 and they all result in the same Dout (=

6) as shown in Equation 3.2, 3.3 and 3.4. This demonstrates that redundancy has the

capability to digitally realize correct oputput code for at least some bit decision

errors.

, - ( ) ( ) ( )

( ) ( ) ( )

(3.2)

24


, - ( ) ( ) ( )

( ) ( ) ( )

(3.3)

, - ( ) ( ) ( )

( ) ( ) ( )

(3.4)

Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4-

step) and a sub-binary search algorithm (4-bit 6-step) [3]

Figure 3-3: Digital error correction using redundancy in SAR ADCs [3]

25


3.1.1. Error tolerance windows for redundancy

The redundancy only provide limited amount of error tolerance for SAR

algorithm. During the conversion process, if the decision errors are too large, even

with redundancy, the errors still cannot be recovered and the digital outputs will be

incorrect. For each conversion step, a range of recoverable analog voltage can be

highlighted around the decision level. This implies that during the transition, if an

analog voltage falls within this range and error is made, the ADC can recover from

the errors if there are no mistakes in the rest of the conversion process. This error

tolerance window is denoted as . For the output bit, (n) can be calculated

according to Equation 3.5.

( ) ( ) ( )

(3.5)

As an example, Figure 3-4 shows a redundant SAR ADC with s = [8; 2; 2; 2; 1].

For the 5th

output bit, the error tolerance window is given by Equation 3.6.

( ) ( ) ( ) ( ) ( ) (3.6)

The formula 3.5 can be intuitively understood as follows. For the output

bit, the next decision level will either move up or down by the step size of s(n-1)

once a decision is made. If erroneous occurs, then the sum of the follow-on step

sizes, s(n-2); s(n-3):; s(1), must be large enough and exceed the value of the

current step size to correct this mistake. That exceeded amount is the tolerance

window for that decision level.

Figure 3-4: Transfer functions for SAR designs with step sizes that are binary,

subradix-2 and super-radix-2 weighted [3]

26


Figure 3-5: Highlighted error tolerance windows ( ) for a sub-binary search SAR ADC [3]

3.1.2. Dynamic Threshold Comparison

Error-tolerance window

Input voltage

Input voltage

Error-tolerance window

temporary shift

Middle range Middle range

Figure 3-6: Illustration of Dynamic Threshold Comparison technique

From previous section, it can be seen that if an input voltage falls inside

error-tolerance window, the decision error can be corrected in later steps. To further

improve the error resilience of SAR ADC, Dynamic Threshold Comparison

technique [4] will be utilized. The main idea of this technique is if the input voltage

sits outside the error-tolerance window, it should be temporary shift into this

window to exploit the error resilience of the redundancy. Therefore, this technique

27


provides extra error tolerance capability for the ADC with the input voltage outside

error window. In other words, the range of window is enlarged when DTC

technique is applied. Note that by utilized DTC technique, the error-tolerance

window does not increase unlimited, the amount of range extension will depend on

the way of implementation of this technique in SAR ADC.

3.2. Digital calibratability

The previous section discussed about how dynamic conversion error can be

resolved by using redundancy. In chapter 2, it can be seen that the dominant error

source of the target ADC is capacitors mismatches, which lead to mismatches in the

searching steps, s(n). In the section, the condition of digital calibratability in the

presence of static mismatches in capacitors will be explored.

3.2.1. Condition of digital calibratability

Figure 3-5 shown three transfer functions which represent 3 different cases.

Figure 3-5 (a) shows the ideal case of transfer function in which the analog input is

linearly mapped to digital output code. Figure 3-5 (b) shows the case that the MSB

step size smaller than its nominal value, which is referred as the sub-radix-2 search

and Figure 3-5 (c) has the MSB step size larger than its nominal value, which is

referred as the super-radix-2 search. In a super-radix-2 search, a horizontal

misalignment (missing level) appears in the transfer function. In this case, the

analog information is lost since multiple analog inputs are mapped to the same

digital output code and the errors cannot be corrected digitally. In contrast, in a sub-

radix-2 search, vertical misalignments (missing codes) appear in the transfer

function. In this case, more than one digital output codes could potentially be

mapped to one analog input while some of the digital output codes never show up

during normal operations. In contrast to previous case, since the analog information

is not lost, the error is digitally correctable in this case. The large vertical jump is

embodied in the redundant search algorithm. By designing step size s(N)

intentionally smaller than the sum of the remaining s(n), digitally correctable codes

can be created. By extending this idea into every search step in the sub-binary

search, redundancy can be built into all decision levels

28


( ) ( )

(3.7)

where i = 1; 2;; N . There will be no missing levels and all static errors are

digitally correctable as long as all decision levels satisfy Inequality 3.7.

3.1.2.2. Amount of redundancy

As discussed in the previous discussion, whenever Inequality 3.7 is satisfied,

redundancy is built into the search algorithm. To achieve this inequality, one simple

way is choosing a fixed radix that is less than 2. Even though the design is

originally built to satisfy Equation 3.7, the added variation in the search steps

resulted from random manufacturing variation of capacitors can break this

relationship and create missing levels that are not digitally correctable. In this

section, a relationship that determines the amount of redundancy needed to

guarantee Inequality 3.7 with respect to different amounts of DAC capacitance

variation will be established.

Figure 3-7: Effective number of bits (N) versus number of steps (M) for

different radices () [3]

29


When the ADC is designed with a fixed radix, , the following relationship

is obtained

( )

( ) (3.8)

where i = M-1; M-2;; 1. The effective number of bits, N, can be calculated using

Equation 3.9

( )

(3.9)

where is the sum of all the step sizes, N is the effective number of bits and M is

the total number of conversion steps. Figure 3-7 shows that although converters

with smaller radix, , require more steps to achieve the same resolution as the

converters with larger radix, they are more resilient against both dynamic and static

conversion errors.

3.1.2.3. Radix and number of steps

In order to incorporate redundancy to provide the capability to digitally

calibrate for static random mismatches, Inequality 3.7 must be satisfied at all times

even with the presence of variation. Due to manufacturing variation, random

variation in capacitor size is unavoidable. Since the step sizes (s(M ); s(M-1);;

s(0)) are proportional to the capacitor sizes ( ; ;; ), Equation 3.7 can be

re-written as follows

(3.10)

where is the desired (or designed) relationship between the

capacitances in the DAC. Manufacturing variation in 's can break this

relationship. In this section, the appropriate radix number and the number of steps

such that Inequality 3.10 is satisfied with high probability, even in the face of

variation will be found.

A plot of maximum radix and the minimum number of conversion steps

needed for a given amount of capacitor mismatches in a 12-bit ADC is shown in

Figure 3-8 [3]. From this figure, it can be seen that when the variance of capacitor

30


is 0%, = 2.0 and M = 12; this corresponds to the classic non-redundant binary

search ADC case. On the other hand, in this implementation, it is estimated that is

about 7%, then = 1.86 and M = 14 are obtained.

Figure 3-8: The maximum radix and the minimum number of conversion steps M versus the standard deviation of the unit capacitor, in order to achieve

digital calibratability in a 12-bit ADC [3]

31


32

32 Digital Background Calibration of SAR ADCs

Chapter 4

Digital Background Calibration of SAR

ADCs

In Chapter 3, the redundancy algorithm in SAR ADC was introduced. If

implemented correctly, redundancy can provide error tolerance for the ADC during

the conversion process. To ensure digital calibratability in the presence of

capacitors mismatches, some requirements on redundancy are needed. The

requirements can be expressed in a simple relationship between the maximum radix

number, the minimum total number of conversion steps and the expected

manufacturing random variance of capacitors. From this relationship, the total

number of steps and the radix number for the target ADC were chosen.

In this chapter, to take another step towards designing higher resolution SAR

converters, a digital background calibration schemes that can utilize the redundant

information to digitally remove the nonlinearity is provided.

4.2. Overview of digital calibration in SAR ADC

Without trimming or calibration, static nonlinearities usually limit the

resolution of SAR ADC from going above 8-10 bits [10]. To alleviate effect of

nonlinearities on SAR performance, a lot of new calibration techniques to achieve

designs with higher accuracy have developed. For example, Li et al. in [11] came up

with a ratio-independent algorithmic technique, and Song et al. in [12] proposed a

capacitor error averaging technique to achieve exact multiplication by a factor of

two regardless of capacitor mismatch error in a pipelined ADC. The most common

of these techniques [11-16] is that they use analog components in the signal path to

remove static nonlinearity. Although they are quite effective in removing static

33


nonlinearities in the design, these techniques typically degrade conversion speed

and add circuit noise. The circuit noise based FoM degradation is roughly 12X and

9X in [11] and [12], respectively.

Besides, digital calibration techniques, which can realize the benefit of

technology scaling, have also been developed. They can be divided into two groups:

foreground calibration and background calibration. In foreground calibration, the

calibration is done during a calibration phase at startup and nonlinearity is measured

by driving the inputs with specific calibration signals to extract the mismatch

information. For example, Lee et al. in [17] developed a self-calibrated capacitor

array in a SAR ADC. The ratio errors of the capacitors will be extracted

sequentially from the MSB capacitor to the LSB capacitor during calibration. The

mismatch data stored in a RAM is used to correct matching errors of the capacitor

array during the normal operation. Other calibration schemes extract nonlinearities

by using statistically-based methods [18, 19]. These calibration schemes interrupt

the normal operation of the ADC since they require collection of measurement data

at the beginning of the operation. To minimize the effect, these calibration schemes

are typical to run during manufacturing or at startup, so they cannot track parameter

drifts.

In contrast, digital background calibration does not interrupt the normal

conversion process since it runs transparently in the background. A common

approach is to inject a known calibration signal, , onto the signal path [4], [20-

23]. With an ideal linear transfer function, an injected calibration signal will

cause a constant shift of (the corresponding digitized output of ) which is

independent of the input signals at the output. Therefore, when is subtracted

from the final digitized output, the injected signal should have no correlation with

the output signal. The calibration engine is designed to null this correlation by

adjusting the calibration parameters. Using this approach, the signal range and the

over-range protection is reduced since the signal path must accommodate the

addition of the calibration signal.

Rather than tampering with the input signal path, another approaches

estimate the static errors by using the input signal itself instead of a calibration

34


signal [24-26]. Adaptive equalization techniques are used to resolve nonlinearity

problems for pipelined and SAR ADCs in [24,25] and [26], respectively. In these

techniques, an accurate reference ADC is typically used to estimate and correct the

errors. Even though the reference ADC may run at a slower speed compared with

the core ADCs, these techniques will increase power consumption or reduce in

conversion speed.

In this work, the perturbation based digital background calibration [4] and

[27] is used because of its simplicity and effectiveness as demonstrated in [4]. This

calibration algorithm will be discussed carefully in the next parts.

4.1. Superposition Principle

The superposition principle of a linear system is the soul of the perturbation-

based digital calibration. In Figure 4-1, the SAR ADC is represented by an

operation Q(X), which maps analog samples to output digital codes. The ADC

respectively maps its input and (the perturbation signal) to the output Q( )

and Q( ). Assuming ideal quantization, the Q(X) is a linear operation. Therefore,

using the superposition principle

( ) ( ) ( ) (4.1)

Figure 4-1. The superposition property of linear system [27]

Denote ( ) as . Then the Equation (4.1) is rewritten as ( ) ( ) (4.2)

Equation (4.2) implies that the correct quantization value of input voltage

can be obtained by subtracting the perturbation signal in digital domain in a linear

A/D conversion. Equation (4.2) can also be intuitively explained as follow: adding

and horizontally shifts the original transfer curve as in Figure 4-2(a),

while subtracting the output codes by and in Figure 4-2(b) vertically

35


shifts the transfer curve accordingly. If transfer curve is linear and all bit weights

are optimal, the two perturbed transfer curves line up with the original one,

assuming . In reality, is adapted so the injected can be precisely

removed in digital domain.

However, in a nonlinear case the superposition property does not hold. For

example, considering the MSB bit weight error where the transfer curve distorts at

the transition from the digital code 0111 to the digital code 1000 and assuming

the other bit weights are optimal. In Figure 4-3(a) and (b), the same horizontal and

vertical perturbations respectively as Figure 4-2(a) and (b) is shown. The two

perturbed transfer curves in Figure 4-3(b) form a window with a horizontal size of

2 instead of aligning with the original one in this case. Each analog input can be

digitized twice using both of the dashed and dash dotted curves in Figure 4-3(a) and

(b) respectively. Therefore, when an analog sample falls in the window, two

different digital codes are obtained. The difference between them gives a chance to

observe the bit weight error. By adjusting the bit weights to obtain optimal ones, the

error (window) diminishes and the transfer curve is linearized. The superposition

property of the linear transfer curve holds again. A large results in a wide

window, which provides a better opportunity to observe the error.

In general, every bit weight derails from its nominal bit weight so the

transfer curve is distorted at various locations, but the perturbation detects all of

them in the same mechanism as the MSB example above. [27]

4.2. Perturbation-Based Calibration Algorithm

The perturbation-based digital calibration for a SAR ADC with N conversion

steps can be described as follow:

A single SAR ADC digitizes each analog sample twice. However, the two

quantizations are perturbed by analog offsets of and respectively, and

then two N-bit raw codes, and , accordingly, is given at the output. With the

same bit weights, W={ }, i=0, , N-1, (these bit weights represent conversion

step in chapter 3) the weighted sums and are obtained by

36


Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights).

[27]

Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit

weight only). [27]

( ) , -

(4.3)

( ) , -

(4.4)

37


where is the quantized input-referred offset, and the ratio between the

capacitor ( ) and the total capacitance ( ) defines the bit weight, .

Equation (4.3) and (4.4) calculate the weighted sums of all bits of

and . With digitally subtracted, the error between the two conversions is

obtained by Equation (4.5),

(4.5)

where and are quantized versions of and . Similarly the

desired value of is

( ) ( ) (4.6)

where Q() is ideal quantization. Assuming optimal bit weights are learnt, Equation

(4.1) holds. Putting Equation (4.1) and into Equation (4.6), a zero error is

obtained. The superposition property of the linear transfer curve shown in Figure 3-

9 holds in this case. Otherwise, the non-zero error indicates the nonlinearity in the

transfer curve, as depicted in Figure 3-10. Plugging Equations (4.3) and (4.4) into

Equation (4.5) gives,

[ ( )] , -

(4.7)

Equation (4.7) is in the form of a generalized code-domain linear equalizer. Then, to

drive that to 0, an LMS algorithm is applied by adjusting the N individual bit

weights and the simultaneously using Equation (4.8) and Equation (4.9):

, - , - , -( , - , -)

(4.8)

, - , - , - (4.9)

where and are the step sizes of the update equations. Eventually, the

calibration engine forces the error to zero in a least-mean-square sense. In steady

state, all optimal bit weights are learnt, the mean of and ( cancelled in

averaging) yields the correct digital output of . In the double conversion both the

quantization noise and the comparator noise are reduced by 3 dB.

38


The perturbation based calibration only requires an analog offset injection.

Compare to a highly linear reference ADC required by the equalization-based

digital calibration [17, 24, 25], [28-30], the hardware overhead is negligible.

Although the dynamic range of the ADC is reduced by analog offset injection, it is

typically tiny compared to the full-scale range. Unlike the splitting-based calibration

where the generation of multiple decision paths and double routing are involved

[31], by adding only a pair of injection capacitors, this calibration requires

significantly lower circuitry complexity and less design effort. The deterministic

character and the zero-error-forcing nature of this calibration result in a much

shorter convergence time than the correlation-based ones [22, 32]. Although the

calibration reduces the conversion speed by half, the sampling rate of target ADC is

quite low, so this does not affect much to the ADC performance.

39


40

40 Design and Implementation of Redundancy SAR ADC with Digital Background

Calibration

Chapter 5

Design and Implementation of

Redundancy SAR ADC with Digital

Background Calibration

In Chapter 4, the perturbation based calibration algorithm that is able to utilize the

redundancy information to digitally correct output code was introduced. The

superposition principle in which the calibration is based on was explained first.

Then the calibration algorithm was described in details. From that, its advantages

and disadvantages compare to other algorithms also was discussed.

In this chapter, the real implementation of a redundant SAR ADC is

described. In the first part, the implementation at the architectural level will be

focused on. All the circuit blocks are combined and how all these blocks work

together is analyzed carefully. The next part of the chapter describes the design at

the circuit level with discussion of several new contributions. Firstly, DAC

switching scheme that is able to achieve higher energy efficiency than conventional

switching schemes will be presented. Secondly, some circuit blocks such as

bootstrapped switch, comparator, preamplifier will be described. A new way to

implement the dynamic threshold comparison which requires less area is proposed

in this part. And the last once, an enhanced digital calibration circuit which require

less hardware resource compare to [4] is introduced.

5.1. Architecture

The architecture of overall ADC is shown in Figure 5-1. Its operation can be

described as follow. A single SAR ADC digitizes each analog sample twice, with

41


Calibration

two analog offsets, and , resulting in two 14-bit raw codes, and ,

respectively. Depend on values of and , the calibration engine will calculate

output d and update the new value of bit weights * +.

SAR ADC

+a, -a

VinD+, D-

CalibrationEngine d

Figure 5-1: The architecture of overall ADC

5.1.1. SAR ADC architecture

Figure 5-2 shows the architecture of SAR ADC. Its operation can be

described as follow. At first, the ADC samples the input signal on the top plates via

bootstrapped switches, which increases the settling speed and input bandwidth. At

the same time, the bottom plates of the capacitors are reset to . Next, after the

ADC turns off the bootstrapped switches, a perturbation signal is added to the

input by connecting capacitor to the ground. After that, the comparator performs

the first comparison without switching any capacitor. Depend on the comparator

output, the largest capacitor on the higher voltage potential side is switched to

ground while the other one (on the lower side) remains unchanged. Then, the

comparator continues comparing and the switch or will be closed. The

procedure is repeated until the LSB is decided and the raw 14 bit of is obtained.

After that, all capacitors are reset to . The process to generate is begun. The

all procedure above is repeated except the perturbation is added to the input by

connecting capacitor to the ground.

42


Calibration

SAR Control Logic

V

ref

V i+Vi-

Vref

Bootstrapped switch

C0C0C1C2C7C 10C 11C 12

C0C0C1C2C7C 10C 11C 12 C tn

C tp

preamplifier

S12n S0nS7nS10n S1nS2nS11n

S12p S0pS7pS10p S1pS2pS11p

Signal injection

Dynamic threshold

comparison

clk

V+

V-

Figure 5-2: SAR ADC architecture

5.1.2. Calibration architecture

The block diagram of the calibration engine is shown in Figure 5-3. The

inner product block is used to calculate the weighted sum from 14-bit raw code

. It is also utilized to calculate the difference between and (from 14-bit

raw code and ). From this difference and value of , we can obtain all other

important parameter such as output code d, bit weights W as in Equation (3.23)

and (3.24). This way of implementation will save a lot of hardware resource as well

as power compare to the implementation in [4] (1 inner product block, 1 subtractor

).

SAR ADC

LMS+a, -a

Vin

dd

error

2dw

+

d+ d --2

+

-

d+ d --+

-

Figure 5-3: The block diagram of the perturbation-based background digital

calibration.

43


Calibration

5.2. Key circuit building block

5.2.1. Capacitive DAC Design

5.2.1.1. Monotonic Capacitor DAC Switching Operation

In this part, Monotonic Capacitor DAC Switching algorithm will be

described. Although the implemented Capacitive DAC uses sub-radix-2 monotonic

switching algorithm, we will introduce this algorithm with binary weighted

capacitor for easy to understand and compare to other switching algorithms.

Conventional switching algorithm

In a SAR ADC, the DAC is used for 2 two purposes: sampling the input

voltage and generating error residues between the input and the current digital

estimate. The conventional SAR switching algorithm for a 3-bit ADC in a fully

differential implementation is shown in Figure 5-4; the top-plate waveform for a 6-

bit ADC using the conventional switching algorithm is shown in Figure 5-5. Even

though this switching algorithm is able to produce the correct logic operations, it

does not move the charges among capacitors efficiently, wasting energy during

operation.

The energy consumption of each transition in conventional switching

algorithm is shown in Figure 5-4. During the first phase, the differential inputs are

sampled onto the upper and lower arrays of the DAC. After that, they are

disconnected from the DAC at the end of sampling phase. The DAC is configured

by charging the MSB capacitor to and the remaining capacitors to ground for

the top array and, the opposite is done for the bottom array. The total energy

consumption for this operation is . The first output bit is produced by

comparing the voltage on the plus and minus nodes of the comparator. Then the

switching scheme either takes the up or down transitions depending on whether

the bit is 0 or 1, respectively. The procedure is repeated until the LSB is

decided.

44


Calibration

Figure 5-4: Conventional SAR switching algorithm, showing energy

consumption related to capacitor switching transitions [3]

Figure 5-5: The top-plate waveform when using the conventional switching

algorithm [3]

Observing the first two transitions, it can be seen that energy efficiency can

be improved. In the above example, the sign bit of the input signal is generated by

comparing the magnitude of and in the first transition. As shown in

45


Calibration

Figure 5-4, depending on the values of the input signal, there are a total of four

potential transition paths that the SAR algorithm can take. Assume that the upper

most path is taken, the first step makes up more than 75% of the total energy

consumption to just generate the sign bit. Intuitively, without consuming any

energy, the sign bit can be generated by directly comparing and after

sampling. It implies that simpler algorithm can be developed to avoid this energy

loss.

The average switching energy of an n-bit conventional switching algorithm

can be derived as follows:

( )

(5.1)

Monotonic Switching Algorithm

Liu et al. in [33] proposed a monotonic switching algorithm. The ADC

samples the input signal on the top plates while the bottom plates of the capacitors

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Final Thesis - ADC