Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage

CSE 577 Spring 2011

A i i CAnalog-to-Digital Converters

Jaehyun Lim, Kyusun Choi

D t t f C t S i d E i iDepartment of Computer Science and EngineeringThe Pennsylvania State University

Mixed Signal Chip Design Lab

ADC Glossary

DNL (differential nonlinearity)- measure of the maximum deviation from the ideal

step size of 1 LSB


ADC Glossary

INL (integral nonlinearity)- deviation of the entire transfer function from the

ideal function


ADC Glossary

Offset Error- difference between the ideal LSB transition to the

actual transition point


ADC Glossary

Gain Error- how well the slope of the actual transfer function

matches the slope of the ideal transfer function


ADC Glossary

Resolutionf- number of discrete values it can produce

Monotonic- digital output code always increases as the ADCdigital output code always increases as the ADC

analog input increasesFull scale

lt ADC t- voltage range ADC can acceptAliasing- due to unwanted signals beyond the Nyquist limitdue to unwanted signals beyond the Nyquist limit- to prevent, all undesired signals must be filtered


ADC Glossary

SINAD (signal-to-noise and distortion)RMS l f th t t i l t th RMS l- RMS value of the output signal to the RMS value of all of the other spectral components below half the clock frequency

ENOB (effective number of bits)- dynamic performance of an ADC at a specificdynamic performance of an ADC at a specific

input frequency and sampling rate

761SINAD02.6

76.1−=

SINADENOB


High Speed ADC Architecture

Flash ADC

- highest speed

large # of comparators- large # of comparators

- large size

- large power consumption

8 bit i l ti- 8-bit maximum resolution



Two-Step Flash ADC

- SHA

- D/A converter

- subtractor

- coarse flash ADC (MSB)coarse flash ADC (MSB)

- find flash ADC (LSB)

- reduce # of comparatorsreduce # of comparators

2N-1 2(2N/2-1)



Pipelined ADC

- multi-stage conversion

hi h d- high speed

- acceptable power

- each stage has SHA, ADC, DAC, subtractor, Amp

- different conversion step concurrently



Folding ADC

- no SHA (flash)

- reduce # of comparatorsreduce # of comparators

(two step flash)

ll hi h d- small area, high speed

- rounding problem



Time-Interleaved ADC

- multiple ADCs in parallel high speed

- offset/gain mismatchg

- phase skew


And More ADC Architectures

Algorithmic ADC

- low power, small size, slow

Integrating-Type ADCg g yp

- high accuracy, simple architecture, very slow

S i A i ti ADCSuccessive Approximation ADC

R&C / C&R Type ADC

Interpolating ADC


Design Consideration – Flash ADC

Large Input Capacitance• parallel structure of 2N-1 comparators• limits speed performance• large size buffer

Bubble / Sparkle• no SHA, comparator mismatch…• error in thermometer code• error in thermometer code• solution : 3-input NAND



Metastability• input to ADC ≈comparator reference• indeterminate output error• solution : latch pipelining (extra gain)

gray encoding (no signal split)



Clock Distribution and Timing• clock travels long distance on a large ADC chip• different delay, different loading

Kickback NoiseKickback Noise• disturbs reference


Design Consideration – Two-Step Flash ADC

Subtractor Gain• without gain stage

– output of subtractor = 1-LSB of coarse ADC– difficult comparator design

(offset < 1-LSB of fine ADC)• with gain stage

delay– delay– mismatch between subtractor output and fine

ADC input full scalepmissing code / nonmonotonicity


Design Consideration – Two-Step Flash ADC

Nonlinearity

residue residue

V

residue

V

residue

including errors- gain mismatch

DNL INL

SHA

Vin Vin- DNL, INL- offset- ...

SHAanaloginput

level sensed by subtractor

t

level digitized by coarse ADC

level sensed by subtractor

t1 t2

ΔV


t1 t2

Design Consideration – Pipelined Flash ADC

MDAC (Multiplying D/A Converter)- performs subtractor, gain amplifier, S/H, and DAC



MDAC Operation removes offset

Vx

(2N-1)·C·Vin + C·VinQi =

2N C V= 2N·C·Vin



MDAC Operation

Qf = 2N·C·DVref + C·VQf 2 C DVref + C Vo

from Qin=Qf, Vo = 2N(Vin-DVref)


Design Consideration – Folding ADC

Rounding Problem- only linear at zero-crossings

limits resolution to ~10 bitslimits resolution to ~10 bits


Design Consideration – Folding ADC

Multiple Folds


Two-Step Flash ADC Implementation

SHA

4-bit Coarse ADC

3-bit Fine ADC

Resistor-String DAC

Voltage Subtractor

Amplifier

Registers



Coarse ADC

Fat-Tree EncoderBubble Correction


Bubble Correction


Coarse ADC



Resistor-String DAC

• voltage scaling DAC

• simple

• fast

• small (under 8-bit)

• resistor mismatchingresistor mismatching



Resistor-String DAC

00011111



SHA

input

outputoutput



Voltage Subtractor

V2

V1 8 x (V1-V2)



Things To Be Done

• voltage subtractor and gain amplifiervoltage subtractor and gain amplifier

- input voltage range for the subtractor

- output offset

- proper gain setting (input range of fine ADC)

• 3-bit fine ADC

id ti l t th 4 bit ADC- identical to the 4-bit coarse ADC


Documents

Analog-to-Dii Cigital Converterskxc104/class/cse577/11s/lec/S08ADC.pdfAnalog-to-Dii Cigital Converters Jaehyun Lim, Kyusun Choi ... High Speed ADC Architecture Pipelined ADC-multi-stage