pipeline adc thesis

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Design Techniques forUltra-Low-Voltage andUltra-Low-Power Pipelined ADCs

Junhua Shen

Submitted in partialfulfillmentof therequirements for the degree of

Doctor of Philosophyin the Graduate School of Arts and Sciences

COLUMBIA UNIVERSITY2010


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UMI Number: 3420870

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2010

Junhua Shen

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AbstractDesign Techniques for Ultra-Low-Voltage and Ultra-Low-Power Pipelined AD Cs

Junhua Shen

This thesis addresses two important aspects of pipelined analog-to-digital converter(ADC) design . The first one is regarding a pipelined A DC w ith ultra-low supply voltage.As CM OS technology advances, lower supply voltages are expected in the nearfuture.Weexplore its design feasibility and implications. The second aspect is related to minimizingthe total power consum ption of th e pipelined AD C. In particular the power associated w iththe reference voltage b uffer is ad dressed.

A 0.5V 8bit pipelined ADC operating at lOMS/s is proposed. The AD C uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting.The switch OFF leakage in the sampling circuit is suppressed using a cascaded samplingtechnique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by usinga coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-AD C and signal path sampling circuit. A 0.5V operational transconductance amplifier(OTA) is presented that provides interstage amplification with an 8bit performance for thepipelined AD C operating at lO MS /s. The prototype chip has eight identical stages and stagescaling w as not used. It consumes 2.4mW fo r lOMS/s operation at 0.5V supply voltage.


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Measured peak SNDR is48.ldB and peak SFDR is 57.2dB for afull-scalesinusoidal input.Maximal integral nonlinearity (INL) and differential nonlinearity (DNL) are 1.12LSB/-1.19LSB and 0.55LSB /-0.48LS B, respectively. The prototype achieves a figure-of-me rit(FOM) of 1.15pJ/Conv. Step. It was fabricated on a standard 90nm CMO S process andmeasures 1.2mm x 1,2mm.

A low power stage architecture for a IV 8bit lOOMS/s pipelined ADC using current-charge-pum p multiplying digital-to-ana log conversion (MDAC) circuit is presented. Byavoiding the use of OTAs for the interstage amplification and eliminating power hungrybuffers for the reference voltages, the proposed current-charge-pump pipelined AD C con-sumes much less power and thus achieves very high operation efficiency. Two versionsof inverter based comp arators are employed in the signal and sub-ADC paths. The de-sign involves minimu m an alog circuitry and is digital dominant. It consumes 1.39mW forlOOMS/s operation at IV supply voltage. Measured peak SNDR and SFDR are 37.1dB and46.7dB respectively, with a -ldB FS sinusoidal input at Nyquistfrequency.Maximum INLand DNL are 2LSB/-2.3LSB and 1LSB/-0.8LSB, respectively. T his concept-proving pro-totype achieves an FOM of 237fJ/Conv. Step while largely alleviating the requirement ofreference voltagebuffers.The core circuit occupies 0.04 4mm2. The design was fabricatedon a standard 90nm CM OS process using regular V t devices.


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Contents

List of Figures iii

List of Tables xii

1 Introduction 11.1 Overview 11.2 Mo tivations 151.3 Contribution s 161.4 Thesis Organization 17

2 Ultra-Low-Voltage Pipelined AD C 192.1 Introduc tion 19

2.1.1 Challenges 192.1.2 Solutions 212.1.3 Chapter Organization 22

2.2 Ultra-Low-Voltage Pipelined ADC System Design 22i


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2.2.1 Top-Level and Stage Design Considerations 222.2.2 MDAC Design Considerations 272.2.3 Auxiliary S/H for Sub-ADC Path 362.2.4 Reverse Short Channel Effect for Reduced V T 41

2.3 Circuit Level Design Considerations 432.3.1 Cascaded Sampling Technique and Switches 432.3.2 0.5V OTA Design 492.3.3 Com parator 532.3.4 Non-Ov erlapping Clock Generator 54

2.4 Measuremen t Results 542.5 Idea for Future Improvement 64

2.5.1 Switch Gate-Bootstrapping 642.6 Summ ary 69

3 Current-Charge-Pum p Ultra-Low-Power Pipelined ADC 713.1 Introduction 71

3.1.1 Challenges 713.1.2 Solutions 723.1.3 Chapter Organization 74

3.2 Review of Ultra-Low-Pow er Pipelined ADC Architectures 743.3 Reference Bu ffer Design Review and Its Challenges 80

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3.4 Current-Charge-Pump Pipelined ADC System Design 943.4.1 Current-Charge-Pump Residue Amplification 963.4.2 Current-Charge-Pump Pipelined ADC Stage 993.4.3 Architecture of the Current-Charge-Pump Pipelined ADC 102

3.5 Circuit Level Design Considerations 1043.5.1 Signal-Path Com parator with Signal-Independent Delay 1053.5.2 Sub-ADC Path Com parator with Offset Calibration 1073.5.3 Four-Phase Non-Overlapping Clock Generator 109

3.6 Noise and Nonlinearity of Current-Charge-Pump MDAC I l l3.6.1 Noise of Current-Charge-Pump MDAC I l l3.6.2 Nonlinearity of Current-Charge-Pump MDAC 114

3.7 Measurem ent Results 1163.8 Ideas for Future Improvement 125

3.8.1 Fully Differential Design 1253.8.2 Alternative MDACs Avoiding Reference Buffers 128

3.9 Summary 133

4 Conclusions and Future Work 1354.1 Conclusions 1354.2 Ideas for Future Work 137

A OTA Settling Consideration at Ultra Low Voltage 152iii


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List of Figures1.1 Block diagram of the first two stages of a pipelined AD C 51.2 (a) Num ber of bits versus sampling frequency for different types of AD Cs;

(b) Power consumption versus sampling frequency for different types ofADCs 6

1.3 Com plete diagram of a pipelined AD C 71.4 Trend of supply VD D and technology node versus year, (a) Analog and

RF; (b) digital high perform ance 91.5 Trend of supply VD D and techn ology node versus year, (a) digital low

standby power; (b) digital low operation power. 10

2.1 Block diagram of the pipeline AD C prototype chip 232.2 (a) Single-ended version of one pipeline stage; (b) non-overlapping clock

signals and their advanced (4>\a) 02a) and delayed (cpid, 2d) ver-sions used to minimize charge injection, clock feedthrough and to ensureaccurate sampling 24

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2.3 A standard fully differential MDAC for a 1.5bit stage, the non-overlappingsampling clock phase CKSand the amplification phase C Kaare also shown.Switches d 0-d 2 are controlled by the sub-ADC output during CK a . Centerswitch d 0 is used to replace the reference voltage Vcm for both paths 26

2.4 Noise sources in a standard MDAC for a 1.5bit stage, during the residueamplification phase 31

2.5 (a) Block diagram of the first stage of a conventional pipeline ADC witha dedicated front-end sample and hold (S/H) and preamplifier (A) in thesub-ADC and (b) the associated operation sequence 37

2.6 (a) Block diagram of the proposed pipeline stage with auxiliary sample andhold circuit and (b) the associated operation sequence 38

2.7 Simulation showing the decrease of the threshold voltage, V t , for increas-ing device lengths, a.k.a. the Reverse Short Channel Effect (RSCE), for2//m wide NM OS transistors in different CMO S technologies 41

2.8 (a) Standard sample-and -hold circuit (all transistors are sized as 12/iin/0.36^mand Ci is lpF ); and (b) associated node waveforms 44

2.9 (a) Proposed cascaded sample-and-hold circuit to combat switch OFF leak-age (all transistors are sized as 12//m/0.36 /um, Ci is lpF and C 2 0.25pF)

and (b) associated node waveforms 45

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2.10 Simulation results for the sample-and-hold circuits in Fig. 2.8, 2.9 withrail-to-rail input showing the significant reduction of the effect of leakageduring the hold time for the cascaded sample and hold compared to stan-dard sample and hold 46

2.11 Schematic of the 0.5 V operational transconductanceamplifier.Device sizesshown in Table 2.1, The bodies of all transistors are shorted to their sourceterminals, except for the bodies of M 8A and M8B 49

2.12 Biasing loops using an on-chip replica OTA to generate the bias voltagesCM 1, CM 2 and VBB for the OTA in Fig. 2.11 50

2.13 A standard dynamic latch based fully differential difference comparator. . . 532.14 (a) Non -overlapp ing clock generator, the advanced and delayed clock phases

are achieved by inserting NMOS M x-M 4; (b) Two clock phases with ad-vanced and delayed versions from the clock generator. 55

2.15 Die photo (left) and layout plot (right) 562.16 Measured output spectrum at lOMS/s with a full-scale 109kHz sinewave

input using a 16384-point FFT. 572.17 Measured SNDR, SN R, SFDR at lOMS/s for a full-scale input sinewave

with frequencies varying from 101kHz to 4.9MHz 58

2.18 Measured SN DR, SNR , and SFDR for a full-scale input sinewave at 49kHzwith sampling frequencies varying from 100kHz to 10MHz 59

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2.19 Measured SNDR, SNR, and SFDR at lOMS/s with a 109kHz sinewaveinput of varying amplitude from -45dBFS to OdBFS 60

2.20 Measured DN L and INL 612.21 Su b-lV ADC Perform ance Comparison; SNDR and signal bandwidth are

shown next to reference number. 622.22 Transconductance versus input voltage for both transmission gate and boot-

strapped gate switches 652.23 A standard implementation of the gate bootstrapped switching circuit. . . . 662.24 A modified version of the gate bootstrapped circuit 672.25 The operating sequence of the circuit in Fig. 2.24 67

3.1 Power breakdown of a typical pipelined ADC, reference buffer consumesa significant portion of the total power. 73

3.2 Basic operation of the dynam ic source followeramplifier. 753.3 Half circuit pseudo differential stage implementation 753.4 Com parator based switched capacitor circuit, a comparator and a current

source is adopted to replace the OTA in a traditional implementation. Out-put voltage is obtained when the comparator virtual ground is detected andthe comparator output toggles 77

3.5 1 bit charge domain pipelined ADC stage 783.6 Capacitive charge-pump based pipelined ADC stage 79

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3.7 A standard MDAC in the am plifying phase, with the reference voltage con-nected to the sampling capacitor. 81

3.8 An MD AC with a dedicated referenc e capacitor C r ef, during the amplifyingphase 81

3.9 A fully differential opam p with resistive feedback to generate the positiveand negative referen ce voltage 83

3.10 A reference buffer with the same form of a standard low dropout linearregulator. 84

3.11 Mo del for the referencebufferdriving the sam pling capacitor in the MD AC,the buff er has a finite R 0a nd a bypass capacitor Cb is added. Phase1is thesamp ling phase and phase 2 is the am plifying phase 84

3.12 A referen ce buffe r with source followe r output stage 903.13 A referen ce buffer using resistive feedback and source follower output stage. 923.14 A referen ce buffe r with open loop source follower driving stage 933.15 Standard stage implementation of a pipelined ADC. High performance

OTA and reference buffer are used to achieve high accuracy, but at thecost of high powe r consum ption 94

3.16 Proposed current-charge-pump residue amplifying circuit for a pipelinedAD C stage 96

3.17 Simplified diagram of the proposed pipelined AD C stage 100

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3.18 Inpu t-outpu t transfer curve for an 1.5bit stage, reference voltage for eachsection 1, 2, 3 is 350mV, 450m V and 550m V respectively 101

3.19 Simplified architecture of a conventional pipelined ADC, including twoclock phases 103

3.20 Simp lified architecture of the current-charge-pum p pipelined AD C, includ-ing four clock phases 104

3.21 Inverter based signa l-path com parator with differential output, offset of thefirst stage is calibrated during the clock phase CK r2 105

3.22 Inverter based sub-ADC path comparator, dynamic latch is gated at theclock phase CK r2dd to ensure proper latching 108

3.23 Operation sequences for stages in the current-charge-pump pipelined ADC. 1093.24 Generation of four non-overlapping clock phases from a frequency divide-

by-2 circuit 1103.25 Current-charge-pump multply-by-2 circuit, only phases CK r2 and CKa are

shown for circuit distortion analysis. C l p , C rp , C 2 p are parasitic capacitors. 1143.26 Die photo 1173.27 Measured output spectrum at lOOMS/s with a -ldB FS input sinewave near

Nyquist 118

3.28 Measured SNDR, SNR, and SFDR at lOOMS/s for a Nyquist input withamplitudes varying from -37dBFS to OdBFS 119

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3.29 Measured SNDR , SNR, and SFDR at lOOMS/s for a- ld B F S input sinewavewith frequencies varying from 101kHz to 49MH z 120

3.30 Measured SND R, SNR, and SFDR for a -ldB FS input sinewave at 49kHzwith sampling frequencies varying from 1MHz to 100MHz 121

3.31 Measured DN L and INL 1223.32 Fully differential schematic of the proposed current-charge-pump circuit

for a pipelined AD C 1253.33 Fully differentia l schem atic of the current-charge-pum p circuit with output

reset to V cm before sampling. CKn_i and CK n + i are from previous andsucceeding stage respectively 128

3.34 Alternative MDAC with V ref subtracted from V in , operation in the ampli-fyin g phase is shown 129

3.35 Alternative MDA C with reference current injected into the comparator vir-tual ground node, operation in the amp lifying phase is shown 130

3.36 Alternative MDAC with reference voltage sampled onto a separate capaci-tor, operation in the amp lifying phase is shown 132

A .l A typical two stage miller compensated OTA 153A.2 OTA in a capacitive feedbac k configuration, step signal is applied at the

input to analyze the outpu t settling behavior. 154A.3 OTA outpu t slewing and linear settling 155

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List of Tables2.1 Device sizes for the 0.5 V OTA 502.2 ADC performance summary from 0.4 5V -0.5 5V @25C 612.3 Sub -lV ADC Performance Comparison 632.4 SFDRs of two gate-bootstrapped sampling switches and a transmission

gate sampling switch 68

3.1 ADC performance summary from 0.95V-1.05V @ 25C 1223.2 8bit ADC performa nce comparison 1233.3 OTA-less Pipelined ADC perform ance comparison 1243.4 Reference voltage and sub-ADC comparator threshold values, VDD = IV,

Vpp,diff = 800m V 127

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AcknowledgmentsThroughout my Ph.D. study here at Columbia Integrated Systems Lab, I received nu-

merous h elp from m any peop le. W ithout them, I wo uldn't be able to finish the dissertationin a timely manner. I hope I could express my gratitude to all of them.

First of all, I am very g rateful that I did my Ph.D. under Professor Peter Kinget's guid-ance. His deep knowledge and insights into circuit design is always a great source for meto learn from. His focus and dedication to the field of integrated circuit is an inspiration toall ofhisstudents. He also sets a high standard for us by being hard-working, energetic andhighly efficient.

I am also very grateful to Professor Yannis Tsividis, Professor Charles Zukowski, Dr.Kumar Lakshmikumar and Dr. Vincent Leung for serving on my thesis defense commit-tee. Thanks for taking their precious time reviewing my thesis and giving me insightful

feedbacks.I am very thankful to my colleagues at Columbia Integrated Systems Lab (CISL). They

are always an essential pa rt of my lif e here. In my early days and years of Ph.D. study, I gotmuch help from Shou ribrata Ch atteijee, Frank Zhang, Anuranjan Jha and Babak Soltanian.Learning from the experiences and wisdom of senior students helped me move forwardmuch smoother. For almo st my entire stay in the lab, I am grateful that I have the com pan-ions of three other fellow Ph.D . students, Ajay Balankutty, Yiping Feng, and Shih-AnYu.Ihonestly learned as much from them as I did through my own research and study. W henever

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I needed some help or felt like to discuss som ething, they are always there, willing to sharetheir time and know ledge. Mo st importantly, it's the time w e spend together, inside the labor outside, that makes my Ph.D. life more dynamic and memorable. My sincere thanks alsogo to many other colleagues at CISL. In no particular order, they areKshitijYadav, K arthikJayaraman, B aradwaj Vigraham, Jayanth Ku ppamb atti, Colin Weltin-Wu, Nebojsa Stanic,Na Lei, Bob Schell, Maria Kurchuk, Ari Klein, Christos Vezyrtzis, Kagan Irez, Chen Li,Marco Crepaldi, Jorge Fernandes, Richard Hsieh, Navin Harwalkar, Jonathan Tompson,Robin Stevenson, Ryan R oberts, Mingdong Hu, Frank Fang, etc. I appreciate much alltheir friendship. I would also like to use this opportunity to thank Dr. Katsu Nakamurafor the internship and later a full time position in his group at Analog Devices, and my M .Phil, advisor Dr. Kong-Pang Pun for his encouragement and belief in me. Special thanksto Ajay Balankutty and Colin Weltin-Wu for proofreading my thesis draft.

My Ph.D. study was sponsored by Realtek, Analog Devices, as well as Dept. of Electri-cal Engineering and Dept. of Physics for teaching and research assistantships. My sincerethanks for their generous financial support for the past four and a half years. Special thanksto Prof. Gustaaf Brooijmans and senior colleague Jaroslav Ban of Physics department. Iwould also like to thank U nited M icroelectronics (UM C) for chip fabrications.

Lastly, I can't be more grateful to my family members, my sister Xiuhong Shen, mymom Wenjuan Chen and dad Zhiming Shen. W ithout their support and love, I wou ldn't behere pursuing my Ph.D. My girlfriend Qinghui Yu deserves my very special thanks here.Thanks for her love and understanding.

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Chapter 1

Introduction

1.1 OverviewDigital CMOS technology has already stepped into the nanometer era and digital signalprocessors are getting faster and morepowerful.As a result, more traditional analog circuitfunctionalities are being pushed and implemented in the digital domain to take advantageof the process scaling. Nonethe less, the analog-to-digital converter (ADC) can never bereplaced by digital circuitry, as it acts as the bridge between digital processing and theanalog world [1]. B ecause of the imp ortance of the ADC, much research has been done inthis field in the last few decades and a few of the ADC architectures are widely used fo rvarious applications. Each type of ADC has its own pros and cons. They are very brieflyreviewed h ere to provide the context f or the pipelined ADC we are focusing on.

1


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2Flash ADCFlash AD C is a fully parallel architecture, and is therefore the fastest ADC. An N-bit flashADC needs 2N 1 comparators and the same number of reference voltages. The digitaloutputs from the co mparator array are thermometer codes and are further encoded to pro-duce the binary w eighted co des. For the flash ADC, the operating frequency is only limitedby the speed of a comparator.

The two main drawbacks of the flash ADC are the large hardware requirement andsensitivity to the offset of the comparator. It is suitable for high speed, low resolutionapplications.

Two Step Flash ADCTwo step flash ADC consists of two stages of flash ADC, namely the first stage coarseADC and the second stage fine ADC. The coarse ADC produces the most significant bits,and then the residue is applied to the fine ADC to get the least significant bits. This type ofADC takes two clock cycles to do one conversion and is thus considerably slower than thesingle stage flash ADC. But it substantially saves the hardware requirement.

Subranging ADCThe concept is sim ilar to the two step flash ADC. Subranging AD C breaks the conversionprocess into multiple steps, thus saves more hardware, but at the cost of longer conversion


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3time. Each step is responsible for several bits of digital output and sends the residue to thenext stage.

Successive Approximation ADCThis kind of AD C is a special type of subranging A DC. It uses a DAC to produce an analogsignal to approximate the input signal. By adjusting the DAC until the DAC output matchesthe input sample, digital code representing the analog input is generated. The successiveapproximation ADC only consists of one stage and a digital logic circuit that controls theDAC. The accuracy of this ADC can be very high at the cost of long conversion time. Inaddition, this architecture is also very hardware-efficient.

Dual Slope AD CA standard dual slope ADC has two parts: an integrator followed by a comparator thatproduces a pulse with its width propo rtional to the input signal; a counter that translates thepulse w idth into digital codes. It is also called an integrating A DC. This type of ADC canachieve very high resolution but is very slow. In the modern days, sigma delta ADCs havevirtually replaced integrating AD Cs.


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4Oversampled ADCOversampled ADC s started to gain attention a coup le of decades ago and have been appliedto many fields like audio, digital telephony, etc. T he basic concept underlying the oversam-pled AD C is the use of feedback to track the input signal. Due to the high low-frequencygain from the internal loop filter, the low frequency part of the digital output spectrumvirtually replicates that of the input signal, while the quantization noise sees a high passand is shaped by the n oise transfer function. Sigma delta ADC is the main category ofoversampled ADCs. They are suitable for very high resolution but relatively low operatingspeed.

Pipelined ADCPipelined A DC has its origin in the subranging AD C, which was first patented in 1959 [2].It also divides the conversion task into several stages to dramatically save the hardware re-quirement com pared w ith the flash ADC . But unlike conventional subranging AD C, whichtakes multiple clock cycles to do one conversion, pipelined ADC has a sample and holdcircuit for each stage. The stage track and hold circuit serves as an analog memory cell sothat the previous stage can be released to process the next input. In this way, the pipelinedADC works like a shift register and achieves very high throughput rate. The throughput isindependent of the number ofstages.A n interstage am plifier is added to restore the residuefrom the previous stage back to fu ll scale, thus it alleviates the accuracy requiremen t of the


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5succeeding stages. The drawback of the pipelined ADC is its inherent latency, which mightcause stability problem in a feedback control system. But for many applications, it is thebest choice due to the superior combination of high speed, medium to high resolution andrelatively low power consumption. Fig. 1.1 shows the simplified block diagram of the firsttwo stages of the pipelined AD C.

Figure 1.1:Block diagram of the first two stages of a pipelined ADC.

To understand the performanc e tradeo ffs of different types of AD Cs, extensive studieson commercially available ADCs have been done and the results are shown in Fig. 1.2 [3].As w e can see, the performance of pipelined ADC s is a compromise between low resolutionhigh speed flash ADCs and high resolution low speed sigma delta or SAR ADC s.

Fig. 1.3 shows the complete diagram of a standard pipelined ADC. There are three in-puts to the ADC, namely the analog input signal V in , the reference voltage V ref and theclock CLK in . Any nonideality associated with those inputs will affect the converter's ac-curacy. The "pipeline" is enabled by the internal sample and hold circuit for each stage.Notice that the clock phases are alternated from stage to stage, therefore each one intro-duces half a clock cycle latency. The number of bits for each stage is mainly determined bythe operating speed and pow er [4,5 ]. Besides a numb er of pipelined stages, the converter


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6

Theoretical slope = 1/3b/dBmmm \ \\ Actual Slope1/2,3 b/dB Fiash Folding* Half-Flashx Pipelined* SAR Sigma-DeltaUnknown

40 50 6010log(Q (dBsps)

100

(a) FlashFolding m i f a M Half -FlashX PipelinedX SAR Sigma-Delta Unknown

40 50 6010log{/s) (dBsps)

(b)Figure 1.2: (a) Number of bits versus sam pling frequency for different types of ADCs [3];(b) Power consump tion versus sampling frequency for different types of ADCs [3].


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7

thresholdFigure 1.3:C omplete diagram of a pipelined AD C.

also includes, among others, a non-overlapping clock generator, reference voltage buffer,and sometimes a dedicated front-end track and hold stage (not shown in Fig. 1.3) [6,7]. Aflash type A DC is usually employed for the last pipelined stage, where no residue needs tobe generated. The accuracy requirements for the later stages are largely alleviated due tothe aggregated gain from the earlier stages. In a typical design, a redundant bit is usuallyadded to each stage to tolerate the thresholdoffsetin the sub-ADC [8]. Accordingly, digitalcorrection logic needs to reconfigure the stages' output bits to the final digital output.

The pipelined ADC architecture is a leading choice where sampling rates from a fewMH z to a few hundred MHz are required. Its main applications include com munication,video, CCD -based image processing, and data acquisition.


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8Ultra-low-voltage pipelined ADCsAs CMOS technology advances, which is mainly driven by digital circuits, the supplyvoltage for digital and analog circuits keeps scaling down. The International TechnologyRoadm ap fo r Semiconductors (ITRS) reported the trend of supply voltage and technologynode in the nearfuture[9], whic h is shown in Fig. 1.4,1 .5. As projected, the supply voltagefor analog and RF transistors is going down to sub-IV in a few years; the supply voltagefor digital low pow er circuit will be down to 0.5V in about 7 years. Serving as an importantinterfacing circuit between the analog and digital domain, the pipelined ADC needs tokeep up with the supply voltage scaling and consistently deliver high performance to meetits applications' requirements.

In the past few years before we published our work [10, 11], a couple of sub-IVpipelined ADC were reported in literature [12,13], both of them operatefroma 0.9V supplyvoltage. Wh ile the supply of 0.9V had already started to show the performance implica-tions of the pipelined ADC such as finite OTA gain and sampling switch linearity, moresignificant supply voltage reduction was desired to further explore the feasibility of highperformanc e ultra-low-voltage pipelined AD Cs. On the other hand, the nanometer CMOStechnology that dem ands low supply voltage has its own unique features. We need to takeadvantage of some new characteristics like reverse short channel effect, and address theissue that comes with it, for instance, high transistor leakage when it is in off-state.


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9

21.81.6

E 1 - 4Q5 1.2

Analog/RF

1

0.8

W

-+-G ate Length

\S . < c

--VDD

1401201 0 0 ~80 o>c664020

.8(0O

2005 2010 2015 2020Year(a)

Digital High Performance

20&

2005 2010 2015Year(b)

Figure 1.4: Trend of supply VDD and technology node versus year, (a) Analog and RF;(b) digital high perform ance.


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10

Digital Low Standby Power

2005 2010 2015 2020Year(a)

Digital Low Operation Power 100

EcOicJ(3O

2010 2015Year(b)

Figure1.5: Trend of supply VD D and technology node versus year, (a) digital low standbypower; (b) digital low operation power.


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11Ultra-low-power pipelined ADCsWh ile ultra-low-voltage pipelined A DCs is a research topic to prepare for the near future,ultra-low-powe r pipelined A DC s are always of great research interest, especially fo r batterypowered devices. Unlike digital circuits, where power consumption reduces as supplyvoltage goes down:

Pdigital CK fclk x C x VDD 2 (1.1)

Analog circuits' power consumption, taking ADC as an example, goes up as VDD scalesdown [14]:

Panalog OC f c l k X 2 2 B / V D D ( 1 .2 )

where B is the resolution of an ADC. To separate the design issues involved with lowsupply and low power consump tion, a regular supply voltage can be used to betterfocusonthe power aspect of the pipelined ADC .

From a general point of view, there are three ways to reduce the power consumptionof a pipelined ADC, one is to optimize the design in the circuit level, especially for themain building blocks like OTAs [ 1 5 - 1 7 ] ; the second w ay is to innovate in the architecturallevel, which could potentially increase operating efficiency substantially [18-22]; finally,employing digital calibration to reduce the power. By mov ing the analog design complex-


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12ity into the digital dom ain and taking advantage of the low power consumption of digitalcircuits in advanced CM OS technology, the total power consumption can be brought downsignificantly [23-2 8]. Sometimes, the latter two approaches can be combined to reach abetter solution [29-31 ]. In this thesis, the work on low power pipelined ADC mainly fo-cuses on the architectural innovation, as well as taking advantage of the standard digitalcalibration.

Imp lications on pipelined A DC p ower consumption with lowering sup-ply voltageLow v oltage does not necessarily mean low power. In the case of the pipelined AD C, wehave two scenarios when the supply voltage is scaled down. One is that the ADC is noiselimited, the other is that the ADC is mismatch limited. The following simplified analyseslook at the power change with half the VDD, given the same signal-to-noise (SNR) andsampling frequenc y fs .

Noise limited pipelined ADC

In the noise limited scenario w hich mainly applies to high resolution pipelined A DCs, wecan furthe r divide it into the following two cases:

VDD scaling without technology scaling In this case the same CM OS technology isused w hen V DD is scaled by half, thus the transistor biasing point orgm/I is kept constant


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13to maintain the maximum operating speed. A ssuming signal swing is proportional to VDD,the sampling capacitor in the pipelined AD C has to be four times larger to achieve the sameSNR. This results in four times the biasing current to keep the same GBW and samplingfrequencyfs.In conclusion, the pow er consumption dou bles when VDD is half.

VDD scaling with technology scaling As CM OS technology advances, the transistor'speak f Troughly doubles as channel length goes down by half [32], This means that we canincreasegm/I by one tim e (assuming it hasn 't reached the maximum yet) while keeping f Tthe same as that in the old technology. In this case, the current I only needs to be doubleto have four times thegm,thus power consumption will remain the same as VD D scales byhalf.

Mismatch limited pipelined AD C

The performan ce of lower resolution pipelined AD Cs tends to be mismatch limited. Thetransistor mismatches in an OTA are not critical because they only cause input referredoffset, which can be tolerated in a pipelined ADC . The capacitor matching is critical sinceit defines the AD C's interstage gain. Here w e also divide this category into the followingtwo cases:

VDD scaling without technology scaling If we assume no technology scaling, then thesampling capacitor has to be four times larger to maintain the same signal-to-mismatch


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14accuracy. T his will lead us to four timesgmand I, thus the power consumption is twice aslarge.

VD D scaling with technology scaling Acco rding to the prediction of the ITRS report [3 2],the matching error of MOM capacitors will go from 0.15% to 0.1% over the following 3-5 years, for a lp F capacitor. For MIM caps, the matching improves about 40% in thefollowing 5 years. Considering the corresponding VDD for newer technology also scalesdown modestly, Matching accuracy A cc = V r m s / ( 3a (V o s)) will roughly stay the same forthe same capacitor size, so power consumption will scale proportionally with VDD in thiscase.

In summary, the FOM versus technology node (thus VDD) roughly stays the same ifthe pipelined ADC is noise limited and improves if it's mismatch limited. In the caseof VDD scaling in the same technology, power always doubles as signal swing is half.Furthermore, unlike the random noise in noise limited pipelined A DC, the error caused bycapacitor m ismatch only results in fixed interstage gain error and can be compensated usingcapacitor error-averaging technique [33], digital calibration [23] or trimming.

The p ower consum ption analyses above regarding VDD scaling is highly simplified. Inpractice there are m any other factors that affect the power and technology/VDD relation-ship. For instance, the digital part in the pipelined ADC can always benefit from VDDscaling; the leakage issue in advanced technology need more power to combat; the ex-


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15tra power is consumed by biasing circuit; and the available signal range scales faster thanVDD.

1.2 MotivationsUltra-low-voltage pipelined ADCDigital circuit designers are pushing for lower and lower supply voltages to reduce powerconsump tion. The dynamic digital power consumption is proportional to VD D 2, and thestatic power consum ption due to various leakage mechanisms is often exponentially depen-dent on VDD. ADCs typically coexist on the digital die, especially in the context of systemon a chip (SOC) devices. Sharing the same pow er supply voltage reduces the power domaincomplexity.

In some energy scavenging applications like wireless sensor networks, a single solarcell can be used as the power supply when due to space constraints. The supply voltage ofa so lar cell is around 0.5 V.

We also want to explore and push the lower boundary of supply voltage for analogdesign, to see if it could be fully compatible with the low supply voltage associated withfuture thin-oxide nano-scale devices and to understand what the performance implicationsare.


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16Ultra-low-power pipelined ADCPower consumption in general has always been an active topic for integrated circuit design.There are two broad aspects to it, one is that high power consumption means less batterylife for mobile devices, and the other is that it potentially involves heat dissipation issue.

As the information technology develops, mobile devices like cell phones, and consumerelectronics like digital cameras, are reaching more and m ore people and they are being usedmuch more frequently. Pipelined A DCs are widely used in these devices. By reducing itspower consumption, together with other parts of the system, the devices' operating timecan be dramatically increased.

The CM OS technology has well entered the nanometer era. While it enables higherintegration, more functionalities and cheaper products, it also dramatically increases thepower density and thus makes the h eat dissipation issue much worse. In applications wherenumerous channels of pipelined ADC s are used, for example, in a multi-channel readout ordetection circuits, the heat dissipation could b ecome a big concern.

1.3 ContributionsTwo pipelined A DC chips were designed, fabricated and measured. The first one focuses

on ultra-low-voltage power supply fo r the pipelined ADC , the main contributions are listedbelow:


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17 The design feasibility of a 0.5V 8b it lOMS/s pipelined ADC on a 90nm CM OS pro-

cess is demonstrated, without internal voltage boosting or using special devices.

A cascaded sampling technique is used to combat switch OFF leakage. An auxiliary S/H in the sub-ADC path is introduced to eliminate the front-end S/H.

A two-stage 0.5V OTA with 50dB DC gain and 32MHz GBW is presented.

The second chip aims at an ultra-low-power pipelined ADC, the main contributions areas follows:

A IV 8bit lOOMS/s current-charge-pump p ipelined ADC in 90nm CMOS process isdemonstrated, the FOM of237fJ/Conv.Step is achieved.

Current-charge-pump MDAC is introduced, power hungry reference buffers for theADC are largely eliminated fo r the proposed stage architecture.

Two inverter-based com parators are designed fo r the current-charge-pump pipelinedADC.

1.4 Thesis OrganizationThe thesis is organized into four chapters. This first chapter provides a brief overview ofvarious types of analog-to-digital converters, which leads to our focus on pipelined ADC


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18and the background information for the work being presented. It also states the challengesand m otivations for our research.

Chapter2presents an ultra-low-voltage pipelined ADC in advanced digital CMO S tech-nology. Introduction and brief background of low voltage operation are given at the begin-ning of the chapter, follow ed by system level and block level designs of this work, includingvarious proposed design techniques. Theoretical analyses are also given where appropriate.Afte r presenting the m easurement results for the prototype, the idea of an improved versionof the gate bootstrapped switch for low supply voltage circuit is described.

Chapter 3 addresses the power consumption issue. A current-charge-pump pipelinedADC without a big reference buffer is presented. Similar to chapter 2, introduction andreview of other ultra-low-power pipelined ADCs are given before the descriptions of pro-totype design at system and block levels. After the measurement results, we present severalideas for futu re improvement, including the schematic of a fully differential version of theproposed circuit and alternatives to a standard MDAC for the pipelined A DC stage to avoidthe use of big reference buffers.

Chapter 4 summarizes the results of the two pieces of work and concludes the thesis.Future directions are then discussed for further investigations.

Appendix A presents and analyzes the OTA settling behavior at ultra-low-voltage sup-

ply.


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Chapter 2

Ultra-Low-Voltage Pipelined ADC

2.1 Introduction2.1.1 ChallengesThe research goal of exploring ultra-low-voltage analog circuit design is motivated by sev-eral trends in integrated circuit design and semiconductor technologies, and the applica-tions they enable. System on a chip (SOC) designs have made possible substantial costand form factor reductions, in part, since they integrate crucial analog interface circuits,such as analog-to-digital converters (ADCs), with digital computing and signal processingcircuits on the same die. The interfaces only occupy a small fraction of the chip die andfor SOC designs the technology selection and system design choices are mainly drivenby digital circuit requirem ents. In the past decades, design technique s for analog inter-

19


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20face circuits, that are fully compatible with scaled standard digital CMOS technologiesand do not require special technology options, have been important enablers to continueever more com plex SOC designs (see e.g., [34]). A s the feature sizes in modern nanoscaleCM OS technologies reduce, the maxim um supply voltage also has to be reduced to main-tain reliable device operation. The International Technology Roadmap for Sem iconductors(ITRS) foresees that the supply voltage for low power digital circuits will scale below IVfor high p erformance applications and down to 0.5 V for low power applications w ithin thenext decade or so [35]. Additionally, the most energy efficient operation of digital systemsoccurs for supply voltages between 0.3 and 0.5V in deeply scaled technologies.

Scaveng ing energy to ope rate circuits from the environment is desirable for applicationssuch as wireless sensor nodes or ambient intelligence. For example, if only one solar cellis available due to space constraints, the operational supply voltage is about 0.5V [36,37].

Pipelined A DCs are a popular choice fo r analog-to-digital conversion for their attrac-tive features of high operation speed, good resolution, and low power consumption. In thiswork, an 8bit lOMS/s pipelined ADC is targeted with an aggressive low supply voltage of0.5V. In prior work, several techniques have been developed to accommodate low voltageanalog circuit design such as the use of special low V t devices [38,39], on-chip clock andgate voltage boosting [40-43], body driven circuits [44,45], or switched-opamp [46^18]techniques. Low V T devices require extra mask s during fabrication and thus result in highercost. On-ch ip voltage boosting can lead to long-term reliability concerns, especially fornano-scale CM OS devices. Using the body terminal of a MOSFET offers the circuit de-


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21signer a num ber of interesting circuit design opp ortunities, but the body transconductance,gmb> is significantly smaller than the gate transconductance, g m , which can lim it the attain-able speed or noise performance. Switched-opamp techniques have been successfully usedfor very low voltage designs but typically operate at a reduced operation frequency due tothe amplifier turn-ON times.

2.1.2 SolutionsThe w ork presented here is using true low vo ltage design techniques to take full advantageof advanced CMOS technologies without resorting to special devices or on-chip voltageboosting [10]. The switch OFF leakage in the sampling circuit is suppressed using a cas-caded sam pling technique. A front-end signal-path sample-and-hold am plifier (SHA) isavoided by using a coarse auxiliary S/H for the sub-ADC, and by synchronizing the sub-ADC and pipeline-stage sam pling circuit. A 0.5 V operational transconductance am plifier ispresented that provides interstage am plification with an 8bit performance for the pipelinedAD C operating at lOM S/s. The chip was fabricated on a standard 90nm CMOS processand measures 1.2mm x 1.2mm. T he prototyp e chip has 8 identical stages and stage scalingwas not used. It consumes 2.4mW for lOM S/s operation. Measured peak SNDR is 48.1dBand peak SFDR is 57.2dB fo r afull-scalesinusoidal input. Maximal INL and DNL are 1.19

and 0.55 LSB respectively.


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222.1.3 Chap ter OrganizationIn Section 2.2, the top level design of the pipelined ADC is presented, where system, stageand MDAC design considerations are covered, as well as the introduction of an auxiliarysample and holdfor thesub-ADC . Reverse short channeleffect(RSCE) can favorablyaffectthe design of the pipelined AD C and is also briefly discussed in this section. Section 2.3details the block level designs, em phasis are given on the cascaded sampling technique asa solution to address switch-OFF-state leakage and the 0.5V OTA design fo r the pipelinedADC. Experimental results are presented in Section 2.4. Following that, the design issueregarding the sampling switch at ultra-low supply voltage is investigated in Section 2.5.Finally, the summary of this chapter is given in Section 2.6.

2.2 Ultra-Low-Voltage Pipelined ADC System Design2.2.1 Top-Level and Stage Design ConsiderationsIn ultra-low-voltage analog design, one intrinsic challenge is the reduced available signalswing. It makes mu lti-bit stages not desirable due to comparatoroffsetand hysteresis con-cerns. Mu lti-bit stages further require a higher open-loop gain-bandwidth (GBW) fo r theresidue amplifiers due to the small feedback factors in the stage. In this design, we use a1.5bit/stage architecture, which tends to consum e less power and retains high throughput.Using digital offset correction, the 1.5bit pipeline stage can tolerate a comparator offset


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23

A.Vi, I

w

/V 2 d[13,12]^21 ED tt>d[ 15,14]

CLK (en. U \14 3Stage 1 Stage 2 Stage 81.5b 1.5b 1.5b

[V r e f+V c m v r e f. ]

Figure 2.1:Block diagram of the pipeline ADC prototype chip.magnitude of up to |LSB of the sub-ADC. Fig. 2.1 shows the block diagram of the con-verter prototype. To simplify the prototype d esign, the second through the eighth stagewere kept identical to the first stage, which has the most stringent requirements. The per-forman ce could be further optimized by app lying progressive size and power consump tionscaling to the later stages. A front-end SHA of the pipelined AD C is not implemented tosave power and reduce noise. This is made possible by the introduction of an auxiliary S/Hfor the sub-ADC , which will be presented later in this section.

A single-ended diagram of a stage of the pipelined ADC is shown in Fig. 2.2(a) forclarity, but the actual chip implementation is fully differential. It consists of 2 comparatorsas sub-ADC and an M DAC that perform s signal sampling, subtraction and residue ampli-fication. A 400m V peak-to-peak differential full-scale input swing is targeted, taking intoaccount the typical available output swing of a 0.5V OTA. The signal comm on-mode volt-age is set to 250mV and the reference voltages are 250mV100mV. For an 8bit accuracy


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24

CascadedSamplingV ir

AuxiliaryS/H|V ref+/4iv re f74

T d[i,i-1](a)

(b)Figure 2.2: (a) Single-ended version of one pipeline stage; (b) non-overlapping clock sig-nals 02) and their advanced (cf>a,


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25level, the LSB of the ADC is still as large as 1.6mV. The choice of the size of the sam-pling cap acitor is driven by the c oncern of keeping parasitic capacitors sufficiently small.To avoid an extra m ask to realize a MI M capacitor, an interdigitated metal-metal capacitorwith a unit size of 250fF was custom designed and verified using an electromagnetic sim-ulation. The unit c apacitor uses a stack of interdigitated m etal combs on Metal 1 throughMetal6 and occupies 130/xm 2. In this design, four unit capacitors in a common-centroidlayout for improved matching are used to realize the sampling capacitors Ci and C 3 (seeFig. 2.2(a)). The RM S value of the thermal noise, v2 R M g kT/C, for a lpF samplingcapacitor is 64/iV R M s and sufficiently small com pared to the LSB value.

The on-ch ip clock g enera tor gen erate s two no n-overlap ping clock signals


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26

CK S | 1 | 1CK a | | | |

Figure 2.3: A standard fully differential MDAC for a 1.5bit stage, the non-overlappingsampling clock phase CK Sand the amplification phase CKa are also shown. Switches d0-d 2 are controlled by the sub-ADC output during CKa. Center switch d 0 is used to replacethe reference voltage V cm for both paths.


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272.2.2 MD AC Design ConsiderationsA standard switched capacitor MDAC is widely used in designing pipelined ADCs [8],and its functionality and performan ce are well studied. But a few practical design issuesmight easily be overlooked . Here w e will briefly investigate the issues related to inputcommon mode, capacitor matching and noise of the MDAC. Fig. 2.3 shows the standardfully differential MDAC for a 1.5bit stage, center switch d 0is used to replace the referencevoltage V c m . For the following analyses, assuming center switch d 0is turned on during theC K a phase.

MDAC Input Common Mode

First we look at the MDAC input common mode issue, to see whether it affects the op-eration of the circuit. Here we assume all the capacitors in Fig. 2.3 are identical, and thenominal co mm on mode voltage is OV, for both of the OTA input and output. In the casethat there is a common m ode voltage shift at the input of the MDAC:

v i p = A V c m i + V; (2.1)vin = AVcrni-V; (2.2)


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28Then, from clock phase CK Sto CKA, we can apply the charge conservation rule at the inputshorted nod e V N l , two OTA input virtual ground nodes V n2and VNa respectively:

( A V C M I + V I ) C + ( A V C M I - V O C = ( V N l - V N 2 ) C + ( V N L - V N 3 ) C ( 2 . 3 )

( A V C M I - V I ) 2 C = ( V N 2 - V N L ) C + ( V N 2 - V O P )C (2 . 4 )

( - A V C M I + VI)2C = ( V N 3 - VN l)C + ( V N 3 - V O N ) C (2.5)

Assum ing the OTA is ideal, VN2 = VN3. From (2.3), we get:

A V C M I = V N L - V N 2 I 3 (2 . 6 )

From (2.4), (2.5), and V o p + Vo n = 0 given OTA output common mode is forced to 0 byits CMFB circuit, we reach the following equation by adding them up:

V N l = 2 V N 2 > 3 + 2 A V c m i (2.7)

From (2.6) and (2.7), we arrive at the following equations at the end of the phase C K a :

V N L = 0

V N 2 I 3 = - A V ,

(2 .8 )

(2.9)


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29It's evident that even if the MDAC output comm on mode is not affected by the input com-mon mode, given ideal output comm on m ode rejection, the OTA input common mode willshift the same amount as the MDAC input common mode. Thus we either need to makesure the incoming signal's common mode is well controlled or the OTA is designed tohandle large common mode range.

Capacitor Matching

There are in total four capacitors in the 1.5bitfullydifferential MDAC. Ideally we want allof them to have the same capacitance. Carefu l layout including common centroid techniquecan improv e the capacitor matching to 0.1% level, but it's much harder trying to match allfour of them. H ere we 'll address the issue whether matching all the capacitors C i to C4 isnecessary.

Assuming everything else is ideal, except for the matching of the capacitors, we canagain apply the charge conservation rule at nodes V N l , V N2 and VN 3 , respectively. Notethat the results from 2.9 migh t not hold since the capacitors were assumed to be identicalin the derivation.

Charge conservation at node Vnx,from the end of the phase CKSto the end of the phaseC K a :

C x V i - C a V i = ( V N 1 - V N 2 i 3 ) C 1 + ( V N i - V N 2 i 3 ) C 3=> (Ci C3 ) V i = ( C i + C 3 ) ( V N I - V N 2 I 3 ) (2.10)


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30Charge conservation at node V N 2 :

- V i ( C i + C 2) = ( V N 2 , 3 - V n J C i + ( V N 2 , 3 - Vo p)C 2 (2.11)

Charge conservation at nodeV n3 :

V I(C 3 + c 4 ) = (V N2,3 - V N l ) C 3 + (V N2 ,3 - Vo n)C 4 ( 2 . 1 2 )

Assume OTA output common mode is fixed at 0, we can plug V op = V 0n =V 0 into 2.11and 2.12. Then there are three variables V N l , V N2 3 and VQ in the three equations above.Solving V 0 finally gives:

V o = + + ( ( - ( 2 . 1 3 )

From 2.13, we observe that as long as Ci = C 2and C3 = C4, the second term on the rightside of the equation will drop out and V 0 is exactly equal to 2Vi? which is the expectedoutput in this case. N ote that given Ci = C 2and C3 = C4, Vni and VN a 3are still functionsof Ci and C 3 :

= lrtv<


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31If Ci52 is not equal to 3,4, the common mode voltage at the OTA virtual ground will bemodulated by the input signal. If we further apply a VCM source (which should be 0 here)at node NI , then 2.10 no longer holds because no de NI is driven during phase CKA. In thiscase derivation show s V N 2 , 3 I Sequal to 0 , which means the virtual ground is not mod ulatedby the input signal anymore. In short, for both cases where node Ni is driven or not, thefunction of the MDA C does not rely on the matching between C i ;2 and C3)4. But if the nodeNx is floating, the OTA is required to hand le a larger input comm on m ode range, dependingon how well Ci ;2 and 03,4 are matched.

plification phase.


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32MDAC Noise

For a typical pipelined AD C, noise is an important design parameter. It often limits theperformance especially for a high resolution ADC. Usually we need to make sure that theinput referred noise of an AD C is below the quantization noise. For a pipelined AD C,noise is mainly contributed by the MD AC of a pipelined stage, the reference voltage sourceand the sampling clock jitter. Among them, the noise from the MDAC usually dominatesand it receives much attention when designing a pipelined ADC. Due to its discrete na-ture and involvement of two clock phases, the noise analysis of an MDAC might not ap-pear straightforward. Noise in switched capacitor circuits has been dealt with in varioussources [4 9-52 ]. In order to better understand how different noise sources in an MDACplay a role, w e present a sim plified analysis for the MDA C used in a 1.5bit stage. Fig. 2.4shows the MD AC in the am plification phase. All the switch noises and OTA noise are in-cluded. The value of the load capac itor is equal to the unit capacitor in the MDA C, whichassum es a stage scaling factor of 2 [5 ,15].

During the sam pling phase, which is not shown in the schematic, due to aliasing of thesampled noise [53], the total noise powe r on both capacitors is:

(2.16)

It's not a fun ction of switch on resistance, because the power spectral density is proportionaltoRON,w hile the bandw idth of the RONC circuit is inversely proportional to RON . During


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33this sampling phase, the OTA is being reset and not connected to the sampling network,so the OTA wo n't con tribute any noise. Then we move on to analyze the noise in theamplification phase. As show n in Fig. 2.4, switch on resistance R o n ifromreference voltagepath and R o n 2 from feedback p ath, as well as OTA contribute to the output noise. Here w ecan use superposition and calculate each noise source's contribution separately. The outputnoise can be calculated using the following formula:

/infK o = Sn>i(a;)| H(a;) |2da; (2.17)Jo

or it can be simplified if we know the equivalent noise bandwidth of the transfer functionH(w):

V*>o= S n | H ( 0 ) | 2 B W (2.18)

In the above formulas, Sn(u;) is the spectral den sity of a noise source, H(0) is the noise gainat DC fro m the noise source to the M DAC output, H(ai) is the circuit transfer function andBW is the equivalent noise bandwidth from the noise source to the MDAC output. For thesimplicity of this analysis, assume a single stage OTA is used and it has an input referrednoise spectral density:

S n,o ta M = 2 - 2 - 4 k T ^ (2 .19)3 K m


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34where the first factor 2 accounts for the two input transistors of the OTA, the second factor2 roughly accounts fo r the extra noise from the rest of the OTA, mainly the loading currentsources. The spectral density for the two switches are straightforward:

S i , 2 M = 4kTRo n l,2 (2.20)

Noise gains at DC for the three noise sources are:

Hi(0) = ^ = l (2.21)H n2(0) = 1 (2.22)

H n , o t a ( 0 ) = 1 + ^ = 2 (2.23)

It shows that the OTA noise gain is twice as large as those of the R o n noise. And in apractical design, switch R o n is designed to be 5-10 times smaller than l/g m , so that itdoe sn't affect the settling during the amplification phase. Thus the OTA noise spectraldensity in 2.19 dominates over the switch ones in 2.20. It can also be shown that all threenoise sources see the same pole to the M DAC o utput. Based on 2.17, we can see that theOTA noise dominates at the MD AC ou tput during the am plification phase1. The GBW ofthe OTA is g m / ( C + C / / C ) = 2g m /(3C) and the feedback factorf i of the MDAC is 1/2,

1Derivations sho w that Vn i and V n2 also see a zero and a non-dominant pole, but their transfer functionsare still m ainly shaped by the dominant pole, comparable to the transfer function fromV n , o t a to the output.It would be com plex and tedious to derive the exact output noise due to V n i and V n2, using 2.17


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35thus theeffectivenoise bandwidth that Vn,0ta sees is [54]:

= (2.24)

After plugging 2.19, 2.23 and 2.24 into 2.18, we get the output noise power due to thedominating OTA noise in the am plification phase:

V 2 = 1 6 k T - 22 3 g m 4 3C

32kT= i c - ( 2 ' 2 5 )

Referring the output noise po wer to the input by dividing the MDAC gain of22,and addingthe noise fro m the sampling ph ase, we reach the total input referred noise of the MDAC:

v 2 . = v 2 . + v 2 .n,i n,i,sa 1 n,i, ampkT 32kT , -= 1 22C 9Ck T 16kT

= 2 C + T 2 C ( 2" 2 6 )

The result shows that the noise of the MDAC is not a function of gmof the OTA. In thisparticular exam ple w ith a stage gain of 2, the assum ed OTA noise factor and its load, 2.26shows the noise contributed by the OTA is almost twice as large as the sampling k T /(2 C )noise. Note that the calculated outpu t noise power in the amplification phase is assumed


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36to be sampled by the next stage, so all the noise is aliased to the Nyquist band, similar tothe input k T/ (2 C ) noise. Since the sampled noise at the end of the amplification phaseis all that counts, it seems that the noise in the sampling phase can be ignored. But notethat during the am plification phase, the sampled n oise charge from the sampling phase istransferred to the output and has a voltage gain of2,so it appears in the amplification phaseand the vo ltage gain of 2 fro m the sampling phase to the amplification phase also explainswhy the outpu t noise power is divided by 2 2w hen referred to the MDAC input.

2.2.3 Auxiliary S/H for Sub-ADC PathThe conventional circuit architecture for the first stage of a pipeline ADC includes a ded-icated front-end SHA , as shown in Fig. 2.5(a). This front-end SHA guarantees that theMDAC path and the sub-ADC path operate on the same sample of the input signal. Asshown in Fig. 2.5(b), the sub-ADC decides when the M DAC is sampling and the sub-ADCoutputs are ready w hen the M DAC starts am plifying. A dditionally, preamplifiers are typ-ically used in the comp arators of the sub-ADC to block their kick-back noise [55]. Theseapproaches allow a fast operation of the ADC , but at the cost of a dedicated front-end SHAcircuit and comparator pream plifiers.

Design techniqu es for signal path SHAs at ultra-low voltages have been explored in [56].In this work, we propose an architectural change to avoid the front-end SHA, as well as thecomparator preamplifiers. As shown in Fig. 2.6(a), a simple, coarse, auxiliary S/H is in-


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37

(a)

S/H Sample Hold Sample HoldMDAC Sample Amplify Sample

Sub-ADC Reset Compare Reset Compare

(b)t

Figure 2.5: (a) Block diagram of the first stage of a conventional pipeline ADC with adedicated front-end sample and hold (S/H) and preamplifier (A) in the sub-ADC and (b)the associated operation sequence.


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38

G L K M D A C

V o -mCLKsub-ADC

C L K A U X . S / H ^

(a)

MDACAux. S/HSub-ADC

Sample t[Amplify SampleTi Am plify

Sample Hold Sample HoldReset k Reset

Jlit\Compare Compare(b)

Figure 2.6: (a) Block diagram of the proposed pipeline stage with auxiliary sample andhold circuit and (b) the associated operation sequence.


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39serted in the sub-ADC path. This auxiliary S/H samples the input signal during the samesampling phase as the MDAC p ath. It holds the input signal while the comparators in thesub-AD C m ake their decision (see Fig . 2.6(b)) at the start of the MDA C's residue amplifica-tion phase. T he open sampling sw itch blocks the comparator kickback noise from enteringthe signal path. In the presented lOMS/s pipelined ADC design, the latched comparators,using the topology presented in [57], reach their decision in less than 2%of the samplingclock period w hich leaves plenty of time fo r the MDAC to amplify the residue2. This ap-proach is well suited for moderate-speed pipelined ADCs and offers three benefits: thededicated, high accuracy, front-end SHA , and the associated considerable power consump-tion and die area, as well as the comparator preamplifiers are eliminated; kickback noisefrom the comparator is blocked by the switch of the auxiliary S/H; the auxiliary S/H canbe significantly less accurate than a front-end SHA, since sampling errors are equivalentto comparator offset and a 1.5 bit/stage pipelined ADC is very robust against such offsets.A mismatch between the time constants of the sampling network in the MDAC path andsub-ADC path translates into an offset in the sub-ADC path [58,59]. Assuming that thesampling clock skew between these two paths can be neglected, the worst case mismatcherror is [58]:

Verror = A27rfin(r MDAC ~ T s u b - A D c ) (2.27)2TO further improve the design, the non-overlapping time between the sampling and amplifying phase of

the MDAC could be used to get the comparator outputs ready earlier.


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40where A and fj nare the full-scale input signal amplitude and maximum signal frequencyrespectively, r is defined as the sampling time constant or propagation delay:

r = t a n '( 2 : f i R 0 ) * RC (2.28)27rfin

where RC is the time co nstant of the sampling network; since the sampling network band-width (1/RC) is designed to be much higher than maximum input frequency, f i n , the ap-proximation in 2.28 indeed h olds. In the presented ADC, the full-scale single-ended signalamplitude, A, is equal to V re f, which is lOOmV, and the 1.5 bit sub-ADC can tolerate anoffsetofVref/4,or25mV,so that for a maximum signal frequency of 5MHz when samplingat lOMS/s, we obtain the following requirement:

V f 1A ( R C ) A t < - r ^ - 8 n s ( 2 .2 9 )V ; 4Vre f27rfin

This derivation assumes there are no other offsets in the sub-ADC path, while in practice,we need to allow for com parator offsets due to device mismatch. If we allocate half of thetotal tolerable offset to the comparators, the system is able to tolerate a sampling-networktime-constantdifferencebetween the M DAC and sub-ADC of up to 4ns.

In the presented design, the RC network in the MDAC has a time constant smaller than4ns to guarantee the dynamic performance in the presence of nonlinear resistance of theswitch. It is interesting to note that, theoretically, the auxiliary S/H could be eliminated.


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41However, it is still used to block the comparator kick-back noise and to allow for largercomparator offsets. The auxiliary S/H is realized with the same sampling switch as theMDA C path but a samp ling capacitor of about | the size. This sampling capacitor is stilllarge enough so that the clock feed-through from the switch does not affect the sampledvoltage significantly.

2.2.4 Reverse Short Chan nel Effect for Reduced VT

0.6

0.5

0.4

^ . 0 . 3

0 . 2 ,

0.1 >

0 2 4 6 8 10 12 14 16L/L .minFigure2.7: Simulation show ing the decrease of the threshold voltage, VT , for increasingdevice lengths, a.k.a. the Reverse Short Channel Effect (RSCE), for 2/xm wide NMOStransistors in different CM OS technologies.

In scaled CMOS technologies (0.18/xm and beyond), the reverse short channel effect


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42(RSCE), i.e., the increase of the transistor threshold voltage,Vx, for decreasing channellength, L, is well known to occur [60,61] and is illustrated in Fig. 2.7. In ultra-low-voltageanalog design, we can take advantage of this effect and obtain a lower V r by choosinga larger L. However, increasing L, increases the transistor's parasitic capacitors, and de-creases the its transit frequency fr - In nano-scale CM OS technologies, the transistor fT sare very high and additionally, for analog circuits, the attainable speed performance is typi-cally limited by load or compensation capacitors rather than transistor parasitic capacitors.Moreover, for analog designs, the length is usually chosen as 2 to 5 times the minimumlength to improve the output impedance and to reduce 1/f noise, as well as, to improvedevice matching. A VT reduction is very w elcome fo r transistors used as active loads ortransconductors, since it results in more flexibility in the choice of their bias point even atultra-low supply voltages. For transistors used as switches, the reduced VT improves theswitch ON conductance for limited gate voltage swings but increases the OFF state leak-age. However, the switch OFF leakage is alleviated using cascaded sampling technique asdescribed next.

In the presented prototype in 90nm CMOS, the majority of the transistors are sized 4times the minimum length or 0.36//m, and have a V T between lOOmV and 200mV acrosscorners in simu lation.


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2.3 Circuit Level Design Considerations43

2.3.1 Cascaded Samp ling Technique and SwitchesIn nano-scale CMOS technologies, sub-threshold MOS channel leakage, MOS gate leak-age, and reverse-biased PN junction band-to-band tunneling become more and more sig-nificant [62-64], At an ultra-low supply voltage of0.5V,MOS ga te leakage is substantiallyreduced since it is exponentially de penden t on the gate voltage. The reverse-biased PNjunction leakage becom es significant when the reverse biasing voltage exceeds the break-down voltage, which do esn 't occur with a 0.5V supply. The main leakage concern inthis design is the sub-threshold leakage of switches in their OFF state, particularly duringthe non-overlapping time between sampling and holding phases, when a capacitor is notconnected to any voltage source. This leakage causes signal dependent distortion in theswitched capacitor samp le and hold circuits.

To illustrate the effect of this leakage, a basic S/H circuit and the associated waveformsare shown in Fig. 2.8. Du e to the sub-threshold switch leakage, the output voltage V out isnot held constant when Si is OFF. In the worst case, assuming a rail-to-rail input signalat Nyquist frequency, V in changes from VDD to 0 after Si turns off; this puts Si in weakinversion and saturation. T he leakage current ISI.OFF ISthen given by:

W V tIs i .OFF OC - ^ 7 E X P ( N K T / ) ( 2 - 3 )


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44

* sr im ~V I N V o u t

(a)A Track Ho ld Track Ho ld

rv,V o u t

4

IT

(b)Figure 2.8: (a) Standard samp le-and-hold circuit (all transistors are sized as 12 /jm/0.36/imand Ci is lpF); and (b) associated node waveforms.


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45

Figure 2.9: (a) Proposed cascaded sam ple-and-hold circuit to combat switch OFF leakage(all transistors are sized as 12/im/0.36/im, C x is lpF and C2 0.25pF) and (b) associatednode waveforms.


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46

Figure 2.10:Simulation results for the sample-and-hold circuits in Fig. 2.8, 2.9 with rail-to-rail input showing the significant reduction of theeffectof leakage during the hold timefor the cascaded sample and ho ld compared to standard sample and hold.


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47where W /L is the transistor aspect ratio, V r is the threshold voltage, kT/q is the thermalvoltage and n is a technology dependent factor. Similar leakage challenges exist in eachstage of the pipelined ADC when the sample and hold switches are OFF. This issue is mostsevere in the first stage where noise and distortion should be kept well below LSB of thefull ADC.

To overcome this problem , a cascaded sampling technique is proposed to alleviate theswitch sub-threshold OF F leakage. An extra switch, S 2 , and an additional, smaller hold ca-pacitor C 2are used in fron t of the main sw itch Si and capacitor C i, as shown in Fig. 2.9(a).Switch SI and S 2operate during the same clock phase, but S2 is turned OFF slightly laterto ensure that it does not affect the accurate sampling on Ci . An intermediate voltage Viis now introduced which is held by the extra capacitor C 2 . During the track phase, bothswitches S I and S 2 are ON, andVOUTandV I trackV I N . In the hold phase,S I andS 2 are OFFand enter weak inversion. The difference between VOU T and V I is very small, but slowlygrows during the hold phase due to the leakage of S 2(see Fig. 2.9(b)). SI operates in weakinversion but in the linear region with a very small drain-source voltage Vd s,Si; the channelleakage current of Si is then:

Since Vds.Si rema ins very small, the O FF current in S I is very small and VOUT ISkept closeto constant during the hold phase. The simulation results in Fig. 2.10 show that the slope


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48of the output voltage fo r the cascaded sample and hold is about one tenth of the slope forthe conventional one. In the worst case leakage scenario, when the transistors are in thefast-fastprocess corner and operate at a temperature of85C,the proposed sampling circuitstill has a 4-fold reduction in leakage. In digital circuit, stacking of two OFF devices [65]are sometime s employed to reduce static channel leakage current. In our proposed cas-caded sampling technique, an extra capacitor is introduced to make sure the main switchremains in linear region when it is in OF F state, thus reducing channel leakage current moreeffectively.

Since there are two switches in series in the proposed scheme, the switch size needsto be increased. The extra sampling capacitor C2 can be kept much smaller than samplingcapacitor CI to limit the area overhead and settling time impact. C 2was setto or 250fFin this design. The leakage caused by the path connecting toVDAC during the non-overlapperiod does not introduce distortion since the reference voltages are constant.

Switch nonidealities result in important error contributions including settling errors,charge injection errors and clock feedthroug h errors. T he fully differential circuit topologylargely eliminates the latter two, but the voltage-dependent gate capacitance causes slightlydifferent errors in the two d ifferential paths. A switch design using a CM OS transmissiongate with \ sized dumm y sw itches was adopted to largely suppress clock feedthrough and

charge injection. To reduce the switch threshold voltage and improve settling during theON state, the switch-transistor gate and body terminals are shorted and connected to the


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49clock signal [56]. With a supply of only 0.5V, latch-up due to the forward biased bodyjunctio n is not a concern [66].

2.3.2 0.5V OTA Design

Figure 2.11: Schematic of the 0.5V operational transconductance amplifier. Device sizesshown in Table 2.1, The bodies of all transistors are shorted to their source terminals, exceptfor the bodies of M8A and M8B-

The residue amplifier is the most important active block in a pipelined AD C d esign. Toachieve 8bit resolution, the OTA DC gain in the first pipeline stage should exceed 50dB.Assum ing a feedback factor of 1/3, which takes into account the input parasitic capacitanceof the OTA, the GBW should be at least 18MHz to achieve a settling accuracy better than0.4% for a 10MH z sampling frequency.

A two-stage OTA with M iller compensation has been designed, as shown in Fig. 2.11.


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50

Table 2.1: Device sizes fo r the 0.5V OTATransistors W(yum) L(/im) Transistors W(Atm) L(/v,m)M I 150 0.36 M 6 A , M 6 B 18 0.36M 2 A , M 2 B 360 0.18 M 7 A , M 7 B 56 0.18

M 3 A , M 3 B 12 0.36 M 8 A , M 8 B 50 0.18M 4 A , M 4 B 12 0.36 M 9 0.4 4M 5 A , M 5 B 8 0.36 M10 1.2 1Resistors and CapacitorsR I A , R I B 500k0 C1A1 CIB 0.2pFR2A, R2B 30kfi C 2 A , C 2 B 0.2pFR 3 , R 4 C 3 ,C4 1.8pF

Figure 2.12: Biasing loops using an on-chip replica OTA to generate the bias voltagesCM 1, CM 2 and VBB for the OTA in Fig. 2.11.


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51The first stage (Mi-M^) uses a folded cascode topology to achieve higher gain, and acommon-source, second stage ( M 7 - M 8 ) is adopted to further increase the gain and to max-imize the available output swing. The input and output common-mode voltages are set to250mV. The sizes of the devices in the OTA are summarized in Table 2.1. As mentionedearlier, the transistors are sized with larger than minimum length to improve their outputimpedance and reduce their V T . The input differential pair transistors M 2 A / M 2 B have alength of only 2 times L m in to reduce their parasitic gate-source capacitance which affectsthe feedbac k factor; they are biased in weak inversion to maximize their (gm /I) and reducetheirVGSto leave sufficient headroom for the tail current source M i.

The OTA has a minimum single-ended output swing of 200mV p_p . The second stagehas a gain larger than 20dB (in simulation across corners) which results in a 20mV p_psingle-ended signal swing at the output of the first stage. In order to stack four transistors( M 3 - M 6 ) in the cascode stage, their overdrive voltage, (VGS V T ) , was designed to bearound lOOmV, resulting in a VDs,sat of about 80mV. For a 0.5V supply and a 20mV p_psingle-ended signal swing, each transistor in the stack can be allocated a nominal V Ds of120mV, which guarantees operation in the saturation region.

Two local common-mode feedback loops have been adopted so that the output com-mon mode of each stage is set to 250mV. A single common-mode feedback loop for the

full OTA is not suitable, since the output com mon-mod e voltage of the first stage wouldchange too much due to process, voltage and temperature (PVT) variations and affect theoperation of the cascode transistors M 3 - M 6 . Local common -mode feedback further offers


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easier control of the loop dynam ics and stability. In each stage, commo n-mode sensingresistors (R 1A & Rib, R2A & R2B) feed back the common-mode signals to the gates ofthe active loads. Shunt capacitors (CIA & C IB , C2A & C 2 B) improve the high-frequencycommon-mode feedback and maintain the common-mode gain well below OdB at higherfrequencies. M 9and MI0push a small DC current through the resistors to generate a voltagedrop that determines the DC output comm on-mode voltages. The appropriate bias voltagesfor nodes CM1 and CM2 to set the level shift currents and maintain the common-modevoltages at 250mV across PVT variations, are generated on-chip using servo loops acrossa replica OTA as shown in Fig. 2.12. For testing flexibility the servo loop error amplifierswere implemented on the PCB test board. The V G S of the output transistors M 8 A / M 8 B iskept at 250mV by the common-mode biasing and, due to PVT variations, the current inthe outpu t stage is not well contro lled. An on -chip bias circuit, also shown in Fig. 2.12,adjusts the body voltage of the output transistors to control their DC bias current. T he biasvoltages Vbp, Vbpcand Vbnc are generated on-chip using standard wide-swing cascode bi-asing circuits. Each of these bias circuits is implemented once on the prototype chip and isshared by all stages; they have been laid out next to the first stage in the pipeline since itsrequirements are most stringent.

The measured p erformance of the replica OTA on our prototype chip was a DC gain of50dB and a GBW of 32MH z for a differential load of3pF.Each OTA draws 530/uA undernominal conditions.


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532.3.3 Comparator

Com parator used in the stage sub-ADCs is shown in Fig. 2.13. A preamplifierisavoidedas described in section B. Besides, at 0.5V, simple differential pair preamplifier with diodeconnected transistor load hardly has any gain. K ick-back noise ofthecomparator is largelyisolated from residue output of previous stage by auxiliary SHA circuit.

Input transistors are sized four times the transistors connected to reference voltages.Thusdifferentialinput is essentially com paring to one quarter of Vref difference [57]. These


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54four transistors have larger W and L to improve their matching [67]. The com paratorconsumes 65 ^W at 5MH z sinusoidal input.

2.3.4 Non-O verlapping Clock GeneratorTwo non-overlapping clock signals at 10MHz are required to operate the pipelined ADC.Each c lock signal has two additional variations to minim ize charge injection, clock feedthroughand ensure accurate sampling. Fig. 2.14 shows the clock generator and waveform. The in-verter chain with feedbac k generates non-overlapped clock signal. Clock falling edge delayis mainly achieved by inserting NMOS M1-M4.

2.4 M easurement ResultsThe d ie photo and layout of the chip prototype is shown in Fig. 2.15. It was fabricated

on a 90nm CM OS process using regular V T devices. The chip size is 1.2mm x 1.2mm andactive area is 0.95m m x0. 9m m . The chip is covered by metal 9 fill structures; the mainchip sections are shown on the layo ut: eight identical pipeline stages, the clock generatoran dbuffer,and the OTA replica biasing.

The dies w ere packaged in a 64-pin QF P package and m ounted on a circuit board whichincluded the external voltage reference generators and the error amplifiers for the biasingloops. A Tektronix AWG 2021 arbitrary wa veform generator provided the differential inputsignals, and an Agilent 33220A generated the input clock; an Agilent 1692AD logic ana-


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55

0 1 a 4>4 f A

'la

ld

01010101010

(a)TV

11

(b)

VDD

^ V

Figure 2.14: (a) Non-overlapping c lock generator, the advanced and delayed clock phasesare achieved by inserting NMO S M I-M 4; (b) Two clock phases with advanced and delayedversions from the clock generator.


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56

Figure 2.15:Die photo (left) and layout plot (right).lyzer collected the uncorrected bits from all the stages. The digital offset correction wasperformed off-line.

Fig. 2.16 shows the digital output spectrum for a full-scale, 109kHz input signal whileoperating from a 0.5V supply and sampling at lOMS/s. The third order harmonic is -57dB below the signal. This distortion is probably d ue to the finite gain of the OTAin the residue amplifier or possibly due to capacitor mismatch. The signal-to-noise ra-tio (SNR), the signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamicrange (SFDR) forfull-scaleinput signals withfrequenciesrangingfrom101kHz to 4.9MH zis shown in Fig. 2.17; the dynam ic perform ance of the converter is quite flat with about a4dB drop in the SNDR at the Nyquist frequency. This illustrates the effectiveness of theadopted pipeline stage topology using an additional coarse sub-ADC S/H while eliminatingthe front-end SH A.


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57

0

- 2 0

-40o

Frequency [MHz]Figure 2.16:M easured output spectrum at lOMS/s with afull-scale109kHz sinewave inputusing a 16384-point FFT.

The A DC 's SNR , SNDR, and SFDR are very consistent for sampling frequencies rang-ing from 100kHz to 10M Hz, as shown in Fig. 2.18. This demonstrates that the switchleakage of the cascaded sampling circuit is not significant even at lOOksps. The ADC isalso characterized with varying input signal amplitudes from -45dBFS to OdBFS, Fig. 2.19shows the corresponding SNR, SNDR, and SFDR. The static performance of the ADCwas determined by taking 2048 sam ples at lOMS/s of a full-scale ramp input signal and isshown in Fig. 2.20; the maximum |DNL |and |INL |is 0.55 and 1.19 LSB respectively.


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58

70605040m"O302010

00 1 2 3 4 5Input Signal Frequency [MHz]

Figure 2.17:M easured SNDR , SNR, SFDR at lOMS/s for afull-scaleinput sinewave withfrequencies varying from 101kHz to 4.9MHz.Table 2.2 summ arizes the measured results including the performance for 10 % supply

voltage variations; the performan ce is consistentfrom0.45V to 0.55V, with less than 1.9dBdifference. The chip was further tested at 80C and a degradation of less than 3dB in theSNDR d egradation w as observed for 0.5V and lOMS/s operation. The pipelined ADCnominally consum es 2.4mW from a 0.5V supply. Ten chip samples were tested and thevariation in their SNDR pe rformance was within a 0.75 dB range.

A comparison of the su b-l V ADC s with different architectures is shown in Table 2.3.

W v

- $ - S F D RiSNR- - S N D R- $ - S F D RiSNR- - S N D R


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59

m

70605040302010

0

. A A 0 : iy v ^ be 6 1 1 - discharge


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Pipelined AD C using dy nam ic source follower residue amplification [30]This architecture is based on the dynam ic source follower. Com pared to the traditionalOTA-based MDAC circuit, this design charges the load capacitor dynamically and thussaves considerable power. Fig. 3.2 shows the basic operation of the adopted dynam icsource follower amplifier. During the sampling phase, the MOS transistor is biased indepletion region; during the amp lifying phase, the transistor acts as a source follower andthe output capacitor is being charged until V gs approaches V t . The charge redistributionfrom the uniquely configured sampling phase to the amplifying phase, together with thevoltage dependent transistor parasitic capacitors, provides passive voltage gain. One of thedrawbacks is that the gain achieved in this approach is not accurate, since it relies on theratio of nonlinea r transistor parasitic capacitors. Thus gain calibration is required to restorethe performance. For the similar reason, the accuracy of the sampled signal is limited toaround 8bit level under 1.2V supply. The half circuit pseudo differential stage implemen-tation is shown in Fig. 3.3, where it shows how the reference voltages are precharged in thesampling phase and applied in the amplifying phase. A small Ibieed is introduced to avoidslow settling when the MOS transistor enters subthreshold region.

Pipelined A DC using com parator-based switched-capacitor circuits [18]The m ain differenc e between th e comparator based switched capacitor (CBSC) pipelinedAD C and the traditional OTA based o ne is the way to take advantage of the virtual ground


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77

(b)

(C)Figure 3.4: Com parator based switched ca pacitor circuit, a comp arator and a currentsource is adopted to replace the OTA in a traditional implem entation. Outpu t voltage isobtained when the comparator virtual ground is detected and the comparator output tog-gles [18].to realize a precision gain. The traditional OTA based switched capacitor circuit forces

the input of the OTA to virtual ground in a feedback configuration, which requires a highgain and high GBW OTA. The CBSC circuit replaces the OTA with a comparator and acurrent source, which is shown in Fig. 3.4. Now, instead of forcing V x to virtual ground,the comparator monitors the voltage V x while the current source Ix is on, and turns off Ixwhen V x crosses the virtual ground, when the output voltage VQ is finalized and held onCL- Note that in this scheme, it operates as a class-B circuit where all the current fromthe current source goes to the load capacitors. Assuming the comparator has no delay, ifwe apply charge conservation rule at node V x , we will get the exact same V 0as the OTA


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78based switched capacitor circuit. The CBSC technique can be applied to all the circuits thatswitched-capacitor loads are driven. One of the main downsides is that the finite delay ofthe comparator will cause output voltage overshoot, which requires a fine current source tocorrect the error.

In short, the CBSC based pipelined A DC reduces the design complexity and increasesthe powerefficiencyby replacing the OTA with a comparator and a current source.

Charge-dom ain pipeline ADC using bucket-brigade circuitry [29]VcVPCH 9

E f i f e * r > aQNp9N I 1 . 1 , 1 T U^ o i 9 I QOUTP

QOUTP- GINP+{VPCH- Vo)(Cc+ CR)- VCCC-BCRVR^ o i 9 J _

Q OUTM= Q,NM+ (VPCH- V0)(CC+ CB) ~ VCCC- BCRVR

QiNM-at-

AQOUT = QOUTP- QOUTM - AQIN+ (B-B)CRVRQCM.OUT = VZ(QOUTP+QOUTM)=QCMIN+(VPCH- V0)(CC+ CR) - VCCC- 540RVR

VPCH

vc37 LiQ _ _ fx. Tj QOUTMNotes:1. C RP = C R M = Cr ;B=1 or0;B =1 - B2. P arasitic capacitances are neglected

O U T P U TB I T S

Figure3.5: 1bit charge domain pipelined ADC stage [29].

This pipelined A DC uses charge domain signal processing. The stage architecture of


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79the ADC is shown in Fig. 3.5. The advantage of this design is that charges are beingreused efficiently, as charge packet drawn from the supply is passed from one stage tothe next. Stage transfer function for differential charge is similar to the voltage transferfunction of the traditional MDA C-based stage , but there is no charge gain. To achieveinterstage voltage gain so that the offset requirement for the sub-ADC and the accuracyrequirement for the later stages are relaxed, the capacitors of the following stage are scaledproportionally. To maintain the CM voltage for each stage, the CM charge needs to bereduced fro m stage to stage, which is controlled by a feedback loop in this design. Thehigh performanc e of the pipelined AD C is also aided by the power-up calibration to adjustfor various circuit p arameters.

Pipelined ADC using capacitive charge-pumps [31]

Figure 3.6: Capacitive charge-pump based pipelined ADC stage[31].


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80This architecture realizes the stage gain using capacitive charge-pumps, by sampling

the input to two identical capacitors and then stacking them on each other, a gain of 2 isachieved. Fig. 3.6 shows the stage implementation with clock phases. Compared with thetraditional OTA based approach, this approach breaks the trade off of gain and bandwidthrequirements by using a separate wi

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