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Workshop for Electron Beam Lithography System
JBX-6300FS
By Nelson LI 13 November 2009
Nanoelectronics Fabrication Facility
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1. System specifications2. Importance of chip feature on writing
result3. Requirements of overlay writing4. Photoresist provide5. Requirements of pattern design6. Exposure result7. Charging scheme
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1. System specifications
• System model
• Basic specifications
• Substrates supported by system
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System specifications
Manufacturer : JEOLModel No : JBX-6300FS
SYSTEM MODEL
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System specification
Specifications
Writing mode High speed or high precision
Beam Current 30pA to 20nA
Scanning Speed 12M to 250 Hz
Accelerate Voltage
20, 50 or 100 kV
Max. Field Size (um2)
High speed mode: 2000 (20kV), 1000(50kV) or 500 (100kV)
High precision mode: 250 (20kV), 125(50kV) or 62.5 (100kV)
BASIC SPECIFICATIONS
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System specifications
SUBSTRATES SUPPORTED BY SYSTEM
Substrates Size
Mask 5”x5”x0.09”
Wafer 4”, 3” or 2”
Nano-imprint mask 65mm x 65mm x 6.35mm
Chip sample 2cm x 2cm, 1.5cm x 1.5cm or 1cm x 1cm
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2. Importance of chip feature on writing result
• Cassette to mount chip
• Cases of improper chip feature i, chip with rough edge ii, chip with incorrect size
• Requirements of chip feature
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Importance of chip feature on writing result
Cassette to mount chip: Picture of cassette
Back of cassette Front of cassette (writing side)
Grounding pins
Positioning pins
Chip backside
Chip surface with PR
Exposure window
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Cases of improper chip feature
Chip with rough edges
Cassette back Cassette front (writing side)
Problem:i, Grounding pin cannot touch on sample surfaceii, May cause rotation error
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Cases of improper chip feature
Chip with incorrect size
Cassette back(for 15mm x15mm)
chip)
Cassette front (writing side)
Problem:Exposure area shift from center of chip
Exposure window
18mm x 18mm chip
Exposure window
Exposure window center
Chip center
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Importance of chip feature on writing result
Requirements of chip feature
• Straight and smooth cutting edge
• Square shape with orthogonal angles
• For overlay writing, patterns of previous layer should be located at the center of chip
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3. Requirements of overlay writing
• Feature of Global and Chip alignment marks
• Positions of Global and Chip alignment marks
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Requirements of overlay writing
Feature of Global and Chip alignment marks
L
W
Global Mark: L= 1500 μm
W = 3 μm
Chip Mark: L= 20 μm
W = 3 μm
Etch depth of Mark: 1≧ μm
Page 14Positions of Global alignment marks on wafer
L
Requirements of overlay writing
Wafer
•For 4” wafer, L 40.5mm≦
•For 2” wafer, L 19mm≦
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Requirements of overlay writing
Positions of Chip alignment marks on wafer
Four chip alignment marks located at 4 corners of writing chip M1, M2, M3 and M4 respectively.
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4. Photoresist Provide
• Positive photoresisti, ZEP-520A
(thickness ～ 400 to 100nm)ii, ZEP-7000
(for mask, thickness ～ 400 to 150nm)iii, PMMA950-A2 (thickness ～ 180 to 80nm)
• Negative photoresisti, AR-N7520.18 (thickness ～ 400nm)ii, AR-N7520.073 (thickness ～ 100nm)
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5. Requirements of pattern design
• File format, pattern sizes and pattern area
• Pattern samples
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Requirements of pattern
Pattern sizes and file format
• File format: GDSII
• Total number of vertex point per polygon 600 ≦
• Pattern sizes(line width or gap size) 100nm≧
• Pattern Complexity ↑, file conversion time ↑
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Requirements of pattern
Pattern sizes and file format
• Problems of larger exposure area i, long writing timeii, high risk of field stitching error due to laboratory temperature fluctuation
Stitching error
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Requirements of pattern
Pattern sizes and file format
iii, Proximity error
Correct expose
Over expose
100 μm
120 μm
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Requirements of pattern
Pattern sample 1
1500 μm
1500 μm
Chip area: 1500um2
Exposure area: 11.51% of Chip area
Exposure time: 10.4mins
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Requirements of pattern
Pattern sample 2
500 μm
500 μm
Chip area: 500um2
Exposure area: 11.51% of Chip area
Exposure time: 1min
0.2 μm line width
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Requirements of pattern
Pattern sample 3
500 μm
500 μm
Pattern conversion fail!
0.1 μm x 0.2 μm polygon
100 μm
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6. Exposure result
• Pattern sample 1
• Pattern sample 2
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Exposure result
Pattern sample 1: Shot bar pattern
ZEP-520A (+) ma-N2403 (-)
80nm line width
100nm line width
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Exposure result
Pattern sample 1
ZEP-520A (+) ma-N2403 (-)
100nm line width
100nm2 square pattern
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Exposure result
Pattern sample 1
50nm line patterns with 0.3 ° rotation angleZigzag patterns with 100nm line width
ZEP-520A (+)
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Exposure result
Pattern sample 2
ZEP-520A (+) ma-N2403 (-)
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7. Charging Scheme
• Definitions of Short and Long jobs • Charging for internal users
• Charging for other HK Institutions
• Charging for external users
• Job submission procedure
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Charging Scheme
Charging Scheme: Definition of Short and Long jobs
•Short job: Exposure time ≦ 3hrs
•Long job: Exposure time ﹥ 3hrs
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Long Job(HK$) Short Job(HK$)
5”x5” soda lime mask 2244 1494
5”x5” quartz mask 2814 2064
Wafer or chip sample 2232 1482
Nano-imprint mask 2746 1996
Charging Scheme: Charging for internal users
Charging Scheme
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Other HK Institutions External UsersLong
Job(HK$)Short
Job(HK$)Long Job(HK$) Short
Job(HK$)
5”x5” soda lime mask
5074 4204 11376 7355
5”x5” quartz mask
5735 4865 12037 8016
Wafer or chip sample
5060 4190 11362 7341
Nano-imprint mask
8127 7257 14429 10408
Charging Scheme: Charging for external users and other HK Institutions
Charging Scheme
Remark: Price includes 16% administration fee
Page 32Job submission procedure: internal users
Charging Scheme
The price list of substrates will post on website on coming Monday!
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1. Go to www.nff.ust.hk
2.
3.
Charging Scheme
Job submission procedure: for external users and other HK Institutions
4.
Page 34Job submission procedure
Contact Information :
Name: Nelson LIEmail : [email protected]
Thankyou
Nanoelectronics Fabrication Facility
