Paper ID #6798

Introducing Nanoelectronics into the Electrical Engineering Curriculum

Prof. David H Hoe, University of Texas, Tyler

Dr. David Hoe is an Assistant Professor in the Electrical Engineering department at the University ofTexas at Tyler since 2008.

c©American Society for Engineering Education, 2013

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Introducing Nanoelectronics into the Electrical Engineering Curriculum

Abstract Engineering programs that have introduced nanotechnology into their curriculum typically add material into core classes or have added a separate set of nanotechnology courses. Increasing the number of courses can be a challenge for colleges with limited resources and faculty and it is not easy to make significant changes to the curriculum all in one step. This paper looks at an alternative that is being introduced at the University of Texas at Tyler. The goal is to introduce nanotechnology into select courses while minimizing changes to the curriculum for ease of adoption. The proposed solution is to introduce nanoscale design concepts into existing classes which teach microelectronic-related topics and where nanotechnology will revolutionize the way these circuits are built in the near future. An advantage of this approach is that the students have a prior context to build upon. They can see how state-of-the art microelectronic circuits are currently designed while comparing and contrasting it with the paradigmatic shift offered by nanoelectronic devices. This juxtaposition of technologies is appropriate since a number of proposed nanoelectronic circuits are built upon similar principles and topologies used in current microelectronic technologies. This paper overviews the initial attempts at such an integration in an introductory digital integrated circuits course. Evaluation of this effort through student self-assessment surveys, concept inventory quizzes, and exam and project scores are reported. Plans to improve upon future offerings are also detailed. Introduction Ongoing research in nanotechnology is revolutionizing several fields, including microelectronics, biotechnology, and materials science. It is predicted that by 2020, nanoscale engineering will bring about mass applications in industry, medicine, and information technology.1 As a result, a growing number of scientists and engineers with the ability to create innovative designs using nanotechnology will be required. This is creating an urgent need for curriculum enhancements right now in STEM education. This paper focuses on the impact that nanotechnology will have in the area of microelectronics, one of the main economic drivers of this information technology age. The ability to shrink electronic devices down to submicron dimensions has made possible Very Large Scale Integration (VLSI) circuits. For over four decades, the microelectronics industry has continued to increase the number of devices that can be fabricated on a single silicon-based substrate known as an integrated circuit (IC). Continued advances in processing technology have allowed transistors to be fabricated with feature sizes in the nanometer scale. However, upcoming limitations in traditional fabrication methods combined with the quantum limitations on device operation threaten to put an end to the continued shrinkage of device geometries. Innovations in nanotechnology-based fabrication methods promise to allow future advances in device performance in the coming years. Thus, it is essential to introduce our students to the new paradigm shift that is already occurring and that promises to transform the microelectronics field in the near future.

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Several studies have looked at introducing nanotechnology as entry-level classes in the engineering curriculum. For example, Mendelson et al. discuss the development of a sophomore-level course “Introduction to Nanotechnology” that focused on three applications from a biological perspective: micro-arrays, micro-fluidics and nanostructures.2 Another paper reports on the integration of nano-learning modules into a couple of materials science classes at the sophomore-level.3 Some institutions have discussed the implementation of specific classes at the more advanced level devoted to nanotechnology. For example Pai et al. discuss the introduction of two graduate-level classes that cover the growth and characterization of emerging nanomaterials.4 Uddin and Chowdhury describe a comprehensive plan for integrating a set of courses into the undergraduate engineering curriculum.5 This paper advocates an approach that integrates nanoelectronics material into an existing integrated circuits design course. This is a viable approach for several reasons. First, it is an attractive approach for a smaller-sized institution that may not have the resources for implementing a full set of separate nanoelectronics courses. Second, it is often not easy to make wholesale changes in the curriculum to accommodate a separate set of nanotechnology classes. And third, the proposed approach provides a stimulating introduction to nanoelectronics that can further motivate students to take more advanced courses in this area either as senior technical electives or in graduate school. Such motivation will help contribute to the growing need for graduates who are well qualified to work in the rapidly evolving area of nanotechnology. The University of Texas at Tyler currently has an Introduction to VLSI Design class that exists as a senior elective in the electrical engineering undergraduate curriculum. The class introduces the students to the essential principles of designing digital integrated circuits (ICs) using conventional silicon-based technologies. This paper reports on our initial attempts to integrate nanoelectronics design principles into the existing fabric of the standard course. The approach discussed in this paper is unique in several ways. First, the students are introduced to nanoelectronics while learning the design principles of basic VLSI design. It is argued below that this juxtaposition provides an effective method for teaching this material. Second, the students read extensively in research journal papers for state-of-the-art approaches. Third, a combination of traditional lecture and active-based learning methods are utilized to teach this material. Fourth, assessment instruments such as concept inventories and surveys are developed to evaluate the implementation of these initiatives. This paper is outlined as follows. First, an overview of the current VLSI Design course is described and areas where nanotechnology topics are introduced are highlighted. Next, the overall strategy for integrating the nanoelectronics components into the VLSI course is given. Then the assessment methods and results are discussed from this past fall semester. Finally, some conclusions and future plans are described. Course Overview This section provides an overview of the VLSI Design class offered at our institution and highlights the areas where nanoelectronics principles were introduced. The idea is to teach the students first the basic theory and design principles used in conventional silicon-based electronics and then introduce the students to the corresponding nanotechnology-based devices and circuits. This juxtaposition of technologies is appropriate since a number of proposed circuits are built upon upcoming nanotechnologies such as carbon nanotubes and silicon nanowires that

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utilize similar principles and topologies currently in use. In addition, a feasible near-term solution is to manufacture hybrid nano-microelectronic circuits. The VLSI Design class introduces students to the basic concepts of integrated circuit design utilizing the most common device technology, Complementary Metal-Oxide-Semiconductor (CMOS) transistors. The emphasis is on digital design methods, as outlined in a popular textbook.6 Table I summarized the main topics covered and highlights where nanotechnology-related issues were introduced. The basic strategy of juxtaposition is evident in four key areas: CMOS processing versus nanoscale device fabrication (Lectures 3 and 4); device structure: silicon versus carbon nanotube Field Effect Transistors (FETs) in Lecture 6; logic circuit design: CMOS pass-transistor logic design versus CNT logic design (Lecture 13), and issues with interconnect (Lectures 5, 10, and 11). The use of journal articles and active learning activities to introduce the nanotechnology issues are discussed in the next section.

Table I. Topical Overview of the VLSI Design Class

VLSI DESIGN TOPICS NANOTECHNOLGY TOPICS

1. Introduction to VLSI Design Designing Basic CMOS Logic Gates

2 Designing Complex CMOS Logic Gates CMOS Processing Technology – Design Rules

3. CMOS Layout Short-channel effects

4. Submicron FET characteristics Processing – VDSM CMOS

Lithography for Future Technologies Leakage in CMOS devices

5. Delay Modeling RC delay for FETs and Interconnect

Interconnect Scaling Impact on Microprocessor Design

6. Logical Effort MOSFET vs CNT-FETs

7. Logical Effort – complex circuits Carbon nanotube materials/devices

8. Midterm Exam

9. Power Dissipation Low Power Deign Methods

10. Circuit Simulation with SPICE Noise issues with nano wires

11. Interconnect – Energy tradeoffs Interconnect for nanoelectronics: 3D, optical, wireless, carbon nanotube

12. CMOS Logic families: Ratioed Circuits

13. CMOS Logic families: Pass Transitor Logic and CVSL design

Assessment of Intel LVS circuit in carbon nanotube technology

14 CMOS Logic families: Dynamic Logic Clock distribution case study

15. Circuit Robustness and Testing Issues

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Implementation Strategy The introduction of nanoelectronics topics into the VLSI Design course was implemented using two main strategies. First, extensive reading of relevant journal articles was required. The use of journal articles ensures that up-to-date material is available as nanotechnology is a rapidly advancing field. Since undergraduates students typically do not have much experience in reading scholarly articles, introductory overview articles were carefully selected. The students also require guidance in highlighting the important points and critically evaluating the article. This was implemented as part of the in-class learning exercises discussed below. Second, the VLSI class utilizes a mixture of traditional lecture and active learning methods. Both methods were utilized in teaching the nanotechnology-based material, although the focus was on using active learning methods. Active learning places an emphasis on the learner being actively engaged in constructing his own knowledge and has been shown to be more effective than traditional methods of content delivery.7 Active learning methods that were employed include the use of peer interaction thought questions and group exercises, and in-class discussion of case studies. Examples of how journal articles and active learning methods were utilized are discussed in context of the four key areas that involved the comparison of conventional VLSI and nanotechnology-based devices. These key areas cover device fabrication, device structure, circuit design, and on-chip interconnect. 1) Fabrication. A lecture on the photolithography process for fabricating silicon-based integrated circuits was given in the second class. In the fourth week, the students learned the limitations of this top-down fabrication method for nanoscale geometries due to its reliance on optics and masks. Readings were assigned from an article by Pease and Chou, “Lithography and Other Patterning Techniques for Future Electronics.”8 This Proceedings of the IEEE article discusses the challenges and advances made in optical lithography. The lecture covered the salient points from the article and the students were assigned a homework problem to read the section on non-radiation-based lithography, and in particular to describe the advantages and disadvantages of nanoimprint lithography. For the fourth lecture, the students also read the article, “Leakage in CMOS Circuits – An Introduction.”9 As an example, the small group exercise to chart the various sources of leakage that impact nanoscale FETs is shown below:

Plot the approximate values for the various leakage components using the following:

1. Figure 2 for VG = 0.1 V

2. Table 3 for 90 nm and 25 nm

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Estimate the power dissipation for an IC with one million FETs assuming each FET has the leakage components given in Table 3 for the following cases:

1. 90 nm node for VDD = 1.5 V

2. 25 nm node for VDD = 0.85 V 2) Device Structure and Performance. The students were introduced to the basic structure and process cross-section of the conventional MOSFET as well as the basic principles of the device’s operation in the second lecture. For lecture five, the students were assigned the article by Bourianoff, “The Future of Nanocomputing.”10 Three issues were discussed by the students in groups during the class. First, they were asked to compare the structure of the silicon MOSFET with the new Intel FinFET. Second, the similarities and differences between the silicon MOSFET and carbon nanotube transistor were examined. Third, the concept of self-assembly for silicon nanowires was discussed. The instructor discussed all the points with the class as a whole after the groups had time to review the paper and answer the questions themselves. Also, some novel nanotechnology systems such as quantum computation and quantum cellular automata were briefly discussed. In week 7, the students were given a lecture that introduces them to the general properties of carbon nanotubes (CNTs) and the concept of ballistic transport. An article that overviews nanoelectronics devices, “The Future of Integrated Circuits: A Survey of Nanoelectronics”11 was assigned as reading for this class. This explains the advantages of using CNTs as both an active device and a passive interconnect. An in-class exercise presented the students with a set of device data to analyze and then a series of thought questions guided the students to consider the advantages of the CNT FETs over their silicon counterparts in terms of device performance (e.g., current drive) and reliability. An excerpt is provided here:

Comparison of CNT FETs to Silicon and SOI MOSFETs12

Thought Question: what is interesting about the CNFET vs MOSFET performance?

Hint: note the physical dimensions.

The answer the students should observe is that the CNFET is able to outperform both the current and newer technologies despite the larger gate length and gate oxide thickness. 3) Circuit Design. In the context of different CMOS logic families in lecture 13, the students were introduced to a proposed circuit design using carbon nanotube devices based upon the

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paper by Liu et al., “Intel LVS logic as a combinational logic paradigm in CNT technology.”13 This was appropriate for this lecture since the topic covered a differential logic technique known as Cascode Voltage Switch Logic (CVSL). The proposed LVS logic adapted to CNT technology by Liu builds upon this principle using CNT FETs instead of silicon MOSFETs. The students discussed in groups the advantages and disadvantages of the proposed CNT circuit and were asked to critically assess the claims of the paper. The exercise is illustrated below:

Observations from Liu (2010) paper

1. What are the reasons for the dominance of static CMOS?

2. What are the two key advantages of LVS technology? 3. Are there any disadvantages? (Consider the note in textbook)

4. How would you assess the claims in this paper? What should a further evaluation include?

In this case, the students were guided to observe that the overhead due to the clock is not considered and that more sophisticated circuits are needed to validate the claims of the paper. 4) Interconnect. As processes are scaled to nanometer dimensions, the performance of the interconnect becomes a critical factor in designs for two reasons. First, from the standpoint of performance, the interconnect delay becomes more significant than logic gate delay. Second, with respect to reliability, sources of deep submicron noise and reduced voltage swing become a critical issue. In the context of calculating the RC delay of FETs and wires in lecture 5, the students are introduced to the impact of interconnect scaling on circuit-level optimization through reading the article by Flynn et al., “Deep submicron microprocessor design issues.”14 Small group discussions moderated by the instructor enabled the students to realize the major technical challenges associated with on-chip interconnect for deep submicron (DSM) technologies. A follow-up homework question asks the students to read and understand a paper on the reliability issues associated with DSM processes.15 Subsequent lectures in weeks 10 and 11 deal with coding methods to improve delay and reliability of interconnect, and the performance-energy tradeoffs for different on-chip communication schemes. The lectures are based on recent methods described in the literature.16,17 Furthermore, a brief lecture during week 11 introduced the students to some future technologies for on-chip interconnect, including optical and wireless technologies, and the use of CNT wires.18 Assessment An assessment of introducing nanoelectronics into the VLSI class are discussed in this section. The methods used include student self-assessment through surveys given throughout the semester, concept inventory tests, and performance on tests and a course project.

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Student Self-Assessment: Surveys were given to the students at four times during the semester to gauge their attitudes towards the introduction of the nanoelectronics material and towards the active learning methods. In lecture four, the students were asked about their understanding of leakage mechanisms in submicron CMOS devices through reading of the article by Helms et al.9 and participation in the peer interaction exercise. Table II summarizes the results. A total of 13 students submitted the survey for this assessment.

Table II. Student Attitudes towards peer interaction on leakage currents

(Scale: 1= Strongly Disagree, 2= Disagree, 3 = Neutral, 4= Agree, 5 = Strongly Agree)

Statement Rating

1. I gained a better understanding of the various leakage mechanisms in submicron CMOS by either explaining it to one of my peers or listening to an explanation from one of my peers.

3.9

2. I find it beneficial to interact with the material from the journal articles for learning the subject matter

3.8

The students were also asked to rate the various learning methods used for that lecture period on a Likert scale.

Table III. Student Attitudes towards teaching methods (1) Not very useful (2) Not useful (3) Neutral (4) Useful (5) Very useful

Statement Rating

1. Taking notes on handout (Gate capacitance, CMOS process). 4.5

2. Peer interaction (Leakage in CMOS) 3.4

3. PowerPoint + Whiteboard (Inverter DC Transfer) 3.4 Not surprisingly, the students preferred more traditional methods of learning that they were most familiar with. This class was one of their first experiences in peer interaction. A question on the survey asked the students to list the topic that was most unclear. The majority actually listed the leakage components covered in the journal article. A follow-up question asked the students the degree to which they had read the journal article on leakage before coming to class, and most of them admitted to only skimming the article. While this was an introductory level article, it was rather lengthy (19 pages) and it was first time the students were asked to read a journal article before coming to class. The lecture in week 7 dealt with introducing carbon nanotube materials and devices. The students were surveyed on their attitudes towards the peer interaction exercises. A total of 15 students submitted surveys this time.

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Table IV. Student Attitudes towards peer interaction on carbon nanotubes

(Scale: 1= Strongly Disagree, 2= Disagree, 3 = Neutral, 4= Agree, 5 = Strongly Agree)

Statement Rating

1. I have a better understanding of carbon nanotubes from either explaining it to one of my peers or listening to an explanation from one of my peers.

3.9

2. Compared to the other peer interaction exercises, today’s exercise was more helpful in terms of gaining a conceptual understanding of the material.

3.4

3. I think it is a good idea to introduce nanotechnology concepts into this course.

4.3

4. I think it is a good idea to interact with journal articles for learning nanotechnology.

4.3

The student attitudes towards learning from their peers remained about the same while there is some improvement in attitude towards reading the journal articles. Part of this could be that they have more experience now with reading a journal article, but additional factors include the use of a more introductory-type article and the students were given instructions on what areas to focus on in their readings this time. This is reflected in one student’s written comments in the survey, “I like the more focused nature when looking at this journal article this week. 4-6 pages is optimum for general reading.” The students generally agree with the third statement on the survey, indicating the value they are seeing in learning nanotechnology concepts. During week nine, an extensive in-class exercise involved studying the tradeoffs found in various low-power architectures. The students were asked to read a classic article in this area, “Low-Power CMOS Digital Design.”19 The active learning exercise guided the students to understand the tradeoffs in power dissipation, performance, and circuit area by using parallelism and pipelining. While not strictly a nanoelectronics topic, a survey was given to assess the students attitudes towards the group learning exercise, as this was the most extensive in-class exercise and it gives a useful point of comparison with the other nanotechnology-themed exercises. A total of 16 students submitted surveys and their results are summarized in Table V.

Table V. Student Attitudes towards low power case study

(Scale: 1= Strongly Disagree, 2= Disagree, 3 = Neutral, 4= Agree, 5 = Strongly Agree)

Statement Rating

1. In general, peer-to-peer interaction was helpful in trying to learn this material.

3.9

2. Specifically, I was able to get a better grasp of this material by either explaining it to one of my peers or listening to an explanation from one of my peers.

4.0

3. I would like to see more small group activities in my classes. 3.9

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The results show the student attitudes remain about the same, generally positive towards the in-class learning exercises. A follow-up question on the extent to which they read the journal article again indicates that most admitted to just skimming the article. In written comments submitted along with the survey, one student noted the reason for skimming the article was due to its length and position right after the midterm. It should be noted that after the students worked through the exercises and discussed the answers with their peers, the instructor would get responses and go over the correct solution. As one student noted, though, the initial impression of working with the peers carried weight: “I don’t like this method because if other classmates are confused then they give the wrong idea which seems to stick rather than the right idea.” One more survey was taken during week 13, where the lecture covered various CMOS logic families and introduced a carbon nanotube circuit described in the journal article by Liu et al.13 First, the students were surveyed on their attitudes to learning the various circuit approaches – the first two are silicon CMOS and the third is the CNT circuit. For a point of comparison, this exercise was also carried out in a graduate-level VLSI class (EENG 5334). The results are summarized in the table below.

Table VI. Student Attitudes towards learning circuit approaches (1) Not very useful (2) Not useful (3) Neutral (4) Useful (5) Very useful

Statement Rating EENG 4331

Rating EENG 5334

1. Design of a CVSL gate (2 input XOR). 4.2 4.2

2. Understanding pass transistor logic 4.2 4.2

3. Liu (2010) paper - CNT using Intel LVS 3.3 3.6

N (number of students) 17 18

VLSI Classes: 4331 = undergraduate, 5334 = graduate While all three activities listed involved some degree of peer interaction and active learning components, the last one involved reading the Liu paper and critically assessing it. The students perceived this to be the least useful. From the ensuing class discussion, the faculty concur with this observation. The students at this point need additional guidance in what to look for and how to critically assess the paper. The graduate students rated the third activity a bit higher, but also seemed to struggle with the critical assessment. The students in both groups were also asked to rate their interest and appreciation of the peering interaction. The results were consistent with previous survey results: 4.2/5 for peer interaction, although interest in nanotechnology had dropped to 3.7/5 for the undergraduates. A final end of semester survey was given. This was included with the usual formal survey that is typically handed out. The surveys are not turned into the instructor, but transcribed by the administrative staff, so the students can have more confidence that their results are anonymous. The table below summarizes student attitudes towards the different styles of learning. A total of 16 students participated in this survey.

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Table VII. Student Attitudes towards teaching methods (1) Least Helpful (2) Not very helpful (3) Neutral (4) Somewhat helpful (5) Most helpful

Statement Rating

1. Listening to a lecture/taking notes 4.1

2. Reading the textbook 3.3

3. In-class activity – working on a problem individually 3.4

4. In-class activity – peer interaction 4.1

5. Professor working out example in class 4.6

6. Doing the homework 4.3

7. Doing the course project 2.9 The activities led by the professor (categories 1 and 5) rated highly. Of note, the students did see value in peer interaction over working individually (categories 3 versus 4). This is significant, as the majority of the active learning peer exercises involved nanoelectronics-based material. The students were not as excited about the course project, which involved doing simulation with submicron device models and assessing the impact of scaling on various logic families. The results from the evaluation of the course project are described in the next section. The students were also asked to self-assess their understanding of ten topics presented throughout the semester. The results are summarized in the following table, where a Likert rating scale was used.

Table VIII. Student self-assessment of understanding key topics

Statement Rating

1. Designing with static CMOS logic 3.8

2. Designing with dynamic CMOS logic 3.4

3. Designing with pseudo-nMOS/pass transistor logic 3.4

4. The rationale for using various layout design rules 3.6

5. CMOS processing technology 3.6

6. Lower power design procedures in CMOS 3.0

7. Issues with scaling FETs to nanoscale dimensions 2.9

8. Carbon nanotube FETs and wires 3.3

9. Advanced interconnect technologies 3.1

10. Use of coding to improve signal transmission 2.9

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The first five topics are covered in a traditional VLSI Design course. As the material is covered in the textbook and a fair amount of lecture time is devoted to these topics, it is not surprising that the students self-assessed these topics the highest in terms of their understanding. Of the nanoelectronics topics listed in categories 7 to 10, the students believed their understanding of carbon nanotubes and wires rated best. This correlates with the fact that several lectures and learning activities were devoted to this topic, as CNT nanotechnology is considered one of the front-runners to eventually replace silicon-based IC designs. A similar amount of time was spent on topic 7 (scaling of FETs to nanoscale dimensions). The complexity of the topic may have been the reason for the low score. This was an important part of the course project, and the low rating in Table VII is consistent with the performance on the course project, as discussed below. As reading from the journal articles was an important component of learning nanotechnology, the students were asked to rate their attitudes towards interacting with the articles. The results are summarized in Table IX.

Table IX. Student Attitudes towards journal articles

(Scale: 1= Strongly Disagree, 2= Disagree, 3 = Neutral, 4= Agree, 5 = Strongly Agree)

Statement Rating

1. The in-class activities and interaction helped me to better understand the articles.

3.9

2. From the in-class discussions, I have learned to better critically assess the articles.

3.6

3. Rate the amount of journal article reading and interaction appropriate for this course.

2.6

4. I think it is a good idea to interact with journal articles for learning nanotechnology.

3.7

From the survey, the students believed that peer-interaction and class discussion helped them understand the material and to critically assess the articles. While they liked the idea of learning about nanotechnology from the journal articles, they did not rate highly the amount of journal article reading assigned. While the question did not ask specifically whether the amount should be higher or lower, the instructor is under the impression that they would prefer less amount of reading. One comment from a student from the written answer section of the survey seemed appropriate. This student noted that some additional guidance on what to look before should be given out prior to reading the articles. As this was likely the first experience that most of the students had with reading extensively from the scholarly literature, the responses here are quite understandable. Concept Inventories. A concept inventory (CI) is an assessment instrument used to gauge student conceptual understanding of a specific body of knowledge, typically the key concepts in a course. The force concept inventory developed for a physics course is often credited with pioneering this assessment method in the STEM fields.20 A CI instrument can uncover student misconceptions and thus can be helpful in improving the curriculum. Recently, concept inventories have been developed for various electrical engineering courses.21,22 Our interest in

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developing concept inventories for microelectronics courses is to assess the impact of various pedagogical methods on student conceptual learning. The strategies used to develop the tests will be detailed in a separate paper.23 For our VLSI Design course, a basic concept inventory test covering the background electronics knowledge the students should have entering the course was given in the first class. Two other CI tests covering material from the course itself were administered at the midpoint and end of the semester. The CI test given at the midpoint is of interest here as four of the eight multiple choice questions were related to issues with shrinking device geometries down to nanometer-scale dimensions. On those four questions, the students selected the correct answer an average of 58.5% of the time, while on the other four questions, the correct answer was selected 59.3% of the time. At least we can observe that there is equal room for improvement in the student conceptual understanding in both cases. Exam and Project. As the introduction of nanoelectronics material into the VLSI Design course is at the developmental stage, we kept the actual contribution to the student’s final grade to a modest level. On the final exam, eight true/false questions were given that covered this material. On average, the students answered 85.4% of these questions correctly. The overall average score on the final exam was 75.3%. However, it is difficult to conclude that the students have a better understanding of the nanoelectronics-based material compared with the conventional microelectronics material as the other questions involved more in-depth problem solving. For the course project, the students were asked to select a circuit from a CMOS logic family discussed in class and simulate it at a nanoscale technology node using a predictive technology model.24 An important part of the project required the students to interpret their simulation results in light of the discussions in class on technology scaling, and to assess how well the particular logic family would perform when implemented on a nanoscale process. Overall, this component of the project was rated at an average of 7.53/10. From the course project, the instructor’s overall impression is that the students have a basic grasp of the issues involved in designing circuits with nanoscale technologies, but this question involves the ability to analyze and synthesize information at a higher level than typical assignments. As such, it is not surprising that this component could have been done better. Discussion of Results In this section, steps to improve the course based upon the assessment results are considered. From the class surveys, we can observe that the students generally see the benefit of our implementation strategy for using journal articles and active learning methods to study nanotechnology-based material in the VLSI Design class. There are two things we would do to improve the educational impact of the journal readings. First, give the students an outline or list of questions to consider when reading the articles beforehand. As this is the first time they have experience reading scholarly works, the students need some additional guidance, especially for the more research-oriented articles. Second, a short quiz should be given before the journal articles are discussed in class to encourage the students to read them more thoroughly. The use of peer interaction exercises worked well and the students generally seemed to appreciate the time spent working through active learning exercises in class. The use of more neighbor-interaction thought questions spread throughout the lecture would keep the students attention and interest in the lecture.

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From both the student self-assessment and the concept inventory tests, there are indications that the students have an understanding of the nanoelectronics material at only a basic level. To improve upon this, some specific assignments will be planned in future course offerings which allow reinforcement of the material that is learned in class. In particular, it is desirable to include some assignments using computer simulation tools. This, however, can be a challenge. To make room for introducing the nanoelectronics material this past semester, less class time was spent on introducing and learning the basic computer-aided design (CAD) tools for designing VLSI circuits. These CAD tools are typically an important component of the VLSI Design course. A less comprehensive package of CAD tools was selected for this class as the students were required to learn the tools by working through tutorials mostly outside of class time. Some students commented on the end of the semester survey that they found it difficult to learn to use the tools without much class time devoted to it. This may account, in part, for the low rating assigned to the course project in Table VII. Finding and utilizing CAD software that can cover both the essentials of VLSI Design and nanoscale device engineering would be ideal. This, in fact, is currently a major issue in the microelectronics industry, so it remains to be seen what tools will be developed and made available in the near future. Summary and Conclusions This paper has summarized our initial efforts to introduce nanotechnology into a standard Introduction to VLSI Design class for undergraduate students. Readings from the relevant journal articles and use of active learning methods in class proved to be effective for introducing nanoelectronics in the classroom. The students were periodically surveyed to gauge their attitudes to the new material and to solicit feedback on improving the course. The development of concept inventory (CI) tests were utilized to assess conceptual understanding. Future offerings will attempt to refine the use of the CI tests and plan intervention strategies to remedy any perceived misconceptions in student understanding. Finding and using cutting-edge software that will allow the students to simulate and design with both nanoscale CMOS and upcoming nanotechnology-based devices will be a priority for future offerings of this course. In the coming year, we will also consider integrating nanotechnology into other courses with microelectronics themes. This includes our senior electives in Field Programmable Gate Array (FPGA) Design and Radio-frequency (RF) CMOS Integrated Circuit Design. Acknowledgement Thanks to Kathryn McAdams for doing a terrific job in entering all the assessment data for this study.

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References 1. M. C. Roco, “The long view of nanotechnology development: the National Nanotechnology Initiative at 10

years,” J. Nanopart. Research, vol. 13, pp. 427–445, 2011. 2. M. Mendelson et al., “Teaching and Evaluating a New Nanotechnology Undergraduate Course,” American

Society for Engineering Education Annual Conference & Exposition, 2004. 3. M. Al-Haik et al., Introducing Nanotechnology to Mechanical and Civil Engineering Students Through

Materials Science Courses, Journal of Nano Education, vol. 2, pp. 13–26, 2010. 4. D. Pai et al., Introducing Nanotechnology into Traditional Engineering Curricula, 9th International Conference

on Engineering Education, Session T1D, pp. 11-16, 2006. 5. M. Uddin and A. R. Chowdhury, “Integration of Nanotechnology into the Undergraduate Enginnering

Curriculum,” International Conference on Engineering Education, Session 8B2, pp. 6-9, 2001. 6. N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th edition, Pearson–Addison-Wesley, 2011.

7. M. Prince, “Does Active Learning Work? A Review of the Research,” J. Engr. Education, vol. 93, no. 3, pp. 223-231, 2004.

8. R. F. Pease and S. Y. Chou, “Lithography and Other Patterning Techniques for Future Electronics,” Proceedings of the IEEE, vol. 96, no. 2, pp. 248-270, Feb. 2008.

9. D. Helms, E. Schmidt, and W. Nebel, “Leakage in CMOS Circuits – An Introduction,” Proceeding of the 36th European on Solid-State Device Research Conference (ESSDERC 2006), pp. 399-402, 19-21 Sept. 2006.

10. G. Bourianoff, “The future of nanocomputing,” IEEE Computer , vol. 36, no. 8, pp. 44- 53, Aug. 2003. 11. M. Haselman and S. Hauck, “The Future of Integrated Circuits: A Survey of Nanoelectronics,” Proceedings of

the IEEE, vol. 98, no. 1, pp. 11-38, Jan. 2010. 12. S. J. Wind et al.,“Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes,” Applied

Physics Letters, vo1. 80, no. 20, May 20, 2002. 13. B. Liu et al., “Intel LVS logic as a combinational logic paradigm in CNT technology,” 2010 IEEE/ACM

International Symposium on Nanoscale Architectures (NANOARCH), pp. 77-81, 17-18 June 2010. 14. M. J. Flynn, P. Hung, K. W. Rudd, “Deep submicron microprocessor design issues,” IEEE Micro, vol. 19, no. 4,

pp. 11-22, Jul-Aug 1999. 15. C. Constantinescu, “Impact of deep submicron technology on dependability of VLSI circuits,” International

Conference on Dependable Systems and Networks ( DSN 2002), Proceedings, pp. 205-209, 2002. 16. A. Garcia-Ortiz, D. Gregorek, C. Osewold, “Optimization of interconnect architectures through coding: A

review,” Saudi International Electronics, Communications and Photonics Conference (SIECPC), 2011. 17. A. Ejlali, B. M. Al-Hashimi, P. Rosinger, S. G. Miremadi, L. Benini, “Performability/Energy Tradeoff in Error-

Control Schemes for On-Chip Networks,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 1, pp. 1-14, Jan. 2010.

18. P. P. Pande, A. Ganguly, B. Belzer, A. Nojeh, A. Ivanov, “Novel interconnect infrastructures for massive multicore chips — an overview,” IEEE International Symposium on Circuits and Systems (ISCAS 2008), pp. 2777-2780, 18-21 May 2008.

19. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-Power CMOS Digital Design,” IEEE J. of Solid-State Circuits, vol. 27, no. 4, pp. 473-484, April 1992.

20. D. Hestenes, M. Wells, G. Swackhamer, “Force Concept Inventory,” The Physics Teacher, vol. 30, pp. 141-151, 1992.

21. M. F. Simoni, M. E. Herniter, and B. A. Ferguson, “Concepts to Questions: Creating an Electronics Concept Inventory Exam,” ASEE Annual Conference & Exposition, Session 1793, 2004.

22. K. E. Wage, J. R. Buck, C. H. G. Wright, and T. B. Welch, “The Signals and Systems Concept Inventory,” IEEE Trans. on Education, vol. 48, no. 3, pp. 448- 461, Aug. 2005.

23. D. H. K. Hoe, “Developing a concept inventory for microelectronic courses,” submitted to the Frontiers in Education Conference (FIE), October 2013.

24. W. Zhao and Y. Cao, “New generation of Predictive Technology Model for sub-45nm early design exploration,” IEEE Trans. on Electron Devices, vol. 53, no. 11, pp. 2816-2823, Nov. 2006

Page 23.821.15