ABSTRACT

Electric power distribution system is an important part of electrical power systems in delivery of electricity to consumers. Automation in the distribution field allows utilities to implement flexible control of distribution systems, which can be used to enhance efficiency, reliability, and quality of electric service. The main aim of this project is to protect the transformer from failing or damage having applied more loads on it & share these over loads with another transformer.ie, this project provides a secured environment for the transformers from over loads which are distributing power to certain regions. These transformers with over load are protected by sharing these over loads with another transformer. Here we are using two transformers TF1 (Main transformer) and TF2 (sharing transformer). The transfers switch senses when utility power increases more than rating of transformer1, then start up the transformer TF2 which acts as a sharing transformer. The transfer switch continues to monitor utility power, and when it is less than the rating of TF1 then sharing transformer will cutoff from load and switches the load from the Transformer TF2 back to the Main transformer TF1. Once the Transformer TF2 is disconnected, it goes through a cool-down routine and is automatically shut down. The present system is designed around two transformers.These two transformers are connected with the relay which is controlled by the embedded controller. The loads are connected to the main line (TF1) and as well as to the TF2 through relay.

1

Acknowledgement

I express my hearty thanks to beloved chancellor, Janab Dr. A.P.Majeed Khan and also to pro-vice chancellor Prof. Dr. N.Chandrashekhar ,B.E., Ph.D.(IIT.Madras) for giving the consent to do this project work.

I express my hearty thanks to Head Of the Department,Dr.L.Padma Suresh B.E,M.E, PhD, for having accepted this project and for the timely help rendered.

I express deep sense of gratitude and sincere thanks to my Internal guide Prof.F.Shamila Msc(Engg),Department of Electrical and Electronics Engineering,Noorul Islam University.

I enunciate my thanks to professors K.Subramaniam B.E,M.E, D.M.Mary Sythia Regis Prabha, M.E, (PhD)for their guidance to complete the project.

At last I extend my sincere thanks to all other teaching and non-teaching staff members of Electrical and Electronics Engineering department and my Friends who went out their way and took pains to help me in making this project a grand success.

Above all, I thanks my parents who are responsible for what I am today.

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TABLE OF CONTENT

CHAPTER NO

TITLE PAGE NO

ABSTRACT 1

1 INTRODUCTION 10

2 BLOCK DIAGRAM DESCRIPTION

11

2.1 BLOCKDIAGRAM

11

2.2 OVERVIEW OF EMBEDDED SYSTEM

11

2.3 HARDWARE USED

12

2.4 SOFTWARE USED

13

2.5CIRCUIT DIAGRAM

13

3 MICROCONTROLLER

15

3.1 AVR ATMEGA 16 MICROCONTROLLER

15

3.2 FEATURES

15

3.3 PIN DIAGRAM

18

3.4 OVERVIEW

19

3.5 BLOCK DIAGRAM

19

3.6 PIN DESCRIPTION 204 ARCHITECTURAL OVERVIEW

23

4.1BLOCK DIAGRAM OF THE 23

3

AVR ARCHITECTURE 4.1.1 ALU

25

4.1.2 STATUS REGISTER

25

4.1.3 GENERAL PURPOSE REGISTER

27

4.1.4 X REGISTER,Y REGISTER, Z REGISTER

29

4.1.5 STACK POINTER

29

4.1.6 RESET AND INTERRUPT HANDLING

30

4.2 INTERRUPT RESPONSE TIME

32

4.3 IN SYSTEM REPROGRAMMABLE FLASH PROGRAM

32

4.4 CRYSTAL OSCILLATOR 33

4.4.1TIMER/COUNTER OSCILLATOR

34

4.5 SYSTEM CONTROL AND RESET

34

4.5.1RESETTING THE AVR

34

4.5.2RESET SOURCES

35

4

4.6 LCD

35

4.7 POWER SUPPLY

36

4.7.1 7805 VOLTAGE REGULATOR

36

4.7.2 BRIDGE RECTIFIER

38

5 TRANSFORMER 39

5.1 PRINCIPLE OF TRANSFORMER

39

5.2 CURRENT SENSOR

39

5.3 HALL EFFECT BASE LINEAR CURRENT SENSOR

40

5.3.1FEATURE 40

5.3.2FUNCTIONAL DESCRIPTION

41

5.4 FUNCTIONAL BLOCK 43

5.5 DESIGN FEATURES OF TRANSFORMER WITH

RATING110KV/11KV,10MVA

44

5.6 WHY IS CURRENT SENSING IMPORTANT

44

5.6.1 TYPES OF CURRENT SENSING

44

5

5.6.2 INPUT COMMON-MODE VOLTAGE

45

5.6.3HIGH-SIDE VERSUS SIDE

CURRENT SENSING

46

5.7 DIRECTIONALITY 48

5.8 CURRENT SENSOR OUTPUT

49

5.9 RELAY 52

6 LCD DISPLAY 55

6.1 NET MEDIA 2x16 SERIAL LCD

DISPLAY MODULE

55

6.2 PINOUT 56

6.3 INTERFACING 57

6.4 APPLICATIONS 58

7 CONCLUSION 59

7.1 FUTURESCOPE 59

REFERENCE 60

6

7

LIST OF FIGURES

FIGURE NO. TITLE PAGE NO.

2.1 BLOCK DIAGRAM 11

2.2 CIRCUIT DIAGRAM 13

3.1 PIN DIAGRAM 18

3.2 BLOCK DIAGRAM 19

4.1 BLOCK DIAGRAM OF THE

AVR ARCHITECTURE 23

4.2 STATUS REGISTER 26

4.3 STRUCTURE OF 32 GENERAL

PURPOSE WORKING REGISTER 28

4.4 X REGISTER,Y REGISTER,

Z REGISTER 29

4.5 STACK POINTER 30

4.6 PROGRAM MEMORY MAP 33

4.7 CRYSTAL OSCILLATOR

CONNECTIONS 34

4.8 LCD 35

4.9 7805 VOLTAGE REGULATOR 37

5.1 HALL EFFECT BASE LINEAR

CURRENT SENSOR 40

8

FIGURE NO. TITLE PAGE NO.

5.2 FUNCTIONAL DESCRIPTION 42

5.3 FUNCTIONAL BLOCK 43

5.4 DEFINITION OF I/P COMMON

MODE VOLTAGE 46

5.5 LOW-SIDE CURRENT SENSING 47

5.6 HIGH-SIDE CURRENT SENSING 48

5.7 DIRECTIONALITY 49

5.8 CURRENT O/P GSM 50

5.9 VOLTAGE O/P CSM 51

5.10 DIGITAL 0/P CSM 52

5.11 ELECTRICAL RELAY 53

6.1 LCD 55

6.2 PINOUT 56

6.3 INTERFACING 57

9

CHAPTER 1

1.INTRODUCTION

Automatic load sharing of transformers is an integral part of the power

control process, allowing smooth and immediate transfer of electrical current

between multiple sources and the load. Here we are using two transformers TF1

(Main transformer) and TF2 (sharing transformer). The transfers switch senses

when utility power is increases more than rating of transformer1, then starts up the

transformer TF2 which acts as a sharing transformer. The transfer switch continues

to monitor utility power, and when it is less than the rating of TF1 then sharing

transformer will cutoff from load and switches the load from the Transformer TF2

back to the Main transformer TF1. Once the Transformer TF2 is disconnected, it

goes through a cool-down routine and is automatically shut down.

The objective of the present project “Automatic load sharing of

Transformers” is to satisfy the above needs with an extent. The present system is

designed around two transformers. One transformer (TF1) is used as the main

supply and the other transformer (TF2) is used as sharing transformer. These two

transformers are connected with the relay which is controlled by the embedded

controller. The loads are connected to the main line (TF1) and as well as to the TF2

through relay.Initially TF1 is connected to the load, the loads run with this power.

If the load on transformer 1 is increase beyond its rating then controller will find

out that and it will connect the sharing transformer parallel to the main

transformer. When we connect two transformers in parallel load will be shared by

two transformers equally. And controller will continuously monitor the current

flowing in the load and when the load current decreases below the TF1 rating then

it will turn off the sharing transformer.

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CHAPTER 2

BLOCK DIAGRAM DESCRIPTION

2.1BLOCK DIAGRAM

11

MICROCONTROLLER

LCD

MAIN TRANSFORMERTF1

CB

SHARING TRANSFORMER TF2

CB

LOAD

RELAY1

RELAY2CURRENT SENSORADC

POWERSUPPLY

G

2.2OVERVIEW OF EMBEDDED SYSTEM

In Future, Computer is going to rule this world. If the application of

computer is considered, the application of computer can be classified into two. One

is the Administration and the other is the Technical. So far it is concentrated only

in administration. In the forth coming year, computers will be doing all the work

and the automation is going to be the HERO in the next era. If the role of computer

in the industry in technical environment is considered, so far it is being used for

normal purposes. But it is not necessary to use such a BIG Brain for small

applications in an industry. Because it can’t fully depend on computer, since

Windows like operating systems will hang up frequently, if so, the industry will be

shut down. So, to overcome this kind of problem, Scientist came out with a new

concept called Embedded System.

2.3HARDWARE USED:

● MICRO CONTROLLER ATMEGA16

● POWER SUPPLY

● TRANSFORMERS

● RELAY

● LCD DISPLAY

12

2.4SOFTWARE USED:

● WINAVR

● Embedded C

2.5CIRCUIT DIAGRAM

fig 2.2

13

Here in the circuit diagram the central component is the microcontroller ie, ATMEGA 16.To its right is the LCD connection along with a capacitor.The LCD is used for displaying purpose which will display whether the transformer 2 is ON or in OFF condition.To the left of microcontroller X1 crystal is connected which is used for providing a clock for the microcontroller.R1 is the pull up resistor which is used for maintaining the rated voltage of microcontroller.C1 and C2 are the two capacitors which are used to create a spike or noise for the crystal and also it is used for stabilization purpose.R2 is the pull up resistor and R3 is the pull down resistor.RL1 and RL2 are the two relays used here. The resistors along with transistors are used for the switching of the relays. Here one voltage regulator U 7805 is used which is used for the voltage regulation purpose. And the capacitor C4 is used as the rectifier for the LED as it requires only low voltage. From the relay connection to the transformer is going . Under normal working condition the relay RL1 is closed and RL2 is in open condition.Therefore only transformer 1 is in working condition.Whenever there is any overloading the relay RL2 is also closed and both transformers get connected parallelly and sharing loads equally. The current sensor continues monitor the utility power and whenever it decreases beyond the rating of TF1 it will sense and microcontroller will send signal for opening RL2 and TF1 will be working alone.

14

CHAPTER 3

MICROCONTROLLER

3.1 AVR ATMega16 Microcontroller

ATmega16 is an 8-bit high performance microcontroller of Atmel’s Mega AVR family with low power consumption. Atmega16 is based on enhanced RISC (Reduced Instruction Set Computing) architecture with 131 powerful instructions. Most of the instructions execute in one machine cycle. Atmega16 can work on a maximum frequency of 16MHz.ATmega16 has 16 KB programmable flash memory, static RAM of 1 KB and EEPROM of 512 Bytes. The endurance cycle of flash memory and EEPROM is 10,000 and 100,000, respectively. ATmega16 is a 40 pin microcontroller. There are 32 I/O (input/output) lines which are divided into four 8-bit ports designated as PORTA, PORTB, PORTC and PORTD.ATmega16 has various in-built peripherals like USART, ADC, Analog Comparator, SPI, JTAG etc. Each I/O pin has an alternative task related to in-built peripherals.The device supports throughput of 16 MIPS at 16 MHz and operates between 4.5-5.5 volts. By executing instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz, balancing power consumption and processing speed

3.2Features

• High-performance, Low-power Atmel® AVR® 8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

15

– 16 Kbytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1 Kbyte Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG

Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Four PWM Channels

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Programmable Serial USART

– Master/Slave SPI Serial Interface

16

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,

Standby

and Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 2.7V - 5.5V for ATmega16L

– 4.5V - 5.5V for ATmega16

• Speed Grades

– 0 - 8 MHz for ATmega16L

– 0 - 16 MHz for ATmega16

• Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L

– Active: 1.1 mA

– Idle Mode: 0.35 Ma

– Power-down Mode: < 1 μA

17

3.3PIN DIAGRAM

fig 3.1

18

3.4 Overview:

The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

3.5 Block Diagram

fig 3.2

19

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes an PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-Sysem Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,and evaluation kits.

3.6 Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter. Port

A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.

20

Port pins can provide internal pull-up resistors (selected for each bit). The Port A

output buffers have symmetrical drive characteristics with both high sink and

source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, they will source current if the internal pull-up resistors are activated.

The Port A pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port B output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port B pins

that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition

becomes active, even if the clock is not running. Port B also serves the functions of

various special features of the ATmega16

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port C output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port C pins

that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition

becomes active, even if the clock is not running. If the JTAG interface is enabled,

the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be

activated even if a reset occurs. Port C also serves the functions of the JTAG

interface and other special features of the ATmega16

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up

resistors (selected for each bit). The Port D output buffers have symmetrical drive

characteristics with both high sink and source capability. As inputs, Port D pins

that are externally pulled low will source current if the pull-up resistors are

activated. The Port D pins are tri-stated when a reset condition becomes active,

21

even if the clock is not running. Port D also serves the functions of various special

features of the ATmega16 .

RESET Reset Input. A low level on this pin for longer than the minimum pulse

length will generate a

reset, even if the clock is not running. Shorter pulses are not guaranteed to generate

a reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock

operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It

should be externally

connected to VCC, even if the ADC is not used. If the ADC is used, it should be

connected to VCC through a low-pass filter.

AREF AREF is the analog reference pin for the A/D Converter.

22

CHAPTER 4

Architectural Overview

4.1Block Diagram of the AVR Architecture

fig4.1

23

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register file, the operation is executed, and the result is stored back in the Register file – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-register, Y-register and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash Memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine

24

(before subroutines or interrupts are executed). The Stack Pointer – SP – is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.

The I/O memory space contains 64 addresses which can be accessed directly, or as the Data Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has Extended I/O space from $60 - $FF in SRAM.

4.1.1ALU

Arithmetic Logic Unit :The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

4.1.2Status register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The AVR status Register – SREG – is defined as:

25

fig 4.2

The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in software with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.

• Bit 4 – S: Sign Bit, S = N ⊕V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics.

• Bit 2 – N: Negative Flag

26

The Negative Flag N indicates a negative result in an arithmetic or logic operation.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation.

4.1.3General Purpose Register

The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

The structure of the 32 general purpose working registers in the CPU.

27

fig 4.3

Most of the instructions operating on the Register file have direct access to all registers, and most of them are single cycle instructions. As shown in figure 4.3, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

4.1.4X register, y register, z register

28

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are described in figure

fig 4.4

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details).

4.1.5Stack pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with

29

the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

fig 4.5

4.1.6Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt vectors. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0.

30

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts.

4.2Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles, the program vector address for the actual interrupt handling routine is executed. During this 4-clock cycle period, the

31

Program Counter is pushed onto the Stack.The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes four clock cycles. During these 4-clock cycles,the program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

4.3In-System Reprogrammable Flash Program

Memory The ATmega128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega128 Program Counter (PC) is 16 bits wide, thus addressing the 64K program memory locations. Constant tables can be allocated within the entire program memory address space. Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing”.

Program Memory Map

32

fig 4.6.

4.4Crystal oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator. Either a quartz crystal or a ceramic resonator may be used.

Crystal Oscillator Connections

33

fig 4.7

4.4.1Timer/Counter Oscillator

For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. No external capacitors are needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended.

4.5System Control and Reset

4.5.1Resetting the AVR

During Reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the interrupt vectors are in the Boot section or vice versa.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts.

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4.5.2Reset Sources

The ATmega128 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system.

4.6LCD

fig 4.8

This is the first interfacing example for the Parallel Port. This example doesn't use

the bi-directional feature found on newer ports, thus it should work with most, if

not all Parallel Ports. These LCD Modules are very common these days, and are

quite simple to work with, as all the logic required running them is on board. The

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LCD panel's Enable and Register Select is connected to the Control Port. The

Control Port is an open collector / open drain output. While most Parallel Ports

have internal pull-up resistors, there is a few which don't. Therefore by

incorporating the two 10K external pull up resistors, the circuit is more portable for

a wider range of computers, some of which have no internal pull up resistors. We

make no effort to place the Data bus into reverse direction. This will cause no bus

conflicts onthe data lines. As a result we cannot read back the LCD's internal Busy

Flag which tells us if the LCD has accepted and finished processing the last

instruction. This problem is overcome by inserting known delays into our program.

The 10k Potentiometer controls the contrast of the LCD panel. A bench power

supply can be used to set 5v or use an onboard +5 regulator.

4.7POWER SUPPLY

4.7.1 7805 VOLTAGE REGULATOR The78xx (also sometimes known as

LM78xx) series of devices is a family of self-contained fixed regulator integrated.

The 78xx family is a very popular choice for many electronic circuits which

require a regulated power supply, due to their ease of use and relative cheapness.

When specifying individual ICs within this family, the xx is replaced with a two-

digit number, which indicates the output voltage the particular device is designed

to provide (for example, the 7805 has a 5 volt output, while the 7812 produces 12

volts). The 78xx line are positive voltage regulators, meaning that they are

designed to produce a voltage that is positive relative to a common ground. There

is a related line of 79xx devices which are complementary negative voltage

regulators. 78xx and 79xx ICs can be used in combination to provide both positive

and negative supply voltages in the same circuit, if necessary.78xx ICs have three

terminals and are most commonly found in the TO220 form factor, although

smaller surface-mount and larger TO3 packages are also available from some

36

manufacturers. These devices typically support an input voltage which can be

anywhere from a couple of volts over the intended output voltage, up to a

maximum of 35 or 40 volts, and can typically provide up to around 1 or 1.5 amps

of current (though smaller or larger packages may have a lower or higher current

rating).

fig 4.9

4.7.2BRIDGE RECTIFIER

A diode bridge is an arrangement of four diodes in a bridge configuration that

provides the same polarity of output for either polarity of input. When used in its

most common application, for conversion of an alternating current (AC) input into

direct current a (DC) output, it is known as a bridge rectifier. A bridge rectifier

provides full-wave rectification from a two-wire AC input, resulting in lower cost

and weight as compared to a rectifier with a 3-wire input from a transformer with a

center-tapped secondary winding.

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CHAPTER 5

TRANSFORMER

5.1PRINCIPLE OF THE TRANSFORMER

38

A transformer is a static (or stationary) piece of apparatus by means of which

electric power in one circuit is transformed into electric power of same frequency

in another circuit.It can raise or lower the voltage in a circuit but with a

corresponding decrease or increase in current. The physical basis of a transformer

is mutual induction between two circuits linked by a common magnetic flux . In its

simplest form ,it consist of two inductive coils which are electrically separated but

magnetically linked through a path of low reluctance .The two coils posses high

mutual inductance . If one coil is connected to a source of alternating voltage, an

alternating flux is set up in the laminated core , most of which is linked with the

other coil in which it produces mutually induced e.m.f. If the second coil circuit

is closed , a current flows in it and so electric energy is transferred from first coil to

the second coil .The first coil ,in which electric energy is fed from the a.c supply

mains, is called primary winding and the other from which energy is drawn out is

called secondary winding .

5.2Current sensor

A current sensor is a device that detects electrical current (AC or DC) in a wire, and generates a signal proportional to it. The generated signal could be analog voltage or current or even digital output. It can be then utilized to display the measured current in an ammeter or can be stored for further analysis in a data acquisition system or can be utilized for control purpose. The sensed current and the output signal can be:

- AC current input

- analog output, which duplicates the wave shape of the sensed current

-BIPOLAR output, which duplicates the wave shape of the sensed current

39

-unipolar output, which is proportional to the average or RMS value of

the sensed current

-DC current input,

-unipolar, with a unipolar output, which duplicates the wave shape of the

sensed current

-digital output, which switches when the sensed current exceeds a certain

threshold

5.3Hall Effect Base Linear Current Sensor

5.3.1Features

fig 5.1

- Diameter 9.0mm conductor through hole

- Output voltage proportional to AC and DC current

- Wide sensing current range 0~100A at 5V volt

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- High sensitivity 22mV/A - Wide operating voltage range 3.0~12 V. - Low operating current 3mA - Isolation voltage 4000V - Ratiometric output from supply voltage - 23K Hz Bandwidth - Two bronze sticks for easy soldering on PCB

5.3.2Functional Description : The Winson WCS1600 current sensor provides economical and precise solution

for both DC and AC current sensing in industrial, commercial and communications systems. The unique package provodie easy implementation without breaking original system and make current sensing possible. Typical applications include motor control, load detection and management, over-current fault detection and any intelligent power management system etc.

The WCS1600 consists of a precise, low-temperature drift linear hall sensor IC with temperature compensation circuit and a diameter 8.7mm through hole. Users can use system’s own electric wire by pass it through this hole to measure passing current. This design allow system designers to monitor any current path without breaking or changing original system layout at all. Any current flowing through this hole will generate a magnetic field which is sensed by the integrated Hall IC and converted into a proportional voltage. The terminals of the conductive path are electrically isolated from the sensor leads. This allow the WCS1600 current sensor to be used in applications requiring electrical isolation without the use of opto-isolators or other costly isolation techniques and make system more competitive in cost .

41

fig 5.2

42

5.4 Function Block:

fig 5.3

43

5.5 DESIGN FEATURES OF TRANSFORMER WITH RATING 110KV/11KV,10MVA

CT ratio 1000/1 Relay 110V,1A. ADC rating reference voltage min 2.0V,max 5.0V

i/p voltage min 0V,max 5V. ATMEGA 16 max operating voltage 6.0V,DC current per i/o pin

14.0mA. LCD POWER 4.9-5.2V DC@15mA(no backlight),135mA(full

backlight).

5.6Why is current sensing important?

Knowing the amount of current being delivered to a load can be useful in a wide

variety of applications. For example, in low-power consumer products the supply

current can be monitored to understand the system’s impact on battery life. The

load current also can be used to make safety-critical decisions in over-current

protection circuits. In motor control, knowing the magnitude and direction of the

current can tell you the speed and direction of the motor. Finally, test fixtures can

be developed that monitor all supply currents to gain an understanding of system

subcomponent performance. Each of the aforementioned applications has different

design requirements with respect to common-mode voltage, directionality, and

accuracy.

5.6.1 Types of current sensing

There are two types of current sensing: direct and indirect. Indirect current sensing

is based on Ampere’s and Faraday’s laws. By placing a coil (for instance

Rogowski coil) around a current-carrying conductor, a voltage is induced across

the coil that is proportional to the current. This allows for a non-invasive

44

measurement where the sensing circuitry is not electrically connected to the

monitored system. Since there is no direct connection between the sensing circuitry

and the system, the system is inherently isolated. Indirect current sensing typically

is used for load currents in the 100A-1000A range. This type of sensing, however,

requires relatively expensive sensors and is not conducive to sensing currents on a

PCB.

 Direct current sensing is based on Ohm’s law. By placing a shunt resistor in series

with the system load, a voltage is generated across the shunt resistor that is

proportional to the system load current. The voltage across the shunt can be

measured by differential amplifiers such as current shunt monitors (CSMs),

operational amplifiers (op amps), difference amplifiers (DAs), or instrumentation

amplifiers (IAs). This method is an invasive measurement of the current since the

shunt resistor and sensing circuitry are electrically connected to the monitored

system. Therefore, direct sensing typically is used when galvanic isolation is not

required. The shunt resistor also dissipates power, which may not be desirable.

Direct current sensing typically is implemented for load currents <100A. The

remainder of this particular article series will focus on direct current sensing.

 5.6.2Input common-mode voltage Input common-mode voltage is the most

important specification when selecting a direct current sensing solution. It is

defined as the average voltage present at the input terminals of the amplifier.

Figure 5.4 depicts the definition of input common-mode voltage .

45

fig 5.4: Definition of input common-mode voltage.

 This specification is important because it limits the choice of differential

amplifiers. For example, op amps and IAs require an input common-mode voltage

within their power supplies. Difference amplifiers and CSMs, however, typically

can accommodate input common-mode voltages in excess of their power supplies.

This is useful in applications where the amplifier senses the shunt voltage in the

presence of a large common-mode voltage and must interface with a low-voltage

analog-to-digital converter (ADC). In such a scenario the amplifier and ADC can

be powered with the same supply voltage regardless of the system’s common-

mode voltage.

5.6.3 High-side versus low-side current sensing

When monitoring load current the designer can choose to place the sense resistor

either between the supply voltage (Vbus) and load, or between the load and

46

ground. The former is called high-side sensing whereas the latter is called low-side

sensing.

 Low-side sensing is desirable because the common-mode voltage is near ground,

which allows for the use of single-supply, rail-to-rail input/output op amps. The

drawbacks to low-side sensing are disturbances to the system load’s ground

potential and the inability to detect load shorts. Figure 5.5 depicts a typical low-

side sensing scenario.

fig 5.5 Low-side current sensing.

High-side sensing is desirable in that it directly monitors the current delivered by

the supply, which allows for the detection of load shorts. The challenge is that the

amplifier’s input common-mode voltage range must include the load’s supply

voltage, or Vbus. This requirement frequently necessitates the use of DAs or

dedicated CSMs, which allow for common-mode voltages outside their voltage

supply range. Figure 5.6 depicts a typical high-side sensing scenario.

47

fig 5.6 High-side current sensing.

5.7Directionality

Depending on the application, the supply current may flow either in one direction

(unidirectional) or both directions (bidirectional). Unidirectional designs are

straightforward in that the output voltage of the amplifier does not need to

distinguish direction. Bidirectional solutions have an input for a reference, or

pedestal voltage. The output of the device is then referenced to this known voltage.

Output voltages above the known reference voltage are in one direction while

output voltages below the known reference voltage are in the opposite direction.

48

 

fig 5.7 Directionality.

5.8Current Sensor Output

The output of a current sensing solution can be in the form of a current, voltage, or

digital word. Dedicated CSMs can have any of the aforementioned outputs while

op amps, DAs, and IAs have a voltage output. Current output CSMs typically

require an external gain-setting resistor (RL) as shown by the INA138/168 diagram

in Figure 5.9. This allows for flexibility in choosing the gain of the device.

Also, if the design requires driving a large capacitive load, a properly compensated external op amp can buffer the output of the CSM. However, since the gain of the device depends on the external resistor, the internal resistors must be trimmed to an absolute value, which can increase cost.

49

fig 5.9: Current output CSM.

 Voltage output CSMs integrate the gain-setting resistor and output buffer as

shown by the INA193-8 diagram in Figure 5.10. This only requires ratio-metric

trimming which is less costly than absolute trimming. The drawback is that the

devices have predetermined gains (for instance 20V/V, 50V/V, 100V/V) and the

designer does not have access to the feedback path of the buffer amplifier to

compensate for large capacitive loads.

50

 

fig 5.10: Voltage output CSM.

 Digital output CSMs have integrated programmable-gain amplifiers (PGAs) and

ADCs and report the shunt voltage as a digital word via a serial communication

protocol such as I2C or SPI, as shown by the INA219 block diagram in figure 5.11.

While this can be highly desirable for ease-of-use, the full-scale differential input

must be restricted to a range of values. Therefore, care must be taken when

selecting the value of the shunt resistor.

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fig 5.11: Digital output CSM

5.9Relay

The term relay generally refers to a device that provides an electrical connection

between two or more points in response to the application of a control signal. The

most common and widely used type of electrical relay is the electromechanical

relay or EMR.

52

fig 5.12Electrical Relay

The most fundamental control of any equipment is the ability to turn it "ON" and

"OFF". The easiest way to do this is using switches to interrupt the electrical

supply. Although switches can be used to control something, they have their

disadvantages. The biggest one is that they have to be manually (physically) turned

"ON" or "OFF". Also, they are relatively large, slow and only switch small

electrical currents.

Electrical relays however, are basically electrically operated switches that come in

many shapes, sizes and power ratings suitable for all types of applications. Relays

can also have single or multiple contacts with the larger power relays used for high

voltage or current switching being called "contactors".

53

In this tutorial about electrical relays we are just concerned with the fundamental

operating principles of "light duty" electromechanical relays we can use in motor

control or robotic circuits. Such relays are used in general electrical and electronic

control or switching circuits either mounted directly onto PCB boards or connected

free standing and in which the load currents are normally fractions of an ampere up

to 20+ amperes.

As their name implies, electromechanical relays are electro-magnetic devices that

convert a magnetic flux generated by the application of a low voltage electrical

control signal either AC or DC across the relay terminals, into a pulling

mechanical force which operates the electrical contacts within the relay. The most

common form of electromechanical relay consist of an energizing coil called the

"primary circuit" wound around a permeable iron core. This iron core has both a

fixed portion called the yoke, and a moveable spring loaded part called the

armature, that completes the magnetic field circuit by closing the air gap between

the fixed electrical coil and the moveable armature. The armature is hinged or

pivoted allowing it to freely move within the generated magnetic field closing the

electrical contacts that are attached to it. Connected between the yoke and armature

is normally a spring (or springs) for the return stroke to "reset" the contacts back to

their initial rest position when the relay coil is in the "de-energized" condition, ie,

turned "OFF".

54

CHAPTER 6

LCD Display

6.1NetMedia 2x16 Serial LCD Display Module

fig 6.1

• RS232 compatible serial interface (2400 & 9600 baudselectable)• Externally selectable serial polarities (Inverted & Non-Inverted)• Serially controllable contrast and backlight levels• 8 user programmable custom characters• 16 Byte serial receive buffer

55

6.2Pinout

Power and communications connections are made via header J5. Jumper

connections J1 and J2 are used to set the modules baud rate and display type.

Connection JP1 connects the serial module to the LCD, header JP14 is for 2x8pin style LCD modules.

fig 6.2

56

6.3InterfacingThe diagrams below show two common methods for interfacing the 2x16 LCD.

fig 6.3

Note: Never connect LEDSV+ to +5 on the BX-24! The BX-24 +5 regulatorcannot supply enough current to power the LCD backlight and will overheat.

57

6.4APPLICATIONS:

● Industrial areas

● Used in substation

● Shopping malls

58

CHAPTER 7

CONCLUSION

I have successfully completed the phase 2 of my project ”AUTOMATIC

SWITCHING OF CONSUMER CONNNECTION IN DISTRIBUTION

FEEDER FOR EFFICIENT LOAD DISTRIBUTION” .So by using this

project we can provide protection for the transformer and we can avoid

further losses due to overloading.

This is an efficient method for avoiding those damages. Eventhough an

additional transformer is being used its advantage is overcoming that

disadvantage.

7.1FUTURESCOPE

This project can be implemented in industrial areas to protect the transformer from

further damage and failure due to overloading and other short circuit failures.

59

REFERENCE

www.isec.com

Electrical Machines byI.J Nagrath and D.P.Kothari ,Tata McGraw-Hill

Publication.

McPherson G, and Laramore R D,”Introduction to Electrical Machines and

Transformers”,John Wiley & Sons.

Fitzerald A E, C Kingsley and S D Umans,”Electric Machinery”,4th

edition,McGraw Hill,New York.

Sharma Sanjeev,” Basic Electrical Engineering, I K International

Publication,3rd edition.

D P Kothari and I J Nagrath,” Basic electrical Engineering”, Tata McGraw-

Hill Publishing Company,Second Edition.

60