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MoreonSequentialLogic
CS64:ComputerOrganizationandDesignLogicLecture#15Winter2019
ZiadMatni,Ph.D.
Dept.ofComputerScience,UCSB
Administrative
• Lab#7– DuenextweekonWednesday3/6– PapercopytosubmitinHFH2ndFloor(CS64box)
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Administrative
• TheLast3WeeksofCS64:
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Date L# Topic Lab LabDue
2/26 14 CombinatorialLogic,SequentialLogic1 7(CL+SL) Wed.3/6
2/28 15 SequentialLogic23/5 16 FSM1
8(FSM) Wed.3/133/7 17 FSM23/12 18 DigitalLogicReview
9(Ethics) Fri.3/153/14 19 CSEthics&Impact
FinalExamReview
LectureOutline
• MoreonSequentialLogic
• Classexercises
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TheGatedDLatch• ThegatedD-Latchisverycommonlyusedinelectroniccircuits
incomputerhardware,especiallyasaregisterbecauseit’sacircuitthatholdsmemory!
WhateverdatayoupresenttotheinputD,
theD-Latchwillholdthatvalue(aslongasinputEis0)
YoucanpresentthisvaluetooutputQassoonasinputEis1.
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DE
EnablingtheLatchSynchronously:TheClockedDLatch
• IfyouapplyasynchronousclockoninputE,yougetaclockedDlatch.
• Aclockisaninputthatcyclesfrom1to0,thenbackto1againinasettimeperiod– e.g.:ifaclockinputcyclesthis
inaperiodof1ms,wecallita1MHzclock(1Hz=1/1second)
• Note1:WhenCLKis0,bothSandRinputstothelatchare0too,sotheQoutputholdsitsvaluewhateveritis(Q=Q0)
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D
CLK
SR
• Note2:WhenCLKis1:ifD=1,thenQ=1,ifD=0,thenQ=0
ClockedDLatchasDigitalSampler
• Thisclockedlatchcanbeusedasa“programmable”memorydevicethat“samples”aninputonaregularbasis
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DCLK
TheClockedDLatchByAnyOtherName…
• Observinginputandoutput“waveforms”
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DCLK
SR
DClockedLatch
DCLK
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DClockedLatch
DCLK
TheJoysofSampling…
• Samplingdatainaperiodicwayisadvantageous– Icanstartdesigningmorecomplexcircuitsthatcanhelpmedosynchronouslogicalfunctions• Synchronous:in-time
• VeryusefulinpipeliningdesignsusedinCPUs– Pipelining:atechniquethatallowsCPUstoexecuteinstructionsmoreefficiently–inparallel
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Instructionfetch,decode,execute,memoryaccess,registerwrite
TheMostEfficientWaytoSampleInputs
• Insteadofsamplingtheinputtothelatchusingaleveloftheclock…– Thatis,whentheclockis“1”(or“0”)
• …sampletheinputattheedgeoftheclock– Thatis,whentheclockistransitioningfrom0à1,calledarisingorpositiveedge(oritcouldbedonefrom1à0, thefallingedgea.k.anegativeedge)
– Why??
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TheD-FF
• Whentheinputclockedgeisrising,theinput(D)iscapturedandplacedontheoutput(Q)– Risingedgea.k.apositiveedgeFF– SomeFFarenegativeedgeFF(captureonthefallingedge)
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D-FF
D
>CLK
Latchesvs.FFs• Latchescapturedataonanentire1or0oftheclock• FFscapturedataontheedgeoftheclock
– Thisexampleshowsthepositive(0à1)edgeused
Latchout
FFout
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FFsgiveoutless“glitchy”outputs
AnImprovementontheLatch:TheDFlip-Flop
Don’tworryaboutthecircuitimplementationdetails,butunderstandtheuse!TheDFlip-Floponlychangestheoutput(Q)intotheinput(D)atthepositiveedge(the0à1transition)oftheclock
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DFlip-Flop(D-FF)
D>CLK
DGatedLatch
DCLK
Asopposedto:
Notethe(slight)differenceinthe2symbols…
PopularUsesforD-FFs
• Counter
• Serial-to-Parallelconverter
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Again,don’tworryaboutthecircuitimplementationdetails,butunderstandtheuses!
ClassExercise1
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ClassExercise2
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D QClk Q
A
B
C FClk
GivenwaveformsforA,B,C,andClk(seeblackboard),determinetheoutputwaveformforF
ClassExercise3
• Let’sdesigna3-bitcounterusingD-FFsandlogicgates.
• What’sneeded:– Thiscounts000à001à010à…à111à000
• i.e.from0to7andthenloopsagainto0,etc…
• Todescribethisbehavior,let’sstartwithaT.T.– We’llutilizeK-Maps,ifneededtofigureoutwhatthe“nextstates”looklikebasedon“currentstates”
– We’lltranslatethatintoadigitalcircuitdesign
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YOURTO-DOs
• Lab7– DuebackonWednesday– Papercopy–notelectronic– DropoffintheCS64BOXinHFH2ndFloor
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