Digital Electronics (ED)digsys.upc.es/ed/ED/grups_classe/09-10-q1/files/ED_09-10_Q1_class... · Designing simple sequential systems or Finite State Machines (FSM) using the canonical

Digital Electronics (ED) Detailed sessions outline

S1 Introduction MI-1

Chapter 1 COMBINATIONAL CIRCUITS

UNIT 1-1

- Course presentation. Important documents and organization.

Syllabus. Professors. Classes’ timetable. The intranet and the ED webpage. Exercises. The aim of the

application project. Student assessment and cooperative groups. Digital circuit simulation programs

The career of the telecommunications engineer.

Cooperative learning. The basics of the method and why we want to work in teams.

Organizing cooperative base groups:

- Heterogeneous

- Groups of 3 students

- Students must organize an extra cooperative meeting outside the classroom every week for the

whole course (sessions C)

- It is very recommended to bring a portable PC per group to the classroom

- Al the exercises must comply with the quality criteria1

Basic concepts of digital electronics: Signals and systems, digital circuits and systems. Combinational

circuits and sequential systems. Analysis and design concepts. The ED roadmap for any exercise:

a) Specifications

b) Implementation or development

c) Simulation

d) Verification

UNIT 1-2

- Number systems: binary (radix-2 or base 2), octal (radix-8), hexadecimal (radix-16),

decimal (radix-10)

NOTES:

Proposal of the EX12: An exercise about number systems, binary codes and basic arithmetic in radix-2

(Minimum 1)

1 A document defining the quality criteria is available in the ED web.

2 Most of the exercises will be proposed when opening sessions A or B. Furthermore, problem

descriptions will be posted in the web site some days before the date of proposal to help you check or

print beforehand what will be discussed in classroom.

ED COURSE OUTLINE http://epsc.upc.edu/projectes/ed/

2

S2 Working with number systems: from

base to base

MI-1

Continuation of EX1

Practicing with number systems: Concept map for representing numbers in several radix systems

NOTES:

Arranging the definitive cooperative base groups.

The most important thing here is the agenda and the timetable for each group member: The three students

must have every week a coincident pair of hours for developing sessions C out of the classroom.

Note here your scheduled time for every week sessions C: _____________________

(for example: we’ll have a meeting every Thursday from 17:00 to 19:00 in the library)

My cooperative group: UPC e-mail address3

__________________________________________ ___________________________________

__________________________________________ ___________________________________

__________________________________________ ___________________________________

3 You must activate your institutional email address ([email protected]) in order to

communicate with your instructor


3

S3 Operations in binary for signed and

unsigned numbers

MI-1

UNIT 1-3

Basic arithmetic in radix-2

� Addition

� Two’s complement encoding (Ca2) (signed integers)

� Subtraction

� Multiplication and division, etc.

UNIT 1-13 How does a virtual laboratory work?

Introducing Proteus-VSM and the simulation of digital circuits (Demonstration)

Integrated development environment for CAD or EDA

Schematics capture and SPICE-based simulation of digital and analogue circuits

Library of components, models and graphic symbols

Stimulus files (test vectors), batch and interactive simulation

Simulation examples

NOTES:

Continuation of EX1


4

S4 Coding information in binary MI-1

UNIT 1-4

Coding information in binary

• Concept of code

• Codifying numbers: binary, Gray, BCD. Example of a position sensor: a digital encoder using

Gray code

• Codifying characters: 7-bit and 8-bit ASCII code

• Redundancy for detecting and correcting transmission errors. UPC (Universal Product Code).

Odd and even parity generator and checker.

NOTES:

Delivery of EX1


5

S5 Boole Algebra MI-2

UNIT 1-5

Logic functions and Boole Algebra

• Concepts and introduction

• Algebraic equations, truth table and Karnaugh maps for representing functions

• Basic gates and their symbols (also normalized IEEE symbols)

NOT; AND, NAND; OR, NOR; exclusive-OR (XOR) and equivalence (XNOR)

• SSI (small scale of integration) integrated circuits

• Incompletely specified functions

• Boole Algebra : laws and theorems, DeMorgan’s law

NOTES:

Proposal of the EX2: An exercise about your first digital circuit analysis and design (Minimum 2) using gates

and applying most of the concepts included in Unit 1.5 and 1.7

• Concept map: Analysis: from circuit to truth table


6

S6 Concept map: Design: from truth table

to circuit

MI-2

UNIT 1-7

Designing combinational circuits and standard blocks

• Concepts: literal, product, sum, maxterm, minterm

• Canonical forms and universal sets of gates (NOT-AND-OR, NOT-OR-AND, NAND, NOR)

• Logic diagrams and circuits

• Function minimization. Applying Karnaugh maps by zeroes or ones. Computer aided minimization

using Minilog (expresso)

• Minimizing incompletely specified functions

NOTES:

Continuation of EX2


7

S7 Logic family, voltage levels, power

dissipation, speed

MI-3

UNIT 1-6

Electrical characteristics of digital circuits

Logic levels and input-output curve. Noise margins low (NML) and high (NMH). Propagation delays and

maximum frequency of operation. Digital circuits power consumption. Fan-out. Wired-AND and open

collector. Tri-state or high impedance output. Logic families and performance comparison. Evolution of logic

families and obsolescence curve. Examples from datasheets. CMOS technology.

NOTES:

Proposal of exercise EX3: Electrical characteristics of digital circuits (Minimum 3)

VERY IMPORTANT: You have to

deliver your exercises before the deadline,

even if you haven’t answered all the

questions

Delivering improved versions of

your exercises may imply better

marks


8

S8 MI-3

UNIT 1-6 (continuation)

CMOS technology for building basic gates NOT, NOR, NAND, etc.

NOTES:


9

S9 MI-4

UNIT 1-8

• Comparison of 2/3/4 level-of-gates design with respect to the structured modular design

• Standard combinational blocks

• Multiplexers or data selectors: Definition, internal design, multiplexer expansion, commercial

chips, implementing logic functions using the method of multiplexers

UNIT 1-9

• Decoders and demultiplexers. Definition, internal design, expansion of decoders, commercial

chips, implementing logic functions using the method of decoders. 7-segment display and

other special decoders.

UNIT 1-10

• Encoders. Definition, priority encoders, internal design, encoder expansion, commercial chips,

keyboard interface.

NOTES:

Delivering of EX2.

Proposal of EX4 (Minimum 4) and selection of the application project (AP) title and specifications.

Project template and structure: Objectives, development, conclusions and references


10

S10 MI-4

Continuation of Units 1.8, 1.9, and 1.10 Designing combinational systems using any of the following

techniques:

1.- Universal set of gates (NAND, NOR, NOT-AND-OR, NOT-OR-AND)

2.- Method of multiplexers

3.- Method of decoders

NOTES:

You will be asked to solve 8 unannounced (for do not

disturb other subjects) individual controls during the

course, basically for checking how the cooperative

group is running. You must pass 7 of such controls


11

S11 MI-4

UNIT 1-11

• Standard arithmetic blocs

• Comparators

UNIT 1-12

• Binary adder and their series and fast carry-lookahead expansion

• BCD addition

• ALU’s and fast carry-lookahead generators

• Multipliers and dividers

• Parity generators and checkers

From this week, in classroom each group will solve their application project (AP). Generally, projects will use

standard combinational circuits already studied in previous lessons (from U. 1.7 – U 1.12)

NOTES:

Delivering EX3.

Group portfolio guidelines and preparation:

- Organization and table of contents

- Sample materials (exercises, controls, slides, etc.)

- accumulated study time excel graphics,

- Group and personal reflexion


12

S12 MI-4

Peer revision and assessment of the group portfolio (PO) using rubrics

NOTES:

Continuation of the EX4: A classroom jigsaw on designing combinational circuits using any of the 3 methods:

gates, multiplexers or decoders.


13

S13 Demonstration session

UNIT 1-14

VHDL for combinational circuits (Demonstration)

• Hardware descrition languages: VHDL and Verilog

• Structural and high level VHDL

• Examples

UNIT 1-15

Programmable Logic Devices: combinational PLD’s

• Introduction to the PLD’s: The GAL 22V10

• Designing logic functions using PLD’s: NOT-AND-OR

• Design example: Description (schematics or VHDL), simulation and device programming

(Demonstration)

NOTES:


14

S14 MI-4

Preliminary revision and assessment of the application project (AP). Each group will explain in the blackboard

and deliver their first approximation to the AP.

NOTES:

Delivering EX4


15

S15 Concept map: direct method for

designing sequential circuits

MI-5

Chapter 2 SEQUENTIAL SYSTEMS

UNIT 2-1

Specifying sequential systems

• General schematic for a sequential system: Direct and canonical approaches

• The concept of present and future states.

• The canonical sequential system: Mealy and Moore finite state machines (FSM)

• State diagram and timing diagram

• Synchronization of sequential systems: synchronous versus asynchronous systems

UNIT 2-2

Standard sequential blocs: 1-bit memory cell: Latches (asynchronous)

• R-S latch. Internal design using the direct method

• D (or transparent) latch with enable input. Internal design using direct and canonical

methods. N-bit transparent latches

NOTES:

Proposal of EX5 (Minimum 5) Exercises with latches and flip-flops using the direct and canonical methods


16

S16 Synchronous systems MI-5

UNIT 2-3

Standard sequential blocs: 1-bit memory cell: Flip Flops (Synchronous)

• Rising edge detection circuit and the design of a flip flop from a latch cell

• FF J-K: Internal design and applications

• FF-T (toggle)

• FF-D (data)

NOTES:


17

S17 MI-5

UNIT 2-4

Timers, clock circuits and applications

• Timer circuits

- Circuit using logic gates

- Integrated circuits 74x122 and 74x221

- Timer with the 555

• Clock circuits

- Clock using logic gates

- Quartz crystal clocks. Clock chips DS1073

- Clock using 555

NOTES:

Proposal of the EX6: Designing canonical sequential systems : FSM


18

S18 Concept map: canonical method for

designing sequential circuits

MI-6

UNIT 2-5

Designing simple sequential systems or Finite State Machines (FSM) using the canonical method

ED Methodology:

a) FSM specifications using functions tables and state and timing diagrams

b) Particularization of the general FSM structure for the given problem

c) State coding in Gray, binary, one-shot, etc.

d) Design the CS2 for generating the output functions

e) Drawing the state memory using one of the following flip-flops: D-type, JF-FF, T-FF flip-flop

f) Design the CS1 to determine the future state using transition tables and the design-table

for the type of FF selected

g) Simulate and verify the design using Proteus

NOTES:

Delivering EX5

Continuation of the EX6 on the design of canonical FSM


19

S19 MI-6

Designing simple sequential systems or Finite State Machines (FSM) using the canonical method

NOTES:

Continuation of the EX6: A classroom jigsaw on designing FSM using flip flops JK, D, or T


20

S20 Demonstration

UNIT 2-6

2.1.1 Demonstration session: VHDL for sequential systems

UNIT 2-7

2.3.3. Demonstration session: Implementing sequential systems using Programmable Logic Devices

(PLD’s)

2.3.3.1. Introduction to simple PLD (sPLD), complex PLD (CPLD), and Field Programmable Gate

Arrays (FPGA)

2.3.3.2. Example of a design and programming of a FSM into a sPLD GAL22V10

NOTES:


21

S21 MI-7

UNIT 2-8

Useful standard sequential blocs: Counters (I)

• Asynchronous counter, the idea of the 7493 chip

• Synchronous counters. Canonical design of a counter as another example of FSM

• Additional features I: reset, terminal count, up and down counting, parallel load

UNIT 2-9 Counters (II)

• Expanding counters

• BCD counters, real time counters

• Other applications: frequency-meter

NOTES:

Delivering EX6

Proposal of EX7: Designing counters and registers (minimum 7)


22

S22 MI-7

UNIT 2-10

Shift registers

• Canonical design of a shift register as another example of FSM

• Serial input - parallel output

• Parallel input – serial output

• Parallel input and output (data register)

• Universal register and expanding registers

• Register applications: serial data transmission and reception

NOTES:

Delivering EX6

Continuation of the EX7

Application project: How to implement the synchronous FSM of our project


23

S23 MI-8

UNIT 2-11

Memory integrated circuits (I)

• Introduction, structure and classifications

• RAM memories

• ROM (EPROM, EEPROM, etc.) memories

• Memory banks or memory expansion

NOTES:

Proposal of EX8: designing memory banks and logic functions using memories (Look-up tables) (minimum 8)


24

S24 MI-8

UNIT 2-12

Memory integrated circuits (II)

• Logic functions using memories ROM or EEPROM

• General architecture of a synchronous and micro-programmable FSM (CS1 and CS2 in ROM)

• Designing micro-programmable FSM

NOTES:

Continuation of the EX8


25

S25 MI-6-7-8

UNIT 2-13

Digital processor

• The concept of a digital (micro-programmable) information processor: data unit (or datapath or

operational unit) (DU) and control unit (CU). Idea of the microprocessor (and microcontroller)

• Design example: a binary multiplier as a digital processor with DU and UC

NOTES:

Delivering EX7

Application Project development. Designing the operational unit


26

S26 Demonstration

UNIT 2-14

The architecture of a microprocessor, memory and I/O

• La central process unit (CPU). Instruction set in assembler language

• Digital I/O peripherals

• Analogue-digital interface circuits D/A, A/D, V/F

•

NOTES:

Application Project development. Simulation

Portfolio assessment


27

S27

Application project

NOTES:

Delivering EX8

Application Project development. Finalizing the documentation and preparing the oral presentation


28

S28

Application Project oral presentation and documentation delivering. Self and peer assessment using a rubric

with quality criteria.

NOTES:

Documents

Digital Electronics (ED)digsys.upc.es/ed/ED/grups_classe/09-10-q1/files/ED_09-10_Q1_class... · Designing simple sequential systems or Finite State Machines (FSM) using the canonical